CN102263062A - Method for forming side walls of multiple-unit semiconductor device - Google Patents
Method for forming side walls of multiple-unit semiconductor device Download PDFInfo
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- CN102263062A CN102263062A CN2010101874175A CN201010187417A CN102263062A CN 102263062 A CN102263062 A CN 102263062A CN 2010101874175 A CN2010101874175 A CN 2010101874175A CN 201010187417 A CN201010187417 A CN 201010187417A CN 102263062 A CN102263062 A CN 102263062A
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Abstract
The invention provides a method for forming side walls of a multiple-unit semiconductor device. The method comprises the following steps: providing the multiple-unit semiconductor device without side walls, wherein the multiple-unit semiconductor device at least comprises a first component area and a second component area, and the thicknesses of grid medium layers of transistors in each component area are different; covering and depositing an insulating medium layer on the surface of each component area of the multiple-unit semiconductor device; carrying out first plasma etching on the insulating medium layer in a vertical direction, thus a first side wall is formed in the first component area; forming a mask layer on the surface of the first component area; and carrying out second plasma etching on the insulating medium layer on the surface of the second component area in the vertical direction, thus a second side wall is formed in the second component area.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly be integrated with the multiple-unit semiconductor device sidewall formation method of low pressure, high voltage device.
Background technology
Along with development of semiconductor, in integrated circuit fabrication process, the multiple-unit semiconductor device that is integrated with high pressure, low voltage component is common day by day, difference according to environment for use and condition of work, the structure of high pressure and low voltage component also has than big-difference, and for example the transistor gate oxide thickness of general low voltage component exists
Between, and high voltage device is breakdown for preventing owing to will bear bigger threshold voltage, its gate oxide thickness in addition
More than.
In the existing multiple-unit semiconductor device, when forming the transistor sidewall, adopt overall etching technics.I.e. no matter low voltage component or the equal sidewall moulding of high voltage device, Fig. 1 to figure be the sidewall formation method schematic diagram of existing multiple-unit semiconductor device.
As shown in Figure 1, provide the multiple-unit semiconductor device that does not form sidewall as yet, described multiple-unit semiconductor device comprises low voltage component district I and high voltage device district II, and wherein the thickness of transistorized thin grid oxide layer 100 is among the low voltage component district I
And the thickness of transistorized thick grid oxide layer 101 is among the high voltage device district II
A wherein side of described thick grid oxide layer 101 is also by selective oxidation technology (LOCOS), and the selective oxidation that carries out is grown, and thickness reaches
As shown in Figure 2, at the surface coverage deposition insulating medium layer 200 of multiple-unit semiconductor device, described insulating medium layer 200 can be silicon nitride or silica etc.
As shown in Figure 3, in vertical direction described insulating medium layer 200 is adopted plasma etching, because vertical etching speed is greater than the etching speed of side direction, thus respectively in low voltage component district I and high voltage device district II the vertical interface of transistor gate form sidewall 201.
Above-mentioned existing overall sidewall forms technology, and there are the following problems: because transistorized grid oxide layer difference in thickness is bigger among low voltage component district I and the high voltage device district II, cause the size difference of grid also bigger, therefore deposit and carry out etching behind the insulating medium layer again when forming sidewall, be difficult to form synchronously sidewall, have following two kinds of extreme cases:
As shown in Figure 4, etch amount control is more when supposing overall sidewall etching, can access the transistor sidewall 201 among the desirable high voltage device district II, and with respect to low voltage component district I, more etch amount produces the over etching effect, with the surface of source-drain area in the damage low voltage component transistor substrate, cause junction leakage.
As shown in Figure 5, etch amount control is lower when supposing overall sidewall etching, can access the transistor sidewall 201 among the desirable low voltage component district I, and with respect to high voltage device district I, less etch amount will cause the insulating medium layer of source-drain area remained on surface in its transistor substrate thick partially, make when the ion injection is leaked in follow-up source the ion dose step-down of injection, the degree of depth shoals, and further causes transistorized conducting resistance to uprise.
Under the restriction of above-mentioned two kinds of extreme conditions, the sidewall formation method of existing multiple-unit semiconductor device, its process window is very little, is difficult to realize the desired sidewall effect that obtains of Fig. 3, and technology is wayward, has a strong impact on the quality of product, presses for improvement.
Summary of the invention
The object of the present invention is to provide a kind of sidewall formation method of multiple-unit semiconductor device, make the components and parts zone of different structure size to form desirable separately sidewall respectively, improve the quality of product.
For addressing the above problem, the sidewall formation method of multiple-unit semiconductor device of the present invention comprises:
The multiple-unit semiconductor device that does not form sidewall is provided, and described multiple-unit semiconductor device comprises first element region and second element region at least, and transistorized gate dielectric layer thickness has nothing in common with each other in each element region;
Surface coverage deposition insulating medium layer at described each element region of multiple-unit semiconductor device;
In vertical direction described insulating medium layer is carried out first plasma etching, make in the element region of winning and form the first side wall;
Surface at first element region forms mask layer;
In vertical direction the described insulating medium layer that is positioned at the second element region surface is carried out second plasma etching, make to form second sidewall in second element region.
Wherein, in described first element region transistorized gate dielectric layer thickness less than transistorized gate dielectric layer in second element region.
Optionally, described insulating medium layer material is silica or silicon nitride.The employing chemical vapour deposition (CVD) forms.
Described insulating medium layer is carried out first plasma etching, in exposing first element region till the transistorized source-drain area surface.
Optionally, described mask layer material is a photoresist.
Described the insulating medium layer that is positioned at the second element region surface is carried out second plasma etching, in exposing second element region till the transistorized source-drain area surface.
Described formation method also comprises the step of the mask layer of removing the first element region surface.
Compared with prior art, the present invention has the following advantages: in different components and parts zone, grid size is the difference of gate dielectric layer thickness especially, adopts the mode of multiple etching, and subregion forms corresponding sidewall.Accurately control the size of etch amount, thereby guarantee the product quality of multiple-unit semiconductor device.Avoid the extreme phenomenon that exists in the overall etching, had bigger process window, easy to implement.
Description of drawings
Fig. 1 to Fig. 3 is the sidewall formation method schematic diagram of existing multiple-unit semiconductor device;
Fig. 4 and Fig. 5 are two kinds of failure conditions schematic diagrames of existing sidewall formation method;
Fig. 6 is that the sidewall of multiple-unit semiconductor device of the present invention forms the method flow schematic diagram;
Fig. 7 to Figure 12 is a specific embodiment schematic diagram of sidewall formation method of the present invention.
Embodiment
The sidewall formation method of existing multiple-unit semiconductor device adopts overall sidewall etching, is easy to be subjected to the grid oxygen size restrictions in different components and parts zone, and produces the situation of over etching or etching deficiency.The present invention adopts the method for substep subregion etching, solves the unmanageable problem of above-mentioned etch amount, thereby in each components and parts zone, forms required separately desirable sidewall.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
With reference to shown in Figure 6, the sidewall formation method of multiple-unit semiconductor device of the present invention, basic step comprises:
S1, provide the multiple-unit semiconductor device that does not form sidewall, described multiple-unit semiconductor device to comprise first element region and second element region at least, and transistorized gate dielectric layer thickness have nothing in common with each other in each element region;
Wherein, it is thinner relatively to define in first element region transistorized gate dielectric layer thickness, also is that the grid structure size is less.In addition, in existing MOS technology, gate dielectric layer is not to aim at etching of disposable while of gate electrode sometimes, and therefore described gate dielectric layer also may be overlying on transistorized source-drain area undetermined surface, and removes in the lump in follow-up sidewall etching.
S2, at the surface coverage of described each element region of multiple-unit semiconductor device deposition insulating medium layer;
Because the difference of transistorized grid structure size in each element region, the relative thickness of described insulating medium layer when covering deposition also may have nothing in common with each other.Described insulating medium layer is used to form sidewall, therefore should select its material according to concrete needs.Common sidewall material comprises silicon nitride and silica etc.
S3, in vertical direction described insulating medium layer is carried out first plasma etching, make in the element region of winning and form the first side wall;
Wherein, described first plasma etching will carry out on the surface of whole multiple-unit semiconductor device, because transistorized gate dielectric layer thickness is the thinnest in first element region, grid structure size minimum, therefore in the first plasma etching process, the silicon face that should expose source-drain area at first, and form the first side wall, so whether first plasma etching should expose for stopping foundation according to the silicon face in source transistor drain region in first element region.
S4, form mask layer on the surface of first element region;
Because the size of element region is bigger, for reducing cost, to enhance productivity, the mode that can directly adopt photoresist to smear and expose only forms mask on the surface of first element region that forms desirable sidewall.
S5, in vertical direction the described insulating medium layer that is positioned at the second element region surface is carried out second plasma etching, make to form second sidewall in second element region.
Because the surface of first element region is formed with the mask layer of protection, therefore described second plasma etching only exerts an influence to second element region.According to aforementioned theory, when first plasma etching finished, should also residually there be thicker insulating medium layer or gate dielectric layer in the surface of second element region.Whether described second plasma etching plays the effect that further etching is adjusted, should expose according to the silicon face in source transistor drain region in second element region for stopping foundation, thereby further form the second required sidewall.
Through above-mentioned basic step, each element region will obtain desirable separately sidewall, and avoid the situation of over etching or etching deficiency.Except that above-mentioned steps, also should comprise the conventional steps such as mask layer of removing the element region surface.
Below in conjunction with specific embodiment, the sidewall formation method of multiple-unit semiconductor device of the present invention is described further.
As shown in Figure 7, at first provide the multiple-unit semiconductor device that does not form sidewall, described multiple-unit semiconductor device comprises the first element region I and the second element region II.
Wherein, the first element region I comprises first substrate 301, is positioned at the first grid dielectric layer 302 on first substrate, 301 surfaces, is positioned at the first grid electrode 303 on first grid dielectric layer 302 surfaces.Described first grid electrode 303 is over etching location, therefore first substrate 301 be positioned at the part of its both sides will be as source and drain areas, and described first grid dielectric layer 302 is still aimed at without over etching, therefore is covered in the surface of above-mentioned source and drain areas.
The second element region II comprises second substrate 401, is positioned at second gate dielectric layer 402 on second substrate, 401 surfaces, is positioned at second gate electrode 403 on second gate dielectric layer, 402 surfaces.Same described second gate electrode is also located through over etching, second substrate 401 is positioned at the part of its both sides as source and drain areas, and second gate dielectric layer 402 is still aimed at without over etching, therefore be covered in the surface of above-mentioned source-drain area, and the thickness of described second gate dielectric layer 402 is greater than the thickness of described first grid dielectric layer 302.In addition second gate dielectric layer 302 be positioned at second gate electrode bottom a side also by selective oxidation technology (LOCOS), the selective oxidation that carries out is grown, so thickness is thicker than other parts, plays buffer action.
As shown in Figure 8, on the surface of above-mentioned multiple-unit semiconductor device, also promptly the surface coverage of the first element region I and the second element region II deposits insulating medium layer 500.
Described insulating medium layer 500 is used for the subsequent technique etching and forms sidewall, and its material is selected according to the needs of required formation sidewall, can also can be silicon nitride for silica, can form by chemical vapour deposition (CVD).Because in the aforementioned structure, the first grid dielectric layer 302 and second gate dielectric layer 402 are all aimed at without over etching and be covered in the surface of source-drain area separately, therefore described insulating medium layer 500 also covers each the gate dielectric layer surface that is positioned on the source-drain area.In follow-up sidewall etching, each gate dielectric layer on the described source-drain area will with insulating medium layer 500 removal that is etched in the lump.
As shown in Figure 9, in vertical direction described insulating medium layer 500 is carried out first plasma etching, described first plasma etching carries out in the first element region I and the second element region II simultaneously.
Greater than side direction, so insulating medium layer 500 is will be on the vertical interface of gate electrode residual and form sidewall at the etch rate of vertical direction for described first plasma etching.In the present embodiment, because the thinner thickness of the first grid dielectric layer 302 among the first element region I, it is also littler that the size of whole grid structure is compared the second element region II, therefore the first grid dielectric layer 302 on substrate 301 surfaces and insulating medium layer 500 removal that will be etched at first among the first element region I, and expose the source-drain area surface.Therefore described first plasma etching is promptly surperficial for stopping foundation with the source transistor drain region that exposes among the first element region I.After first plasma etching finishes, will form comparatively desirable the first side wall 501 among the first element region I.And there are second gate dielectric layer 402 and a SI semi-insulation dielectric layer 500 in the surface of source-drain area with residual among the second element region I, and its sidewall is not finished as yet.
As shown in figure 10, form mask layer 600 on the surface of the described first element region I.
Because the relative area of the first element region I is bigger, therefore described mask layer 600 can be photoresist.Only need adopt mask exposure and development then, the photoresist on the element region I surface of winning is retained at the surface-coated photoresist of whole multiple-unit semiconductor device.Above-mentioned mask layer 600 will protect the first element region I not to be subjected to the influence of subsequent technique.
As shown in figure 11, in vertical direction the insulating medium layer 500 that is positioned at the second element region II surface is carried out second plasma etching, in the second element region II, to form second sidewall 502.
Owing to passed through first plasma etching, therefore the insulating medium layer 500 on the second element region II surface is by preliminary etching, the thickness of second gate dielectric layer 402 and the size of grid structure in respect to the second element region II, the etch amount of above-mentioned first plasma etching is not enough to form second sidewall 502.Therefore described second plasma etching will further be removed second gate dielectric layer 402 on source-drain area surface and residual insulating medium layer 500 as a supplement.Described second plasma etching also should be to expose among the second element region II transistorized source-drain area surface for stopping foundation.After second plasma etching is finished, should form the second desirable sidewall 502 among the second element region II.Because the protective effect of mask layer 600, described second plasma etching can't cause damage to the first element region I.
As shown in figure 12, remove the mask layer 600 on the first element region I surface.Finish the sidewall formation method of the described multiple-unit semiconductor device of present embodiment.
The foregoing description, only carrying out the desirable separately sidewall of step etching formation with two kinds of different element regions of gate dielectric layer thickness is example, further, when described multiple-unit semiconductor device comprises the components and parts zone of different gate dielectric layer thickness more than three or three, also can adopt sidewall formation method of the present invention.Only need carry out the plasma etching with number of times such as the number of partitions, and, carry out etching successively, and be aided with the protection of mask layer for the element region that forms desirable sidewall according to the ordering of each district's gate dielectric layer thickness.For example, for the sort element region of N of gate dielectric layer thickness, it will be subjected to the plasma etching of N number, revise the final comparatively desirable side wall construction that obtains one by one.Those skilled in the art should be easily according to disclosed content, and the processing step that further pushes away specifically repeats no more herein.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (8)
1. the sidewall formation method of a multiple-unit semiconductor device is characterized in that, comprising:
The multiple-unit semiconductor device that does not form sidewall is provided, and described multiple-unit semiconductor device comprises first element region and second element region at least, and transistorized gate dielectric layer thickness has nothing in common with each other in each element region;
Surface coverage deposition insulating medium layer at described each element region of multiple-unit semiconductor device;
In vertical direction described insulating medium layer is carried out first plasma etching, make in the element region of winning and form the first side wall;
Surface at first element region forms mask layer;
In vertical direction the described insulating medium layer that is positioned at the second element region surface is carried out second plasma etching, make to form second sidewall in second element region.
2. formation method as claimed in claim 1 is characterized in that, transistorized gate dielectric layer thickness is less than transistorized gate dielectric layer in second element region in described first element region.
3. formation method as claimed in claim 1 is characterized in that, described insulating medium layer material is silica or silicon nitride.
4. formation method as claimed in claim 3 is characterized in that, described insulating medium layer adopts chemical vapour deposition (CVD) to form.
5. formation method as claimed in claim 1 is characterized in that, described insulating medium layer is carried out first plasma etching, in exposing first element region till the transistorized source-drain area surface.
6. formation method as claimed in claim 1 is characterized in that, described mask layer material is a photoresist.
7. formation method as claimed in claim 1 is characterized in that, described the insulating medium layer that is positioned at the second element region surface is carried out second plasma etching, in exposing second element region till the transistorized source-drain area surface.
8. formation method as claimed in claim 1 also comprises the step of the mask layer of removing the first element region surface.
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| CN111370371A (en) * | 2020-03-18 | 2020-07-03 | 长江存储科技有限责任公司 | A kind of preparation method of semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006114871A (en) * | 2004-10-12 | 2006-04-27 | Samsung Sdi Co Ltd | Semiconductor device and manufacturing method thereof |
| CN1841706A (en) * | 2005-03-29 | 2006-10-04 | 冲电气工业株式会社 | Manufacturing method of semiconductor device |
| US20070020866A1 (en) * | 2005-07-12 | 2007-01-25 | Shui-Ming Cheng | CMOS transistor with high drive current and low sheet resistance |
| CN1917173A (en) * | 2005-08-16 | 2007-02-21 | 力晶半导体股份有限公司 | Fabrication method of gate dielectric layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2006114871A (en) * | 2004-10-12 | 2006-04-27 | Samsung Sdi Co Ltd | Semiconductor device and manufacturing method thereof |
| CN1841706A (en) * | 2005-03-29 | 2006-10-04 | 冲电气工业株式会社 | Manufacturing method of semiconductor device |
| US20070020866A1 (en) * | 2005-07-12 | 2007-01-25 | Shui-Ming Cheng | CMOS transistor with high drive current and low sheet resistance |
| CN1917173A (en) * | 2005-08-16 | 2007-02-21 | 力晶半导体股份有限公司 | Fabrication method of gate dielectric layer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111370371A (en) * | 2020-03-18 | 2020-07-03 | 长江存储科技有限责任公司 | A kind of preparation method of semiconductor device |
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Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Co-patentee before: Wuxi Huarun Shanghua Technology Co., Ltd. Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |