CN108231612A - A kind of encapsulation manufacturing method of silicon power npn transistor - Google Patents
A kind of encapsulation manufacturing method of silicon power npn transistor Download PDFInfo
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- CN108231612A CN108231612A CN201711490822.2A CN201711490822A CN108231612A CN 108231612 A CN108231612 A CN 108231612A CN 201711490822 A CN201711490822 A CN 201711490822A CN 108231612 A CN108231612 A CN 108231612A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/83169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head
- H01L2224/8318—Translational movements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention belongs to semiconductor device packaging technique fields, are related to a kind of encapsulation manufacturing method of silicon power npn transistor, the specific steps are：Flash electrotinning rib cutting testing package outbound is gone in curing after load bonding plastic packaging；The present invention lifts technology by using Multi-point point tin technology and multiple spot load, improves the Ohmic contact of chip and lead frame, makes to ensure that power transistor second breakdown tolerance and high reliability without cavity below chip.
Description
Technical field
The present invention relates to a kind of encapsulation making method, especially a kind of encapsulation manufacturing method of silicon power npn transistor,
Belong to the encapsulation technology field of semiconductor devices.
Background technology
Due to requirement of the chip after encapsulation under various adverse circumstances, low temperature, high temperature, humidity, salt fog need to be subjected to
Deng the test of complicated harsh environment, so as to must assure that the high reliability of chip after encapsulation, traditional die is welded to lead frame
Reliability requirement is not achieved in the single-point point process of tin and shaping technique of use；Simultaneously as the material in chip metal layer is special
Property and solder material property difference, cause in chip bonding die solder reflux insufficient, and then fin, cavity etc. can be caused
Problem further results in second breakdown, influences the reliability of power transistor.
Invention content
The purpose of the present invention is overcome the deficiencies in the prior art, it is proposed that a kind of silicon power npn transistor
Encapsulation manufacturing method, this method lift technology by using Multi-point point tin technology and multiple spot load, improve chip and lead frame
The Ohmic contact of frame makes to ensure that power transistor second breakdown tolerance and high reliability without cavity below chip.
For realization more than technical purpose, the technical scheme is that：A kind of encapsulation of silicon power npn transistor makes
Method, which is characterized in that include the following steps：
Step 1 loads：Packed chip is chosen, packed chip is attached in lead frame；
Step 2 is bonded：It is bonded using fully-automatic ultrasonic, by bonding wire by chip electrode and the terminal pin of lead frame
Welding；
Step 3 plastic packagings：Using high thermal conductivity epoxy resin plastic package die, it will be encapsulated, expose above packed chip
Terminal pin；
Cure after step 4, the chip after plastic packaging is put into constant temperature oven and is cured；
Step 5 removes flash；Overlap softening is carried out using bating liquor, then removes and overflows in full-automatic high-pressure water spray equipment
Material；
Step 6 electrotinnings：One layer of tin is electroplated in lead frame surface；
Step 7 rib cuttings：Using double fragmentation formula rib cutting, the lead frame that several connect together is separated；
Outbound is packed after step 8 tests.
Further, the detailed process of load is in the step 1：
A. temperature-rise period：Lead frame at the uniform velocity enters auto loading machine track, by 4 sections of ladder-elevating temperature areas, point of arrival Xi Qu,
Temperature rises to 370 degree of solder fusion temperature；
B. it is moved by step motor control XY platforms, lead frame is made to be moved to below Electrically heated tin solding device, utilizes Multi-point point tin skill
Art, control Electrically heated tin solding device put five drop solders on the lead frames；
C. continue to transport and reach integer area, pressing mold integer is carried out to solder, forms solder layer；
D. continue to transport and reach bonding die area, packed chip is drawn using the rubber suction nozzle on plumb joint, is pulled out using multiple spot load
Packed chip is welded to by solder layer on lead frame by high-tech；
E. continue to transport and reach cooling area, carry out ladder cooling, then discharge.
Further, the multiple spot load lifts technology, specially：
（1）Plumb joint drives packed chip quickly to reach at 45 ~ 55 microns of solder layer surface；
（2）With the direction vertically with solder layer surface, continue that packed chip is driven to be depressed into solder layer surface at a slow speed；
（3）Packed chip is driven to continue to be depressed at 18 ~ 22 microns of solder layer lower face；
（4）In the 2ms of setting, plumb joint quickly drives packed Chip Vertical to lift 18 ~ 22 microns upwards, reaches solder layer
Surface；
（4）Rubber suction nozzle closes vacuum, discharges packed chip.
Further, it during the transport of entire load, transports in track and is passed through hydrogen and nitrogen hybrid protection gas, make
Lead frame is not oxidized at high temperature, and the hydrogen and nitrogen pressure being passed through by pressure regulator valve control are 0.2Mpa, pass through stream
Gauge control is passed through hydrogen flowing quantity as 1L/min, nitrogen flow 8L/min.
Further, in the step 2, the bonding wire uses fine aluminium silk, the weldering of the fine aluminium silk and chip electrode
Power setting is connect as 540mW, welding pressure setting 220g, weld interval 120ms；The fine aluminium silk and terminal pin bonding power
It is set as 650mW, welding pressure is set as 320g, weld interval 120ms.
Further, in step 3, temperature control is at 175 DEG C ± 5 DEG C during the plastic packaging.
Further, in step 4, in the solidification process hardening time be set as 6 hours, solidification temperature is set as 165
DEG C ± 5 DEG C, and for 24 hours, the temperature of storage is set as 150 DEG C ± 5 DEG C to high-temperature storage after curing.
Further, in step 5, the temperature that bating liquor is carried out in overlap softening process is set as 110 DEG C ± 5 DEG C, described
The pressure of full-automatic high-pressure sprinkling equipment is set as 11-12Mpa.
Further, in step 6, the thickness of the plating tin layers is not less than 7 microns, and the temperature being electroplated is set as 8-
10 DEG C, the time of plating is set as 7-9 minutes.
Compared with power device package technique, the present invention has the following advantages：
1）Multi-point point tin technology is used during chip scolding tin of the present invention so that the solder after integer can reach in homogeneous thickness
Solder layer ensures that chip can be smooth during bonding die is pressed on solder layer, chip is made to form extraordinary ohm with lead frame
Contact, ensure that second breakdown and the high reliability of transistor；
2）Technology is lifted using suction nozzle bonding die during chip scolding tin of the present invention, this technology is by suction nozzle being pressed in solder under chip
It is quickly lifted after in layer, suction nozzle discharges chip again, and the effect of this technology is auxiliary solder reflux, makes chip surrounding solder after load
Reflux is consistent, promotes the Ohmic contact of chip and lead frame, makes to ensure that power transistor is secondary without cavity below chip and hit
Wear tolerance and high reliability.
Description of the drawings
Fig. 1 is present invention process method flow diagram.
Fig. 2 is the structure diagram that multiple spot load of the present invention lifts technique.
Reference sign：1- lead frames, 2- solder layers, 3- are packaged chip, 4- rubber suction nozzles.
Specific embodiment
With reference to specific drawings and examples, the invention will be further described.
As shown in Figure 1, a kind of encapsulation manufacturing method of silicon power npn transistor, which is characterized in that including walking as follows
Suddenly：
Step 1 loads：Packed chip 3 is chosen, packed chip 3 is attached in lead frame 1, lead frame 1 is here
TO-3PN；
The detailed process of the load is：
A. temperature-rise period：Lead frame 1 at the uniform velocity enters auto loading machine track, by 4 sections of ladder-elevating temperature areas, point of arrival Xi Qu,
Temperature rises to 370 degree of solder fusion temperature；
B. it is moved by step motor control XY platforms, lead frame 1 is made to be moved to below Electrically heated tin solding device, utilizes Multi-point point tin skill
Art, control Electrically heated tin solding device put five drop solders on lead frame 1；
C. continue to transport and reach integer area, pressing mold integer is carried out to solder, forms solder layer 2；
D. continue to transport and reach bonding die area, packed chip 3 is drawn using the rubber suction nozzle 4 on plumb joint, utilizes multiple spot load
Technology is lifted, chip 3 is welded to by solder layer 2 on lead frame 1；
E. continue to transport and reach cooling area, carry out ladder cooling, then discharge
The Multi-point point tin technology that the present invention uses makes the solder layer after integer 2 whole highly uniform, is not in that single-point point tin is whole
2 unfilled corner situation of solder layer after shape greatly improves the Ohmic contact of packed chip 3 and solder layer 2, reduces thermal resistance, reduces empty
Hole rate promotes the qualification rate of product；
As shown in Fig. 2, the multiple spot load lifts technology, specially：
（1）Plumb joint drives packed chip 3 quickly to reach at 45 ~ 55 microns of 2 surface of solder layer；
（2）With the direction vertically with 2 surface of solder layer, continue that packed chip 3 is driven to be depressed into 2 surface of solder layer at a slow speed；
（3）Packed chip 3 is driven to continue to be depressed at 18 ~ 22 microns of 2 lower face of solder layer；
（4）In the 2ms of setting, plumb joint quickly drives packed chip 3 to lift 18 ~ 22 microns vertically upward, reaches solder
2 surface of layer；
（4）Rubber suction nozzle 4 closes vacuum, discharges packed chip 3；This technology can assist solder to flow back, after making load
The reflux of chip surrounding solder is consistent, promotes the Ohmic contact of packed chip 3 and lead frame 1, makes below packed chip 3
Voidage is 1% hereinafter, the failures such as fin, chip collapse caused by solder reflux is bad during reducing load, greatly carry
The yield of high load ensure that power transistor second breakdown tolerance and high reliability；
During the transport of entire load, transport in track and be passed through hydrogen and nitrogen hybrid protection gas, make lead frame 1 in height
Not oxidized under temperature, the hydrogen and nitrogen pressure being passed through by pressure regulator valve control are 0.2Mpa, are passed through by flowmeter control
Hydrogen flowing quantity is 1L/min, nitrogen flow 8L/min.
Step 2 is bonded：It is bonded using fully-automatic ultrasonic, passes through bonding wire drawing chip electrode and lead frame 1
Stitch welds；
The bonding wire uses fine aluminium silk, and the bonding power of the fine aluminium silk and chip electrode is set as 540mW, welding pressure
Set 220g, weld interval 120ms；The fine aluminium silk is set as 650mW with terminal pin bonding power, and welding pressure is set as
320g, weld interval 120ms；
Step 3 plastic packagings：Using high thermal conductivity epoxy resin plastic package die, packed 3 top of chip is encapsulated, is revealed
Go out terminal pin；Temperature control is at 175 DEG C ± 5 DEG C during the plastic packaging；
Cure after step 4, the chip after plastic packaging is put into constant temperature oven and is cured；When curing in the solidification process
Between be set as 6 hours, solidification temperature is set as 165 DEG C ± 5 DEG C, and for 24 hours, the temperature of storage is set as high-temperature storage after curing
150℃±5℃；
Step 5 removes flash；Overlap softening is carried out using bating liquor, then removes and overflows in full-automatic high-pressure water spray equipment
Material；The temperature that bating liquor is carried out in overlap softening process is set as 110 DEG C ± 5 DEG C, the pressure of the full-automatic high-pressure sprinkling equipment
Power is set as 11-12Mpa；
Step 6 electrotinnings：In lead frame 1 electroplating surface, one layer of tin；
The thickness of the plating tin layers is not less than 7 microns, and the temperature being electroplated is set as 8-10 DEG C, and the time of plating is set as
7-9 minutes；
Step 7 rib cuttings：Using double fragmentation formula rib cutting, the lead frame 1 that several connect together is separated；And it controls
Rib cutting impulse force, reducing stress influences product.
Outbound is packed after step 8 tests.
Above to the present invention and embodiments thereof be described, this describe it is no restricted, it is attached it is shown in figure also only
It is one of embodiments of the present invention, practical structures are not limited thereto.All in all if those of ordinary skill in the art
It is enlightened by it, without departing from the spirit of the invention, not inventively designed similar to the technical solution
Frame mode and embodiment, are within the scope of protection of the invention.
Claims (9)
1. a kind of encapsulation manufacturing method of silicon power npn transistor, which is characterized in that include the following steps：
Step 1 loads：Choose packed chip（3）, by packed chip（3）It is attached to lead frame（1）It is interior；
Step 2 is bonded：It is bonded using fully-automatic ultrasonic, by bonding wire by chip electrode and lead frame（1）Lead
Foot welds；
Step 3 plastic packagings：Using high thermal conductivity epoxy resin plastic package die, by packed chip（3）Top is encapsulated,
Expose terminal pin；
Cure after step 4, the chip after plastic packaging is put into constant temperature oven and is cured；
Step 5 removes flash；Overlap softening is carried out using bating liquor, then removes and overflows in full-automatic high-pressure water spray equipment
Material；
Step 6 electrotinnings：In lead frame（1）One layer of tin of electroplating surface；
Step 7 rib cuttings：Using double fragmentation formula rib cutting, the lead frame that several are connected together（1）It separates；
Outbound is packed after step 8 tests.
2. the encapsulation manufacturing method of a kind of silicon power npn transistor according to claim 1, which is characterized in that described
The detailed process of load is in step 1：
A. temperature-rise period：Lead frame（1）At the uniform velocity enter auto loading machine track, by 4 sections of ladder-elevating temperature areas, point of arrival tin
Area, temperature rise to 370 degree of solder fusion temperature；
B. it is moved by step motor control XY platforms, makes lead frame（1）It is moved to below Electrically heated tin solding device, utilizes Multi-point point tin
Technology, control Electrically heated tin solding device is in lead frame（1）Upper point five drips solder；
C. continue to transport and reach integer area, pressing mold integer is carried out to solder, forms solder layer（2）；
D. continue to transport and reach bonding die area, using the rubber suction nozzle on plumb joint（4）Draw packed chip（3）, utilize multiple spot
Load lifts technology, by packed chip（3）Pass through solder layer（2）It is welded to lead frame（1）On；
E. continue to transport and reach cooling area, carry out ladder cooling, then discharge.
3. the encapsulation manufacturing method of a kind of silicon power npn transistor according to claim 2, which is characterized in that described
Multiple spot load lifts technology, specially：
（1）Plumb joint drives packed chip（3）It is quick to reach solder layer（2）At 45 ~ 55 microns of surface；
（2）With vertical and solder layer（2）The direction on surface continues to drive packed chip at a slow speed（3）It is depressed into solder layer（2）Table
Face；
（3）Drive packed chip（3）Continue to be depressed into solder layer（2）At 18 ~ 22 microns of lower face；
（4）In the 2ms of setting, plumb joint quickly drives packed chip（3）18 ~ 22 microns are lifted vertically upward, reach weldering
The bed of material（2）Surface；
（4）Rubber suction nozzle（4）Vacuum is closed, discharges packed chip（3）.
4. the encapsulation manufacturing method of a kind of silicon power npn transistor according to claim 2, which is characterized in that whole
It during a load transports, transports in track and is passed through hydrogen and nitrogen hybrid protection gas, do not make lead frame 15 at high temperature not
It is aoxidized, the hydrogen and nitrogen pressure being passed through by pressure regulator valve control are 0.2Mpa, and hydrogen stream is passed through by flowmeter control
It measures as 1L/min, nitrogen flow 8L/min.
5. the encapsulation manufacturing method of a kind of silicon power npn transistor according to claim 1, which is characterized in that described
In step 2, the bonding wire uses fine aluminium silk, and the bonding power of the fine aluminium silk and chip electrode is set as 540mW, welds
Meet pressure setting 220g, weld interval 120ms；The fine aluminium silk is set as 650mW, welding pressure with terminal pin bonding power
It is set as 320g, weld interval 120ms.
A kind of 6. encapsulation manufacturing method of silicon power npn transistor according to claim 1, which is characterized in that step
In three, temperature control is at 175 DEG C ± 5 DEG C during the plastic packaging.
A kind of 7. encapsulation manufacturing method of silicon power npn transistor according to claim 1, which is characterized in that step
In four, in the solidification process hardening time be set as 6 hours, solidification temperature is set as 165 DEG C ± 5 DEG C, and high temperature after curing
For 24 hours, the temperature of storage is set as 150 DEG C ± 5 DEG C for storage.
A kind of 8. encapsulation manufacturing method of silicon power npn transistor according to claim 1, which is characterized in that step
In five, the temperature that bating liquor is carried out in overlap softening process is set as 110 DEG C ± 5 DEG C, the full-automatic high-pressure sprinkling equipment
Pressure is set as 11-12Mpa.
A kind of 9. encapsulation manufacturing method of silicon power npn transistor according to claim 1, which is characterized in that step
In six, the thickness of the plating tin layers is not less than 7 microns, and the temperature being electroplated is set as 8-10 DEG C, and the time of plating is set as
7-9 minutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711490822.2A CN108231612B (en) | 2017-12-30 | 2017-12-30 | Packaging manufacturing method of silicon NPN type power transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711490822.2A CN108231612B (en) | 2017-12-30 | 2017-12-30 | Packaging manufacturing method of silicon NPN type power transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108231612A true CN108231612A (en) | 2018-06-29 |
| CN108231612B CN108231612B (en) | 2020-05-12 |
Family
ID=62642119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711490822.2A Active CN108231612B (en) | 2017-12-30 | 2017-12-30 | Packaging manufacturing method of silicon NPN type power transistor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110620047A (en) * | 2019-09-18 | 2019-12-27 | 纽威仕微电子（无锡）有限公司 | Small-size integrated circuit packaging process based on ceramic substrate |
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| CN1969383A (en) * | 2003-04-11 | 2007-05-23 | 费查尔德半导体有限公司 | Lead frame structure with aperture or groove for flip chip in a leaded molded package |
| US20090160039A1 (en) * | 2007-12-20 | 2009-06-25 | National Semiconductor Corporation | Method and leadframe for packaging integrated circuits |
| US20120025401A1 (en) * | 2010-07-28 | 2012-02-02 | Chu-Chung Lee | Integrated circuit package with voltage distributor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110620047A (en) * | 2019-09-18 | 2019-12-27 | 纽威仕微电子（无锡）有限公司 | Small-size integrated circuit packaging process based on ceramic substrate |
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| Publication number | Publication date |
|---|---|
| CN108231612B (en) | 2020-05-12 |
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