CN104124216A - Substrate chip carrier CSP package and production method thereof - Google Patents
Substrate chip carrier CSP package and production method thereof Download PDFInfo
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- CN104124216A CN104124216A CN201410318337.7A CN201410318337A CN104124216A CN 104124216 A CN104124216 A CN 104124216A CN 201410318337 A CN201410318337 A CN 201410318337A CN 104124216 A CN104124216 A CN 104124216A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15162—Top view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention provides a substrate chip carrier CSP package and a production method thereof. The package comprises a substrate having a middle supporting layer, opposite side walls of the middle supporting layer are provided with a plurality of connecting holes, a first metal layer is formed in each connecting hole, two end faces of the middle supporting layer are provided with first bonding pads and second bonding pads having the same quantity with the connecting holes, two ends of each first metal layer are respectively connected to the corresponding first bonding pad and the corresponding second pad, the pipe core adhering area of the middle supporting layer is provided with a plurality of ventilation holes in which cylindrical second metal layers are formed, the bonding pads of an IC chip are connected to the second bonding pads, a package body is fixedly packaged on the substrate. The substrate chip carrier CSP package is produced through the steps of thinning and scribing a wafer, connecting pipe cores by adhesive, bonding by a wire, packaging, marking, cutting and separating, testing and visually inspecting. The package body is compact in size, applied to IC components with fewer leading-out terminals, and replaces TSSOP and other conventional packaging; for an IC chip which is 0.350mm thick, the packaging thickness can be lower than 1mm.
Description
Technical field
The invention belongs to electronic device and manufacture semiconductor packaging field, relate to a kind of CSP packaging part, be specifically related to a kind of substrate chip support C SP packaging part; The invention still further relates to a kind of manufacture method of this packaging part.
Background technology
Along with the development of electronic chip packaging part shape, integrated circuit installation method is transformed into surface installing type (STM) from insert type, STM has realized densification, slimming, the lightweight of IC encapsulation, and STM technology comprises conductor wire connecting method, tape automated bonding (TAB) method, flip-chip method.In recent years, due to the fast development of the wireless telecommunications systems such as smart mobile phone, integrated antenna package is more and more higher to the shape need of packaging part, conventional lead frame miniaturization Plastic Package, as TSSOP, TQFP, realize package thickness and be less than the encapsulation below 1mm, its tube core must be thinned to 0.254mm, simultaneously because the distribution area of lead frame pin is larger, make its lead frame carrier area narrow and small, be difficult to hold larger tube core, the proportion that the distribution area of pin accounts for packaging part erection space is also larger.In addition, along with transistorized number in chip is more and more, caloric value is also increasing, and in the situation that chip area does not significantly increase thereupon, device heating density is more and more higher, and problems of excessive heat has become the bottleneck of current restriction electronic device technical development.
Summary of the invention
The object of this invention is to provide a kind of substrate chip support C SP packaging part, there is larger lead frame carrier area, can hold more tube core, and heat dispersion is good.
Another object of the present invention is to provide a kind of manufacture method of above-mentioned packaging part.
For achieving the above object, the technical solution adopted in the present invention is: a kind of substrate chip support C SP packaging part, comprise substrate, substrate comprises again middle support layer, in middle support layer, on one group of relative sidewall, be respectively equipped with multiple semicircular connecting holes, and on these two sidewalls, the quantity of connecting hole is identical; The surface of each connecting hole is all electroplate with the first metal layer, the endoporus of the first metal layer is the first through hole, an end face of middle support layer is provided with the first pad that quantity is identical with connecting hole quantity, another end face of middle support layer is provided with the second pad that quantity is identical with connecting hole quantity, one end of the first metal layer in a connecting hole is connected with first pad, and the other end of the first metal layer in a connecting hole is connected with second pad; The middle part of middle support layer is provided with die bonding district, is provided with multiple louvres in die bonding district, is equipped with the second metal level of tubular on the inner surface of the plurality of louvre; Substrate is provided with on the end face of the second pad and is pasted with IC chip, and the 3rd pad on IC chip is connected with the second pad by bonding wire, and substrate is provided with on the end face of the second pad and is sealed with plastic-sealed body; The end face that the surface of the second pad, IC chip, the 3rd pad, bonding wire, the first metal layer and substrate are provided with the second pad is all positioned at plastic-sealed body.
Another technical scheme of the present invention is: a kind of manufacture method of aforesaid substrate chip support C SP packaging part, specifically carry out according to the following steps:
Step 1: attenuate wafer; Wafer rear after attenuate sticks blue film, and baking adopts double-pole scribing process that wafer is cut into single IC chip; When scribing, the first cutter tool marks degree of depth is that 2/3, the second cutter of wafer thickness after attenuate directly becomes wafer separate single IC chip, and leaves tool marks on the blue film that is pasted on wafer rear, and blue film can not be drawn;
Step 2: the feeding platform of substrate being delivered to chip feeder, wafer after scribing is positioned over wafer work platform, with drawing glue in the colloid system die bonding district on substrate of writing of chip feeder, with thimble by the IC chip jack-up on blue film, draw IC chip with suction nozzle, the die bonding district that IC chip is placed on substrate carries out bonding simultaneously; Then adopt anti-absciss layer baking process, at the temperature of 150 DEG C, toast plasma cleaning 3 hours;
Step 3: the first pad that the 3rd pad on IC chip is connected to upper surface of base plate by bonding wire;
After Bonding, through sealing, marking, cutting and separating, test and visual inspection, choose defective products and waste product, qualified product are the substrate chip support C SP packaging part making.
This CSP encapsulation is a kind of slim CSP of compact dimensions, is mainly used in the less IC device of exit, substitutes the conventional encapsulation such as TSSOP, and for the IC chip of 0.350mm thickness, this package thickness can reach below 1mm.And conventional molded packages, thickness will reach below 1mm, and IC chip thickness at least will be thinned to 0.254mm.In addition, compare with the conventional plastic package with identical pad, this packaging part can hold larger tube core, and because adopt without lead design, erection space is than little many of the lead-frame packages with same package dimension.Meanwhile, the setting in packaging part bottom heat radiation hole, makes this package cooling functional, and heat dispersion is better than conventional encapsulation.
Except good form factor, this encapsulation is the relatively low CSP encapsulation of cost, because the manufacture of this encapsulation can adopt prior art to carry out on existing encapsulation basic facilities, and this encapsulation replaces conventional molded packages while sealing by first method, adopt syringe to drip to be coated with ball-type top to drip glue and seal mode packaged chip and bonding wire are protected; The second encapsulating method adopts MGP mould multistage mould streamer to penetrate anti-warpage software controlling technique, and encapsulate chip and bonding wire are protected; The third encapsulating method adopts the full-automatic AUTO Mold automatic mold encapsulation system with vacuum suction, and encapsulate chip and bonding wire are protected.
Brief description of the drawings
Fig. 1 is the schematic diagram of CSP packaging part the first embodiment of the present invention.
Fig. 2 is the schematic diagram of CSP packaging part the second embodiment of the present invention.
Fig. 3 is the schematic diagram of the third embodiment of CSP packaging part of the present invention.
Fig. 4 is the schematic diagram of substrate in CSP packaging part of the present invention.
Fig. 5 is the left view of Fig. 4.
Fig. 6 is the rearview of Fig. 4.
In figure: 1. substrate, 2. the first pad, 3. the first metal layer, 4. the second pad, 5. plastic-sealed body, 6.IC chip, 7. the 3rd pad, 8. bonding wire, 9. the first through hole, 10. bonding die glue, 11. second metal levels, 12. second through holes, 13. middle support layer, 14. die bonding districts.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
As shown in Figure 1, the first Embodiment C SP packaging part of the present invention, comprise structure substrate 1 as shown in Figure 4, Figure 5 and Figure 6, substrate 1 comprises middle support layer 13, in middle support layer 13, on one group of relative sidewall, be respectively equipped with multiple semicircular connecting holes, and the quantity of the connecting hole on these two sidewalls is identical, and is symmetrical arranged with respect to the axis of middle support layer 13; The surface of each connecting hole is all electroplate with the first metal layer 3, the endoporus of the first metal layer 3 is the first through hole 9, an end face of middle support layer 13 is provided with the first pad 2 that quantity is identical with connecting hole quantity, another end face of middle support layer 13 is provided with the second pad 4 that quantity is identical with connecting hole quantity, one end of the first metal layer 3 in a connecting hole is connected with first pad 2, and the other end of the first metal layer 3 in a connecting hole is connected with second pad 4; The middle part of middle support layer 13 is provided with die bonding district 14, is provided with multiple louvres in die bonding district 14, and the endoporus that is equipped with the second metal level 11, the second metal levels 11 of tubular on the inner surface of the plurality of louvre is the second through hole 12.Substrate 1 is provided with on the end face of the second pad 4 and is pasted with IC chip 6, IC chip 6 is adhered in die bonding district 14 by bonding die glue 10, IC chip 6 is provided with the 3rd pad 7, the 3rd pad 7 is connected with the second pad 4 by bonding wire 8, and substrate 1 is provided with on the end face of the second pad 4 and is sealed with plastic-sealed body 5; The end face that the surface of the second pad 4, bonding die glue 10, IC chip 6, the 3rd pad 7, bonding wire 8, the first metal layer 3 and substrate 1 are provided with the second pad 4 is all positioned at plastic-sealed body 5.
The structure of the structure of the second Embodiment C SP packaging part of the present invention shown in Fig. 2 and the third Embodiment C of the present invention shown in Fig. 3 SP packaging part is all identical with the structure of the Embodiment C of the first shown in Fig. 1 SP packaging part, just the packaging part of these three kinds of structures adopts respectively different encapsulating methods to carry out plastic packaging, cause the profile of plastic-sealed body 5 slightly different: in the first embodiment, plastic-sealed body 5 is smooth radian shape, has certain demoulding angle; In the second embodiment, the profile consistency of plastic-sealed body 5 is better, and the chamfering of 15 °～30 ° is arranged at plastic-sealed body 5 tops, and in the third embodiment, plastic-sealed body 5 tops are plane.
Substrate 1 is a kind of rigid substrates, and middle support layer 13 can adopt organic laminate substrate.The first pad 2 is the I/O interconnection for substrate 1 and IC chip 6 as wire bond pads; The second pad 4 as the exit of packaging part for realizing being electrically connected of packaging part and external circuit.The first metal layer 3 is electrodeposited coating, for realizing the electrical connection of the first pad 2 and the second pad 4.The second metal level 11 of the tubular in each louvre can conduct heat fast, to improve the heat dispersion of packaging part,
The present invention also provides a kind of manufacture method of above-mentioned CSP packaging part, specifically carries out according to the following steps:
Step 1: reduction scribing
Adopt the reduction process of corase grind+fine grinding+polishing to carry out attenuate to crystal column surface; Corase grind and fine grinding are the modes by mechanical lapping, and wafer is thinned to certain thickness, and general corase grind is thinned to 350 ± 10 μ m, and fine grinding is thinned to 280 ± 10 μ m; When corase grind, attenuate machine abrasive wheel rotating speed is very fast, can remove fast the Si material of wafer rear, but easily wafer is caused to damage simultaneously, after so corase grind carries out certain hour, to carry out fine grinding to wafer by the rotating speed that reduces abrasive wheel, thereby farthest avoid mechanical damage and the stress remnants of wafer rear; Because mechanical lapping itself is exactly a process that physics is exerted pressure, damages, breaks, removed, adopt glossing, can further improve mechanical damage and the stress remnants of wafer rear, make wafer surface roughness reach 0.05 μ m～0.12 μ m, prevent that wafer from breaking because warpage produces in moving process, glossing can adopt dry throw, wet throwing, dry etching, wet etching etc.;
Wafer rear after attenuate sticks blue film, and will toast the wafer sticking after blue film, then adopts double-pole scribing process that wafer is cut into single IC chip; When scribing, the first cutter tool marks degree of depth is 2/3 left and right of wafer thickness after attenuate, and the second cutter directly becomes wafer separate single IC chip, and leaves obvious tool marks on the blue film that is pasted on wafer rear, for preventing that chip from dropping, blue film can not be drawn;
Step 2: die bonding
First substrate is delivered to the feeding platform of chip feeder, wafer after scribing is positioned over wafer work platform, and adopt the colloid system of writing that chip feeder is equipped with (to write the size of glue head according to chip size and bonding die adhesiveness different choice, write glue pattern also relevant with chip form size) on substrate, glue is drawn in die bonding district, then use thimble by the IC chip jack-up on blue film, adopt suction nozzle absorption chip, the die bonding district that IC chip is placed on substrate accurately carries out bonding simultaneously; For further improving the firmness of chip and substrate, the substrate after upper core need be sent to baking oven baking, adopt anti-absciss layer baking process, at the temperature of 150 DEG C, toast 3 hours; After baking, further the substrate after upper core is carried out to plasma cleaning;
Step 3: Bonding
The 3rd pad on IC chip is connected to the first pad of upper surface of base plate by bonding wire, when bonding wire: adopt copper cash, gold thread or alloy wire ball-type bonding technology, first utilize heat energy and ultrasonicly on the 3rd pad, weld a circular metal ball at IC chip bonding pad, then chopper height raises, wire drawing arch arc carries out stitch bonding on substrate the first pad, forms fishtail solder joint; Afterwards, draw buttock line to enter bonding next time, until complete the Bonding of whole encapsulation;
Step 4: seal
Sealing of packaging body is divided into three kinds of methods:
First method: small lot and development, in order to reduce process costs, adopt ball-type to drip glue encapsulating process, encapsulating material is the epoxy resin liquid with medium-viscosity (range of viscosities: 9400～11,000 25 DEG C of mPa.s@); First silicone resin mask is installed on substrate, prevent that epoxy resin from overflowing, then use the injector system of syringe and syringe needle to carry out the painting of plastic packaging gob, until plastic packaging material is filled the first through hole, completely coated IC chip, IC chip bonding pad, bonding wire, a upper surface of base plate part and the first pad; After having sealed, remove the silicone resin mask that is arranged on substrate surface, and under 150 DEG C of temperature conditions, carry out solidifying after 2 hours, the plastic-sealed body 5 obtaining as shown in Figure 1.Dripping due to this ball-type that glue seals is at existing COB(chip On board) adopt prior art to carry out in encapsulation infrastructure, so packaging cost is lower, be a kind of low-cost package technique.
Second method: adopt mold encapsulating process, when plastic packaging, adopt semi-automatic MGP (multiple gate plunger) many injecting heads mould encapsulation system, apply existing multistage and inject anti-warpage software controlling technique, plastic packaging material is injected to mold cavity, until plastic packaging material is filled the first through hole, completely coated IC chip, IC chip bonding pad, bonding wire, a upper surface of base plate part and the first pad, multistage is injected anti-warpage software control encapsulating process and can be solved and rush silk, warpage and absciss layer in plastic packaging process.Adopt afterwards the colloid after anti-warpage solidifying clamp plastic packaging, at 175 DEG C ± 10 DEG C temperature, rear solidifying 4～7 hours; Due to the restriction of mold cavity, packaging body profile consistency is better, and for the demoulding after plastic packaging is easy, plastic-sealed body 5 tops have the chamfering of 15 °～30 °, as Fig. 2;
The third method: adopt mold encapsulating process, when plastic packaging, adopt the full-automatic AUTO Mold automatic mold encapsulation system with vacuum suction, apply existing multistage and inject anti-warpage software controlling technique, plastic packaging material is injected to mold cavity, until plastic packaging material is filled the first punching through hole, completely coated IC chip, IC chip bonding pad, bonding wire, a upper surface of base plate part and the first pad, multistage is injected anti-warpage software control encapsulating process and can be solved and rush silk, warpage and absciss layer in plastic packaging process.Adopt afterwards the colloid after anti-warpage solidifying clamp plastic packaging, at 175 DEG C ± 10 DEG C temperature, rear solidifying 4～7 hours; Because automatic mold die cavity is overall package, the packaging body profile consistency after cutting and separating is better, and the rectangular shape of packaging body corner angle, as shown in Figure 3;
Mold encapsulating process is applicable to the production in enormous quantities of packaging part, can improve consistency and the production efficiency of encapsulating products packaging appearance, and wherein, with the full-automatic AUTO Mold automatic mold plastic packaging system price costliness of vacuum suction, one-time investment is larger.
Step 5: marking
After sealing operation, adopt full-automatic or semi-automatic laser printer, on packaging body, stamp mark;
Step 6: cutting and separating
Because substrate is a monoblock flat type at first, include a lot of encapsulation units, when cutting, adopt machinery or laser cutting mode, along line of cut, large substrates cutting and separating is become to single package unit, the first through hole is divided into two halves simultaneously, and the first metal layer in the first through hole becomes dome shape;
Step 7: test and visual inspection
Product after separating is tested and visual inspection, chosen defective products and waste product, qualified product are the substrate chip support C SP packaging part making.
embodiment 1
Adopt the reduction process of corase grind+fine grinding+polishing to carry out attenuate to crystal column surface; The thickness 350 μ m of wafer after corase grind, the thickness 280 μ m of wafer after fine grinding; Polishing makes wafer surface roughness reach 0.05 μ m～0.12 μ m; Wafer rear after attenuate sticks blue film, and baking, then adopts double-pole scribing process that wafer is cut into single IC chip; When scribing, the first cutter tool marks degree of depth be after attenuate wafer thickness 2/3; The second cutter directly becomes wafer separate single IC chip, and leaves obvious tool marks on the blue film that is pasted on wafer rear, blue film can not be drawn; Substrate is delivered to the feeding platform of chip feeder, wafer after scribing is positioned over wafer work platform, adopt the colloid system die bonding district on substrate of writing that chip feeder is equipped with to draw glue, use thimble by the IC chip jack-up on blue film, suction nozzle is drawn IC chip simultaneously, and the die bonding district that IC chip is placed on substrate accurately carries out bonding; Adopt anti-absciss layer baking process, at the temperature of 150 DEG C, toast 3 hours; Plasma cleaning; The 3rd pad on IC chip is connected to the first pad of upper surface of base plate by bonding wire; Adopt copper cash ball-type bonding technology, first utilize heat energy and ultrasonicly on the 3rd pad, weld a circular metal ball at IC chip bonding pad, the chopper height that then raises, wire drawing arch arc carries out stitch bonding on substrate the first pad, forms fishtail solder joint; Afterwards, draw buttock line to enter bonding next time, until complete the Bonding of whole encapsulation; Small lot and development, adopt ball-type to drip glue encapsulating process, and encapsulating material is the epoxy resin liquid with medium-viscosity (range of viscosities: 9400～11,000 25 DEG C of mPa.s@); First silicone resin mask is installed on substrate, prevent that epoxy resin from overflowing, then use the injector system of syringe and syringe needle to carry out the painting of plastic packaging gob, until plastic packaging material is filled the first through hole, completely coated IC chip, IC chip bonding pad, bonding wire, a upper surface of base plate part and the first pad; After having sealed, remove the silicone resin mask that is arranged on substrate surface, and under 150 DEG C of temperature conditions, rear solidifying 2 hours.Adopt fully-automatic laser printer, on packaging body, stamp mark; Adopt machine cuts mode, along line of cut, large substrates cutting and separating is become to single package unit, the first through hole is divided into two halves simultaneously, and the first metal layer in the first through hole becomes dome shape; Product after separating is tested and visual inspection, chosen defective products and waste product, qualified product are the substrate chip support C SP packaging part making.
embodiment 2
Adopt the reduction process of corase grind+fine grinding+polishing to carry out attenuate to crystal column surface; The thickness 360 μ m of wafer after corase grind, the thickness 290 μ m of wafer after fine grinding; Glossing makes wafer surface roughness reach 0.05～0.12 μ m; Wafer rear after attenuate sticks blue film, and baking adopts double-pole scribing process that wafer is cut into single IC chip; When scribing, the first cutter tool marks degree of depth is that 2/3, the second cutter of wafer thickness after attenuate directly becomes wafer separate single IC chip, and leaves obvious tool marks on the blue film that is pasted on wafer rear, blue film can not be drawn; Substrate is delivered to the feeding platform of chip feeder, wafer after scribing is positioned over wafer work platform, adopt the colloid system die bonding district on substrate of writing that chip feeder is equipped with to draw glue, with thimble by the IC chip jack-up on blue film, adopt suction nozzle to draw IC chip, the die bonding district that IC chip is placed on substrate accurately carries out bonding simultaneously; Adopt anti-absciss layer baking process, at the temperature of 150 DEG C, toast 3 hours; Plasma cleaning; The 3rd pad on IC chip is connected to the first pad of upper surface of base plate by bonding wire; Adopt gold thread ball-type bonding technology, first utilize heat energy and ultrasonicly on the 3rd pad, weld a circular metal ball at IC chip bonding pad, the chopper height that then raises, wire drawing arch arc carries out stitch bonding on substrate the first pad, forms fishtail solder joint; Afterwards, draw buttock line to enter bonding next time, until complete the Bonding of whole encapsulation; Adopt mold encapsulating process, when plastic packaging, adopt semi-automatic MGP (multiple gate plunger) many injecting heads mould encapsulation system, apply existing multistage and inject anti-warpage software controlling technique, plastic packaging material is injected to mold cavity, until plastic packaging material is filled the first through hole, completely coated IC chip, IC chip bonding pad, bonding wire, a upper surface of base plate part and the first pad, multistage is injected anti-warpage software control encapsulating process and can be solved and rush silk, warpage and absciss layer in plastic packaging process.Adopt afterwards the colloid after anti-warpage solidifying clamp plastic packaging, at 175 DEG C ± 10 DEG C temperature, rear solidifying 4～7 hours; Plastic-sealed body top has the chamfering of 15 °～30 °; Adopt semi-automatic laser printer, on packaging body, stamp mark; Adopt laser cutting mode, along line of cut, large substrates cutting and separating is become to single package unit, the first through hole is divided into two halves simultaneously, and the first metal layer in the first through hole becomes dome shape; Product after separating is tested and visual inspection, chosen defective products and waste product, qualified product are the substrate chip support C SP packaging part making.
embodiment 3
Adopt the reduction process of corase grind+fine grinding+polishing to carry out attenuate to crystal column surface, the thickness 340 μ m of wafer after corase grind, the thickness 270 μ m of wafer after fine grinding; Polishing makes wafer surface roughness reach 0.05 μ m～0.12 μ m; Wafer rear after attenuate sticks blue film, and baking adopts double-pole scribing process that wafer is cut into single IC chip; When scribing, the first cutter tool marks degree of depth is that 2/3, the second cutter of wafer thickness after attenuate directly becomes wafer separate single IC chip, and leaves obvious tool marks on the blue film that is pasted on wafer rear, blue film can not be drawn; Substrate is delivered to the feeding platform of chip feeder, wafer after scribing is positioned over wafer work platform, glue is drawn in the colloid system die bonding district on substrate of writing being equipped with chip feeder, with thimble by the IC chip jack-up on blue film, adopt suction nozzle to draw IC chip, the die bonding district that IC chip is placed on substrate accurately carries out bonding simultaneously; For further improving the firmness of chip and substrate, the substrate after upper core need be sent to baking oven baking, adopt anti-absciss layer baking process, at the temperature of 150 DEG C, toast 3 hours; Plasma cleaning; The 3rd pad on IC chip is connected to the first pad of upper surface of base plate by bonding wire, when bonding wire: adopt alloy wire ball-type bonding technology, first utilize heat energy and ultrasonicly on the 3rd pad, weld a circular metal ball at IC chip bonding pad, then chopper height raises, wire drawing arch arc carries out stitch bonding on substrate the first pad, forms fishtail solder joint; Afterwards, draw buttock line to enter bonding next time, until complete the Bonding of whole encapsulation; Adopt mold encapsulating process, when plastic packaging, adopt the full-automatic AUTO Mold automatic mold encapsulation system with vacuum suction, apply existing multistage and inject anti-warpage software controlling technique, plastic packaging material is injected to mold cavity, until plastic packaging material is filled the first punching through hole, completely coated IC chip, IC chip bonding pad, bonding wire, a upper surface of base plate part and the first pad, multistage is injected anti-warpage software control encapsulating process and can be solved and rush silk, warpage and absciss layer in plastic packaging process.Adopt afterwards the colloid after anti-warpage solidifying clamp plastic packaging, at 175 DEG C ± 10 DEG C temperature, rear solidifying 4～7 hours; Because automatic mold die cavity is overall package, the packaging body profile consistency after cutting and separating is better, and the rectangular shape of packaging body corner angle; Adopt fully-automatic laser printer, on packaging body, stamp mark; Adopt laser cutting mode, along line of cut, large substrates cutting and separating is become to single package unit, the first through hole is divided into two halves simultaneously, and the first metal layer in the first through hole becomes dome shape; Product after separating is tested and visual inspection, chosen defective products and waste product, qualified product are the substrate chip support C SP packaging part making.
This packaging part is sealed, the ball-type of existing fast Development low cost batch production drips glue to be sealed, also there is the semi-automatic MGP moulding compound encapsulating mold of lower cost to produce, also have the full-automatic AUTO Mold automatic mold encapsulation system with vacuum suction of high-quality, the low rate of breasting the tape to produce, can select as required the mode of production.
The above-mentioned embodiments of the invention of having described.But, should be appreciated that without departing from the spirit and scope of the present invention, can make various amendments.
Claims (8)
1. a substrate chip support C SP packaging part, it is characterized in that, comprise substrate (1), substrate (1) comprises again middle support layer (13), in middle support layer (13), on one group of relative sidewall, be respectively equipped with multiple semicircular connecting holes, and on these two sidewalls, the quantity of connecting hole is identical; The surface of each connecting hole is all electroplate with the first metal layer (3), the endoporus of the first metal layer (3) is the first through hole (9), an end face of middle support layer (13) is provided with the first pad (2) that quantity is identical with connecting hole quantity, another end face of middle support layer (13) is provided with the second pad (4) that quantity is identical with connecting hole quantity, one end of the first metal layer (3) in a connecting hole is connected with first pad (2), and the other end of the first metal layer (3) in a connecting hole is connected with second pad (4); The middle part of middle support layer (13) is provided with die bonding district (14), and die bonding district is provided with multiple louvres in (14), is equipped with second metal level (11) of tubular on the inner surface of the plurality of louvre; Substrate (1) is provided with on the end face of the second pad (4) and is pasted with IC chip (6), the 3rd pad (7) on IC chip (6) is connected with the second pad (4) by bonding wire (8), and substrate (1) is provided with on the end face of the second pad (4) and is sealed with plastic-sealed body (5); The end face that the surface of the second pad (4), IC chip (6), the 3rd pad (7), bonding wire (8), the first metal layer (3) and substrate (1) are provided with the second pad (4) is all positioned at plastic-sealed body (5).
2. substrate chip support C SP packaging part according to claim 1, is characterized in that, the connecting hole on (13) two sidewalls of middle support layer is symmetrical arranged with respect to the axis of middle support layer (13).
3. substrate chip support C SP packaging part according to claim 1, is characterized in that, IC chip (6) is adhered in die bonding district (14).
4. a manufacture method for substrate chip support C SP packaging part described in claim 1, is characterized in that, specifically carries out according to the following steps:
Step 1: attenuate wafer; Wafer rear after attenuate sticks blue film, and baking adopts double-pole scribing process that wafer is cut into single IC chip; When scribing, the first cutter tool marks degree of depth is that 2/3, the second cutter of wafer thickness after attenuate directly becomes wafer separate single IC chip, and leaves tool marks on the blue film that is pasted on wafer rear, and blue film can not be drawn;
Step 2: the feeding platform of substrate being delivered to chip feeder, wafer after scribing is positioned over wafer work platform, with drawing glue in the colloid system die bonding district on substrate of writing of chip feeder, with thimble by the IC chip jack-up on blue film, draw IC chip with suction nozzle, the die bonding district that IC chip is placed on substrate carries out bonding simultaneously; Then adopt anti-absciss layer baking process, at the temperature of 150 DEG C, toast plasma cleaning 3 hours;
Step 3: the first pad that the 3rd pad on IC chip is connected to upper surface of base plate by bonding wire;
After Bonding, through sealing, marking, cutting and separating, test and visual inspection, choose defective products and waste product, qualified product are the substrate chip support C SP packaging part making.
5. the manufacture method of substrate chip support C SP packaging part according to claim 4, it is characterized in that, in described step 1, adopt corase grind+fine grinding+polishing reduction process attenuate wafer, thickness 350 ± 10 μ m of wafer after corase grind, thickness 280 ± 10 μ m of wafer after fine grinding; Then polishing makes wafer surface roughness reach 0.05 μ m～0.12 μ m.
6. the manufacture method of substrate chip support C SP packaging part according to claim 4, it is characterized in that, in described step 3, when bonding wire: adopt copper cash, gold thread or alloy wire ball-type bonding technology, first utilize heat energy and ultrasonicly on the 3rd pad, weld a circular metal ball at IC chip bonding pad, then the chopper height that raises, wire drawing arch arc carries out stitch bonding on substrate the first pad, forms fishtail solder joint; Afterwards, draw buttock line to enter bonding next time, until complete the Bonding of whole encapsulation.
7. the manufacture method of substrate chip support C SP packaging part according to claim 4, is characterized in that, the sealing of packaging body of sealing after Bonding is divided into three kinds of methods:
First method: adopt ball-type to drip glue encapsulating process, selected moderately viscous encapsulating material; First silicone resin mask is installed on substrate, is then used injector system to carry out the painting of plastic packaging gob, until plastic packaging material is filled the first through hole, completely coated IC chip, IC chip bonding pad, bonding wire, a upper surface of base plate part and the first pad; After having sealed, remove the silicone resin mask that is arranged on substrate surface, and under 150 DEG C of temperature conditions, rear solidifying 2 hours, completes and seals;
Second method: adopt mold encapsulating process and semi-automatic many injecting heads of MGP mould encapsulation system, apply existing multistage and inject anti-warpage software controlling technique, plastic packaging material is injected to mold cavity, until plastic packaging material is filled the first through hole, completely coated IC chip, IC chip bonding pad, bonding wire, a upper surface of base plate part and the first pad, at 175 DEG C ± 10 DEG C temperature, rear solidifying 4～7 hours, completes and seals afterwards;
The third method: adopt mold encapsulating process and the full-automatic AUTO Mold automatic mold encapsulation system with vacuum suction, apply existing multistage and inject anti-warpage software controlling technique, plastic packaging material is injected to mold cavity, until plastic packaging material is filled the first punching through hole, completely coated IC chip, IC chip bonding pad, bonding wire, a upper surface of base plate part and the first pad, at 175 DEG C ± 10 DEG C temperature, rear solidifying 4～7 hours, completes and seals afterwards.
8. the manufacture method of substrate chip support C SP packaging part according to claim 4, it is characterized in that, when cutting and separating: adopt machine cuts mode or laser cutting mode, along line of cut, large substrates cutting and separating is become to single package unit, the first through hole is divided into two halves simultaneously, and the first metal layer in the first through hole becomes dome shape.
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| CN111933623B (en) * | 2020-06-29 | 2024-02-27 | 中国航空工业集团公司北京长城航空测控技术研究所 | Packaging interconnection structure and method based on substrate side bonding pad |
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| CN112117204A (en) * | 2020-09-10 | 2020-12-22 | 安徽龙芯微科技有限公司 | A method of making a packaging structure |
| CN112117204B (en) * | 2020-09-10 | 2022-10-14 | 安徽龙芯微科技有限公司 | Manufacturing method of packaging structure |
| CN113991004A (en) * | 2021-10-26 | 2022-01-28 | 东莞市中麒光电技术有限公司 | LED substrate manufacturing method, LED substrate, LED device manufacturing method and LED device |
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