TW201824404A - A method of semiconductor package without substrate - Google Patents

Abstract

A method of semiconductor package without substrate is disclosed. The method includes providing a semiconductor die with bumps on the die and providing a transparent substrate. An adhesive layer is formed on the substrate and the die is flipped and mounted on the adhesive layer. An encapsulating glue is dropped over the adhesive layer and the die. Then a concave mould is used to shape the glue. After removing the mould, an UV light irradiate the substrate to embrittle the glue. Finally, the substrate and the adhesive layer are removed to form a package without substrate.

Description

 Substrate-free semiconductor package manufacturing method  

The present invention relates to a semiconductor packaging method, and more particularly to a substrateless semiconductor packaging method.

Please refer to FIG. 1. FIG. 1 illustrates a conventional semiconductor package having a die 20, and the die 20 is attached to the substrate 10 via the adhesive 30. The die is wire bonded or flipped. A Flip chip (not shown) is connected to the conductive line on the substrate 10 and then electrically connected to the package pad 50 via the conductive via 40 on the substrate 10. In this conventional packaging method, whether the die is placed in a wire bonding manner or a flip chip manner, the thickness H1 of the final package is too thick, which is disadvantageous for miniaturized electronic products. Taking FIG. 1 as an example, the final package thickness H1 is equal to the thickness H2 of the substrate 10 itself plus the thickness H3 of the package. In response to the demand for miniaturized electronic products, it is necessary to reduce the thickness of semiconductor products after packaging.

A method of fabricating a substrateless semiconductor package, comprising: providing at least one semiconductor die, each of the semiconductor pads having a metal bump thereon. A light transmissive substrate is provided having a first surface and a second surface. An adhesive layer is formed on the first surface of the light transmissive substrate. The semiconductor crystal grains are attached to the adhesive layer in a flip chip manner.

A concave mold is provided and an encapsulant is poured into the recess of the female mold. Inverting the transparent substrate to which the semiconductor crystal grains are attached, and placing the transparent substrate in the concave mold with the second surface facing upward and the first surface facing downward, so that the semiconductor crystal grains are immersed in the encapsulant, but the exposed portion The metal bumps are outside the encapsulant. After curing the encapsulant, the concave mold is removed. Ultraviolet light is irradiated from the second surface of the light-transmitting substrate to embrittle the adhesive layer. The transparent substrate and the adhesive layer are removed to form a package, wherein the package exposes the top of each of the metal bumps.

Another method is to attach the semiconductor crystal grains to the adhesive layer in a flip chip manner. A potting compound is poured over the adhesive layer and the semiconductor die. The encapsulant is pressed using a concave mold. Remove the concave mold. The ultraviolet light is irradiated from the second surface of the light-transmitting substrate to embrittle the adhesive layer. The transparent substrate and the adhesive layer are removed to form a package, wherein the package exposes the top of each of the metal bumps.

Another method includes providing a light transmissive substrate. Forming an adhesive layer on the first surface of the transparent substrate to form a metal pattern layer on the adhesive layer, wherein the metal pattern layer comprises a plurality of metal inner pads, a plurality of metal outer pads and a plurality of metal wires. The semiconductor crystal grains are attached to the metal pattern layer in a flip chip manner, so that each metal bump is attached to each of the metal inner pads. An encapsulant is poured over the metal pattern layer and the semiconductor die. The concave mold is removed by pressing the encapsulant with a concave mold to fix the encapsulant after curing the encapsulant. The ultraviolet light is irradiated from the second surface of the light-transmitting substrate to embrittle the adhesive layer. The transparent substrate and the adhesive layer are removed to form a package, wherein the package exposes the bottom of the metal ferrule.

100 101 102‧‧‧Semiconductor grain

110‧‧‧Metal bumps

111‧‧‧ top

200‧‧‧Transparent substrate

201‧‧‧ first surface

202‧‧‧ second surface

210‧‧‧Adhesive layer

300‧‧‧ concave mold

301‧‧‧ Groove

400‧‧‧Package

900‧‧‧Package

910‧‧‧A type sub-package

920‧‧‧B type sub-package

500‧‧‧Metal pattern

510‧‧‧Metal inner pad

520‧‧‧Metal ferrule

530‧‧‧Metal connection

501‧‧‧ bottom

600‧‧‧Insulation mat

UV‧‧‧UV light

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; In the embodiment, the semiconductor die is placed on the transparent substrate; the second (B) is an embodiment in which the semiconductor die is immersed in the encapsulant; and the second (C) is an embodiment in which the transparent substrate is removed; (D) illustrates a package formed in an embodiment; FIG. 2(E) illustrates a sub-package divided in an embodiment; and FIG. 3(A) illustrates a semiconductor die placed in an embodiment. a transparent substrate; FIG. 3(B) illustrates a potting encapsulant in an embodiment; FIG. 3(C) illustrates a stamper encapsulant in an embodiment; and FIG. 3(D) illustrates an embodiment in which removal is performed a concave mold; FIG. 3(E) illustrates a transparent substrate removed in an embodiment to form a package; FIG. 3(F) illustrates a sub-package divided in an embodiment; and FIG. 4(A) shows In one embodiment, a metal pattern is formed on a transparent substrate; a fourth (B) is an embodiment in which a semiconductor die is placed on a transparent substrate; and a fourth (C) is an embodiment of a potting package. ; 4(D) is a view showing a stamper encapsulant in an embodiment; FIG. 4(E) is a view showing an embodiment of removing a transparent substrate to form a package; and FIG. 4(F) is a diagram showing division in an embodiment; Out of the package.

The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

2(A) to 2(E) are diagrams illustrating an embodiment of the present invention. Referring to FIG. 2(A), a plurality of semiconductor dies 100 101 103 are first provided, each of the semiconductor dies. A long metal bump 110 is placed on the bonding pad (not shown). A transparent substrate 200 is provided, which has a first surface 201 and a second surface 202, and is made of glass, quartz, acryl, etc., which can transmit visible light and ultraviolet light, on the first surface 201 of the transparent substrate 200. An adhesive layer 210 is coated on the upper layer. The semiconductor die 100 101 103 is then contacted with the top portion 111 of the metal bump 110 and fixed to the adhesive layer 210 in a flip chip manner. A concave mold 300 is provided, and the encapsulant 400 is injected into the recess 301 of the concave mold 300.

Then, referring to FIG. 2(B), the entire transparent substrate 200 is inverted, and the second surface 202 faces upward, and the first surface 201 faces downward to fix the semiconductor die 100 101 103 on the adhesive layer 210. After being immersed in the encapsulant 400, a portion of the metal bumps 110 are exposed. At this time, the encapsulant 400 has a high fluidity, so that the encapsulant 400 can completely fill the gap between the semiconductor crystal grains 100 101 103 .

Next, referring to the second (C) and the second (D), the ultraviolet light (UV) is irradiated from the second surface 202 of the transparent substrate 200 to make the adhesive layer 210 embrittled and lose the viscosity, and then move. In addition to the transparent substrate 200 and the adhesive layer 210, the concave mold 300 is finally removed to form a package 900. The package 900 encloses the semiconductor die 100 101 102 with an encapsulant 400, but exposes the top 111 of the metal bump 110. The package 900 of the present embodiment covers three semiconductor dies, which are merely examples, and may be coated with a plurality of semiconductor dies in practical applications. Finally, referring to FIG. 2(E), the package 900 is cut into a plurality of sub-packages 910. Each package 910 encapsulates a semiconductor die with a package adhesive 400 and exposes the top portion 111 of the metal bump 110 to form a The semiconductor package of the substrate, the metal bumps 110 simultaneously become the external pins of the semiconductor package.

3(A) to 3(F) are diagrams illustrating an embodiment of the present invention. Referring to FIG. 3(A), a plurality of semiconductor dies 100 101 103 are first provided, each of the semiconductor dies. A long metal bump 110 is placed on the bonding pad (not shown). A transparent substrate 200 is provided, which has a first surface 201 and a second surface 202, and is made of glass, quartz, acryl, etc., which can transmit visible light and ultraviolet light, on the first surface 201 of the transparent substrate 200. An adhesive layer 210 is coated on the upper layer. The semiconductor die 100 101 103 is then contacted with the top portion 111 of the metal bump 110 and fixed to the adhesive layer 210 in a flip chip manner.

Referring to FIG. 3(B), the encapsulant 400 is injected over the adhesive layer 210, and then the encapsulant 400 is pressed by a concave mold 300. Referring to FIG. 3(C), the concave mold 300 is biased, and the encapsulant 400 is pressed and shaped in the shape of the groove 301. The encapsulant 400 has fluidity, which fills the adhesive layer 210 and the semiconductor crystal. A gap between the granules 100 101 102 . Applying a relatively large pressure to the concave mold 300 allows the encapsulant 400 to have a better density. Referring to FIG. 3(D), after the encapsulant 400 is cured, the concave mold 300 is removed. The manner in which the encapsulant 400 is cured includes high temperature baking or irradiation with ultraviolet light.

Referring to FIG. 3(E), the adhesive layer 210 is irradiated from the second surface 202 of the transparent substrate 200 by using ultraviolet light to embrittle the adhesive layer 210 to reduce the viscosity, and then the transparent substrate 200 and the adhesive layer 210 are removed. A package 900 is formed. The package 900 encloses the semiconductor die 100 101 102 with an encapsulant 400, but exposes the top 111 of the metal bump 110. The package 900 of the present embodiment covers three semiconductor dies, which are merely examples, and may be coated with a plurality of semiconductor dies in practical applications. Finally, referring to FIG. 3(F), the package 900 is cut into a plurality of sub-packages 910, each of which encapsulates a semiconductor die with a package adhesive 400 and exposes the top portion 111 of the metal bump 110 to form a The semiconductor package of the substrate, the metal bumps 110 simultaneously become the external pins of the semiconductor package.

4(A) to 4(F) are explanatory views of an embodiment of the present invention. Referring to FIG. 4(A), an adhesive layer 210 is first formed on the first surface 201 of the transparent substrate 200, and then in an adhesive layer. 210 forms an insulating material, and the insulating material is patterned by a lithography process to form an insulating pad 600. Then, a metal material is formed, and then the metal material is patterned by a photolithography process to form a metal pattern 500. Methods of forming an insulating material and a metal material include physical vapor deposition (PVD), chemical vapor deposition (CVD), or printing coating.

The metal pattern 500 includes a metal inner pad 510, a metal outer pad 520, and a metal wire 530. The metal inner pad 510 is placed on the insulating pad 600, and the metal outer pad 520 and the metal wire 530 are on the adhesive layer 210. Referring to FIG. 4(B), the semiconductor die 100 101 102 is attached and fixed on the metal pad 510 in a flip chip manner. If the semiconductor die 100 101 102 need to be electrically connected to each other, Then, the metal connection 530 is connected.

Next, referring to FIG. 4(C), the encapsulant 400 is injected over the adhesive layer 210, and then the encapsulant 400 is pressed by a concave mold 300. Referring to FIG. 4(D), the concave mold 300 is biased, and the encapsulant 400 is pressed and shaped in the shape of the groove 301. The encapsulant 400 has fluidity, which fills the metal pattern 500 and is insulated. A gap between the pad 600 and the semiconductor die 100 101 102. Applying a relatively large pressure to the concave mold 300 allows the encapsulant 400 to have a better density. After the encapsulant 400 is cured, the concave mold 300 is removed. The manner in which the encapsulant 400 is cured includes high temperature baking or irradiation with ultraviolet light.

Referring to FIG. 4(E), the adhesive layer 210 is irradiated from the second surface 202 of the transparent substrate 200 by using ultraviolet light to embrittle the adhesive layer 210 to reduce the viscosity, and then the transparent substrate 200 and the adhesive layer 210 are removed to form. A package 900. The package 900 encloses the semiconductor die 100 101 102 with the encapsulant 400, but exposes the bottom 501 of the metal ferrule 520 and the metal trace 530.

Finally, referring to FIG. 4(F), the package 900 is cut into an A-type sub-package 910 and a B-type sub-package 920. However, the figure is merely an example. In practical applications, the package 900 can be divided into a plurality of parts. The A-type sub-package 910 and the plurality of B-type sub-packages 920. The A-type sub-package 910 encloses a semiconductor die 100 with a package adhesive 400, and the metal external pad 520 forms an external pin of the sub-package 910 to complete a substrateless semiconductor package. The B-type sub-package 920 is coated with at least two semiconductor dies 101 102 by an encapsulant 400. The die and the die are electrically connected by a metal connection 530. The metal ferrule 520 forms an external pin of the sub-package 920. A multi-semiconductor die package module without a substrate is completed.

The main function of the metal pattern in this embodiment is re-distrition. If the metal bumps of the semiconductor die are rather and dense, it is not suitable for directly soldering the top surface of the bump to the system board, and the metal pattern can be re-routed. The packaged semiconductor die has a large area and a large pitch of the external pins. Another function is that when used as a multi-module package, the metal wiring on the metal pattern can be used as an electrical connection between the plurality of semiconductor dies, and the semiconductor dies in the same sub-package contain crystal grains having different functions. For example, a control chip and a memory chip are simultaneously packaged in one sub-package, or a high-frequency chip (RF) and a base band are simultaneously packaged in one sub-package, but are not limited to the above two examples. .

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

Claims (10)

 A method of manufacturing a substrateless semiconductor package, comprising: providing at least one semiconductor die having a metal bump on each of the bonding pads; providing a transparent substrate having a first surface and a second Forming an adhesive layer on the first surface of the light transmissive substrate; attaching the semiconductor crystal grains to the adhesive layer in a flip chip manner; providing a concave mold and injecting an encapsulant to the concave surface In the groove of the mold; inverting the transparent substrate to which the semiconductor crystal grains are attached, and placing the transparent substrate into the concave mold with the second surface facing upward and the first surface facing downward, The semiconductor dies are immersed in the encapsulant, but a portion of the metal bumps are exposed outside the encapsulant; after curing the encapsulant, the concave mold is removed; from the second surface of the transparent substrate Irradiating the ultraviolet light to embrittle the adhesive layer; removing the transparent substrate and the adhesive layer to form a package, wherein the package exposes the top of each of the metal bumps.    A method of manufacturing a substrateless semiconductor package, comprising: providing at least one semiconductor die having a metal bump on each of the bonding pads; providing a transparent substrate having a first surface and a second Forming an adhesive layer on the first surface of the transparent substrate; attaching the semiconductor crystal grains to the adhesive layer in a flip chip manner; injecting an encapsulant on the adhesive layer and the semiconductor crystal grains Pressing the encapsulant with a concave mold; removing the concave mold; irradiating ultraviolet light on the second surface of the transparent substrate to embrittle the adhesive layer; removing the transparent substrate and the adhesive The layers are formed to form a package, wherein the package exposes the top of each of the metal bumps.    A method of manufacturing a substrateless semiconductor package, comprising: providing at least one semiconductor die having a metal bump on each of the bonding pads; providing a transparent substrate having a first surface and a second Forming an adhesive layer on the first surface of the transparent substrate; forming a metal pattern layer on the adhesive layer, wherein the metal pattern layer comprises a plurality of metal inner pads, a plurality of metal outer pads and a plurality of a metal wiring; the semiconductor crystal grains are attached to the metal pattern layer in a flip chip manner, such that each of the metal bumps is attached to each of the metal inner pads; and an encapsulant is poured in the metal pattern layer On the semiconductor die; pressing the encapsulant with a concave mold to shape the encapsulant; after curing the encapsulant, removing the concave mold; and irradiating ultraviolet light from the second surface of the transparent substrate Light absorbing the adhesive layer; removing the transparent substrate and the adhesive layer to form a package, wherein the package exposes the bottom of the metal ferrule.    The manufacturing method of claim 1, 2 or 3, further comprising: cutting the package into a plurality of A-type sub-packages, wherein each of the A-type sub-packages comprises one of the semiconductor dies.    The manufacturing method of claim 3, further comprising: cutting the package into a plurality of B-type sub-packages, wherein each of the B-type sub-packages comprises at least two of the semiconductor dies.    The manufacturing method of claim 3, further comprising: cutting the package into a plurality of A-type sub-packages and a plurality of B-type sub-packages.    The manufacturing method of claim 6, wherein each of the A-type sub-packages comprises one of the semiconductor dies, and each of the B-type sub-packages comprises at least two of the semiconductor dies.    The manufacturing method of claim 3, wherein the method of forming the metal pattern layer on the adhesive layer comprises: forming a plurality of insulating pads on the adhesive layer; forming a metal material on the insulating pads and the adhesive layer The metal material is patterned to form the metal pattern layer, wherein the metal interconnect pads are on the insulating pad, and the metal ferrules are on the adhesive layer.    The manufacturing method of claim 6 or 7, wherein in the B-type sub-package, the semiconductor dies are connected by the metal wires.    The manufacturing method of claim 6 or 7, wherein the semiconductor dies in the B-type sub-package comprise semiconductor dies of different application functions.