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CN107342264A - Fan-out package structure and its manufacture method - Google Patents

Fan-out package structure and its manufacture method Download PDF

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Publication number
CN107342264A
CN107342264A CN201710598696.6A CN201710598696A CN107342264A CN 107342264 A CN107342264 A CN 107342264A CN 201710598696 A CN201710598696 A CN 201710598696A CN 107342264 A CN107342264 A CN 107342264A
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CN
China
Prior art keywords
chip
substrate
face
plastic
conductive
Prior art date
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Granted
Application number
CN201710598696.6A
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Chinese (zh)
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CN107342264B (en
Inventor
林挺宇
陈�峰
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Priority to CN201710598696.6A priority Critical patent/CN107342264B/en
Publication of CN107342264A publication Critical patent/CN107342264A/en
Application granted granted Critical
Publication of CN107342264B publication Critical patent/CN107342264B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Micromachines (AREA)

Abstract

The invention discloses a kind of fan-out package structure, including：Substrate, the substrate include groove；The first chip being embedded in the groove of the substrate, first chip has first surface and the second surface relative with the first surface, the first surface of first chip includes device region, chip circuit and conductive welding disk, the material of wherein described substrate can be flowed under extraneous heat treatment condition so as to which the second surface and side wrap of first chip, the first surface of first chip be flushed with the top surface of substrate；The second chip being mounted on by wire bonding on the first surface of first chip, second chip has the first face and second face relative with the first face, first face of second chip includes device region, chip circuit and conductive welding disk, second face of second chip is fixed on the first surface of first chip, and the conductive welding disk on the first face of second chip is electrically connected to the conductive welding disk on first chip by lead.

Description

Fan-out package structure and its manufacture method
Technical field
The present invention relates to encapsulation field, more particularly to fan-out package structure and its manufacture method.
Background technology
In order to meet that electronic product increasingly develops to miniaturization, intelligent, high-performance and high reliability direction, chip Minimize, the intelligent quantity for causing chip package pin while lifting, the size of packaging pin also drops at the fast speed. I/O connection terminals are dispersed within chip surface area in traditional flip chip wafer level encapsulation scheme, so as to limit I/O Linking number.Fan-out-type wafer-level packaging can solve this problem, simultaneously because it has miniaturization, low cost and height The advantages that integrated level, therefore rapidly becoming the selection of novel chip and Wafer level packaging.
The back side of bare chip is generally embedded in the epoxy, then in the front of bare chip by existing fan-out package Form dielectric layer and reroute layer, and formed and electrically connected between the positive pad of bare chip and rewiring layer, rerouting layer can Again the route that peripheral epoxy regions are connected to from the I/O on bare chip is planned, then is formed on the pad for rerouting layer Soldered ball raised structures, it is consequently formed fan-out package structure.
Fan-out-type wafer-level packaging can realize that the density that three-dimensional stacks is maximum, and appearance and size is minimum, and significantly Improve chip performance and low-power consumption, but there is also it is certain the defects of.It is embedded in the epoxy by the back side of bare chip During, typically bare chip is directly adhered on adhesive layer, then bare chip is transferred in support substrate or support.So And because adhesive layer is easily deformed distortion, the reliability of product encapsulation is leveraged, reduces properties of product.Using injection The fan-out package of technique is extremely difficult in warpage control aspect；Slide and also be difficult to caused by injection molding packaging Material shrinkage in addition Controlled.
Therefore, it is necessary to new fan-out package structure and its manufacture method, so as to solve prior art at least in part Present in problem.
The content of the invention
For problems of the prior art, according to one embodiment of present invention, there is provided a kind of fan-out package knot Structure, including：Substrate, the substrate include groove；The first chip being embedded in the groove of the substrate, the first chip tool Have first surface and a second surface relative with the first surface, the first surface of first chip include device region, Chip circuit and conductive welding disk, wherein the material of the substrate can be flowed under extraneous heat treatment condition so as to by described first The second surface and side wrap of chip, the first surface of first chip flush with the top surface of substrate；Pass through wire bonding The second chip being mounted on the first surface of first chip, second chip have the first face and with the first face The second relative face, the first face of second chip include device region, chip circuit and conductive welding disk, second chip Second face is fixed on the first surface of first chip, and the conductive welding disk on the first face of second chip passes through lead The conductive welding disk being electrically connected on first chip；Plastic-sealed body, the plastic-sealed body is by second chip, first chip First surface and the top surface of substrate be encapsulated；And the rewiring structure on the plastic-sealed body is arranged on, the heavy cloth Cable architecture through the conductive through hole of the plastic-sealed body with the conductive welding disk on the first surface of first chip by electrically connecting.
In an embodiment of the present invention, reroute structure and pass through the conductive through hole through the plastic-sealed body and second core Conductive welding disk electrical connection on first face of piece.
In an embodiment of the present invention, fan-out package structure also includes at least one be arranged in the rewiring structure Conductive welding disk electricity on the first surface of first chip is connected respectively to correspondingly by individual solder bump, the rewiring structure Solder bump.
In an embodiment of the present invention, the rewiring structure includes conducting wire and is arranged between conducting wire Dielectric, one end of the conducting wire electrically connect with through the conductive through hole of the plastic-sealed body, the conducting wire it is another One end is electrically connected to corresponding solder bump.
According to another embodiment of the invention, there is provided a kind of manufacture method of fan-out package structure, including：Make band Reeded substrate；First chip is placed on to the bottom of groove, first chip has first surface and with described The relative second surface in one surface, the first surface of first chip includes device region, chip circuit and conductive welding disk, described The first surface of first chip is substantially flush with groove top, and the second surface of first chip contacts with bottom portion of groove； By wire bonding by the second chip attachment first chip first surface, second chip have the first face, with And second face relative with the first face, the first face of second chip includes device region, chip circuit and conductive welding disk, described Second face of the second chip is fixed on the first surface of first chip, the conductive weldering on the first face of second chip Disk is electrically connected to the conductive welding disk on first chip by lead；Plastic packaging is carried out, second chip is wrapped up and filled up Gap between first chip and second chip, the wherein top surface of plastic-sealed body are higher than the second of second chip Face；And formed on the top surface of the plastic-sealed body and reroute structure, the rewiring structure passes through through the plastic-sealed body Conductive through hole and the conductive weldering on first chip and/or the first surface of the second chip and/or the first face of the second chip Disk electrically connects.
In another embodiment of the present invention, it is mounted on described first before plastic packaging is carried out or by the second flip-chip Before the first surface of chip, the gap filled up between first chip and the groove.
In another embodiment of the present invention, the material of the substrate is selected from prepreg, pure glue, ABF, membranaceous plastic packaging Material, the viscose containing packing material, made using injection or die casting mode with reeded substrate；Fill up first chip with The method that gap between the groove is pressurizeed using heating, reach the glass transition temperature Tg of groove material, the material of substrate Material softening flowing, gap is filled up under the auxiliary of pressure.
In another embodiment of the present invention, after the gap between first chip and the groove is filled up, Continue heating pressurization so that the material solidification of the substrate.
In another embodiment of the present invention, this method also includes forming at least one weldering in the rewiring structure Expect salient point.
In another embodiment of the present invention, forming rewiring structure includes：Top surface and/or institute in the plastic-sealed body State formation first medium layer on the second face of the second chip；Punched in first medium layer and plastic-sealed body, until exposure described the Conductive welding disk on one chip and/or second chip；Form one or more layers conductive material；And pass through photoetching and etching Technology removes region that need not be conductive, so as to form required conductive through hole and conducting wire.
Brief description of the drawings
For the above and other advantages and features of each embodiment that the present invention is furture elucidated, refer to the attached drawing is presented The more specifically description of various embodiments of the present invention.It is appreciated that these accompanying drawings only describe the exemplary embodiments of the present invention, therefore It is restriction on its scope to be not to be regarded as.In the accompanying drawings, in order to cheer and bright, identical or corresponding part will use identical or class As mark represent.
Fig. 1 shows the cross-sectional view of fan-out package structure 100 according to an embodiment of the invention.
Fig. 2A to Fig. 2 D shows to form the diagrammatic cross-section of the process of fan-out package structure according to an embodiment of the invention.
Fig. 3 shows to form the flow chart of fan-out package structure according to an embodiment of the invention.
Fig. 4 shows the cross-sectional view of fan-out package structure 400 according to another embodiment of the invention.
Fig. 5 shows the cross-sectional view of the second chip 450 according to the present invention.
Fig. 6 A to Fig. 6 F show to form the section of the process of fan-out package structure according to another embodiment of the invention Schematic diagram.
Fig. 7 shows to form the flow chart of fan-out package structure according to another embodiment of the invention.
Fig. 8 shows the cross-sectional view of fan-out package structure 800 according to still another embodiment of the invention.
Fig. 9 shows the cross-sectional view of fan-out package structure 900 according to still a further embodiment.
Figure 10 A to Figure 10 F show to form cuing open for the process of fan-out package structure according to still another embodiment of the invention Face schematic diagram.
Figure 11 shows to form the flow chart of fan-out package structure according to still another embodiment of the invention.
Embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize Know can in the case of neither one or multiple specific details or with it is other replacement and/or addition method, material or component Implement each embodiment together.In other situations, it is not shown or known structure, material or operation is not described in detail in order to avoid making this The aspects of each embodiment of invention is obscure.Similarly, for purposes of explanation, specific quantity, material and configuration are elaborated, with Comprehensive understanding to embodiments of the invention is just provided.However, the present invention can be implemented in the case of no specific detail.This Outside, it should be understood that each embodiment shown in accompanying drawing is illustrative expression and is not drawn necessarily to scale.
In this manual, the reference to " one embodiment " or " embodiment " means to combine embodiment description Special characteristic, structure or characteristic are included at least one embodiment of the invention.In the short of this specification middle appearance everywhere Language is not necessarily all referring to the same embodiment " in one embodiment ".
It should be noted that processing step is described with particular order for embodiments of the invention, but this is simply Convenience distinguishes each step, and is not the sequencing for limiting each step, in different embodiments of the invention, can be according to work Skill is adjusted to adjust the sequencing of each step.
In order to solve in the prior art, bare chip to be directly adhered on adhesive layer bare chip is transferred into support substrate again Or on support during, adhesive layer is easily deformed distortion, the problem of influenceing the reliability of product encapsulation, and the present invention provides a kind of Fan-out package structure, the fan-out package structure does not include the bonding Rotating fields for fixed chip, and is sealed in fan-out-type In the manufacturing process of assembling structure, without using the interim fixed chip of tack coat.Encapsulation caused by so as to avoid tack coat distortion can By sex chromosome mosaicism.
Fig. 1 shows the cross-sectional view of fan-out package structure 100 according to an embodiment of the invention.Fan-out-type Encapsulating structure 100 includes substrate 110 and the chip 120 being embedded in substrate 110.Substrate 110, which has, to be used to accommodate chip 120 Groove.After chip 120 is placed in into the groove, the material of substrate 110 can be flowed under extraneous heat treatment condition so that will Chip wraps up.For example, the material of substrate 110 can be prepreg, pure glue, ABF (Ajinomoto Build-up Film), The materials such as membranaceous plastic packaging material (Epoxy Molding Compound Sheet), viscose containing packing material.
Chip 120 has the first surface 120a and second surface 120b relative with first surface 120a, chip 120 First surface 120a may include device region, chip circuit and conductive welding disk (not shown).
The second surface 120b of chip 120 and side are encapsulated by substrate 110, the first surface 120a of chip 120 It is substantially flush with the top surface 110a of substrate 110.
There is weight on the first surface 120a of chip 120 and the surface of the substrate 110 flushed with first surface 120a Wire structures 130, reroute structure 130 and be used to the conductive welding disk on chip 120 being electrically connected to one or more solder bumps 140.In some embodiments of the invention, reroute structure 130 may include conducting wire 131 and be arranged on conducting wire it Between dielectric 132.One end of conducting wire 131 electrically connects with the conductive welding disk of chip 120.Conducting wire 131 it is another One or more external pads 133 are provided with end.One or more solder bumps 140 and one or more external pads 133 Directly contact.In some other embodiment of the present invention, reroute structure 130 and may not include external pad 133, one or more Individual solder bump 140 is formed directly into the top of conducting wire 131, forms BOT structures (Bump On Tracing).
By reroute structure 130 can plan again chip 120 external pad position and be connected with external circuit Route.Due to the area on the surface of chip 120 and the area for the substrate surface being fanned out to can be made full use of, therefore available for electricity mutually The surface area of platoon cloth greatly increases, so that interconnection density maximizes, while can increase the size of soldered ball 140.
Form the process of fan-out package structure according to one embodiment of present invention with reference to Fig. 2 and Fig. 3 descriptions.Figure 2A to Fig. 2 D shows to form the diagrammatic cross-section of the process of fan-out package structure according to an embodiment of the invention.Fig. 3 shows root The flow chart of fan-out package structure is formed according to embodiments of the invention.
First, in step 310, make with reeded substrate 210, as shown in Figure 2 A.In some embodiments of the present invention In, the modes such as injection, die casting can be used, are formed using resin or powder with reeded substrate.Substrate can be square piece or circle Piece.The material of substrate 210 can be flowed under extraneous heat treatment condition so as to which chip be wrapped up.For example, the material of substrate 210 can To be prepreg, pure glue, ABF (Ajinomoto Build-up Film), membranaceous plastic packaging material (Epoxy Molding Compound Sheet), the material such as viscose containing packing material.When the material of substrate 210 is prepreg, should use The mode of low temperature die casting is formed with reeded substrate, so that it is guaranteed that the semi-cured state of prepreg does not change.Substrate The shape of 210 further grooves can be similar to the shape of chip to be packaged, and be slightly larger than chip to be packaged.However, the concave of substrate 210 The shape not limited to this of groove, the shape of groove may differ from the shape of chip to be packaged.
Next, in step 320, chip 220 is placed on to the bottom of groove, as shown in Figure 2 B.Chip 220 has first The surface 220a and second surface 220b relative with first surface 220a, the first surface 220a of chip 220 may include device Area, chip circuit and conductive welding disk (not shown).In the embodiment shown in Fig. 2 B, the first surface 220a of chip 220 It is substantially flush with groove top, and the second surface 220b of chip 220 contacts with bottom portion of groove.
In a particular embodiment of the present invention, because the material of substrate 210 is resin material, substrate 210 is in heat packs It is not fully cured before chip, resin there can be certain viscosity under the conditions of certain temperature, so being placed by chip 220 During the bottom of groove, chip or substrate 210 need to only be heated, and heating-up temperature is no more than the Tg points of material, and Time is shorter, you can it is good to ensure that chip bonds with groove.In addition, the groove of substrate 210 is generally rectangular, incited somebody to action by chip mounter Chip 220 is placed on during the bottom of groove, and the visual identifying system (CCD) of chip mounter can capture groove periphery frame and enter Row positioning, positioning precision are higher, it can be ensured that the accurate positioning of chip 220.
In step 330, melt groove, the gap filled up between chip and groove, as shown in Figure 2 C.The one of the present invention In a little embodiments, the method for heating pressurization can be used, reaches the glass transition temperature Tg of groove material, material softening flows, Gap is filled up under the auxiliary of pressure.When heating is pressurized to certain time, the colloid in material is converted into solid state, so as to protect Card shape does not change.By above-mentioned steps, the second surface 220b of chip 220 and side are encapsulated by substrate 210, The first surface 220a and substrate 210 of chip 220 one side are substantially flush.
Next, in step 340, formed on the first surface of chip and the surface of the substrate flushed with first surface Reroute structure and one or more solder bumps, the final encapsulating structure obtained as shown in Figure 2 D.Structure is rerouted to be used for Conductive welding disk on chip is electrically connected to one or more solder bumps.For example, the concrete technology for forming rewiring structure can It is included on the first surface of chip and the surface of the substrate flushed with first surface and forms dielectric layer, passes through photoetching and etching Technology removes certain media layer to expose the conductive welding disk on chip, then passes through the techniques such as PVD, ALD, chemical plating and plating One or more layers conductive material is formed, then is removed by photoetching and lithographic technique and does not need conductive region, needed for being formed Conducting wire.Also optionally form second dielectric layer in conducting wire, and part the is removed by photoetching and lithographic technique Second medium layer reroutes the external pad of structure with exposure.
Example embodiment
In one particular embodiment of the present invention, can be formed using prepreg with reeded substrate 210.Half is solid The material for changing piece is semi-solid preparation insulating materials, can be selected in structure and includes glass-fiber-fabric and semi-solid preparation resin and resin extender particle BT or FR4 prepregs, also can be selected structure in be free of reinforcing material ABF prepregs or other all circuit board materials Semi-solid preparation insulating resin sheet.Reinforcing material employed in prepreg can be fiber, for example, carbon fiber, glass fibre, Aramid fibre, high-strength polyethylene fiber, boron fibre, steel wire fibre etc., preferably using carbon fiber.
The matrix resin of prepreg can use thermosetting resin or thermoplastic resin, preferably using thermosetting resin. Thermosetting resin may be selected from epoxy resin, phenolic resin, vinylester resin, unsaturated polyester resin, bimaleimide resin, Bismaleimide-triazine resin, cyanate ester resin, benzoxazine colophony etc..
It can be formed with reeded substrate 210, the wherein temperature of low temperature die casting by carrying out low temperature die casting to prepreg In the range of 100 DEG C to 120 DEG C, so that it is guaranteed that the semi-cured state of prepreg is constant.The shape of the further groove of substrate 210 can class The shape of chip to be packaged is similar to, and is slightly larger than chip to be packaged.
After chip 220 is placed on into the bottom of groove, softens semi-solid preparation numerical value by low-temperature heat pressurization and fill out Full gap between chip and groove, improving heating-up temperature makes semi-solid preparation resin cure.
Structure is rerouted next, being formed on the first surface of chip and the surface of the substrate flushed with first surface And one or more solder bumps, finally obtain encapsulating structure as shown in Figure 1.
Because the backing material for after substrate solidifies, encapsulating chip typically no longer has mobility, therefore according to the present invention Scheme formed fan-out package structure can avoid for bond chip tack coat distort caused by package reliability problem. On the other hand, the present invention is placed in groove by preparing substrate with groove in advance, then by chip, by heating the methods of pressurizeing The gap filled up between chip and groove, compared with traditional plastic package structure, the encapsulating structure that the present invention is formed is stable, size Precision is high, is unlikely to deform distortion.
Fig. 4 shows the cross-sectional view of fan-out package structure 400 according to another embodiment of the invention.It is fanned out to Type encapsulating structure 400 includes substrate 410 and the first chip 420 being embedded in substrate 410.Substrate 410, which has, to be used to accommodate The groove of first chip 420.After the first chip 420 is placed in into the groove, the material of substrate 410 is under extraneous heat treatment condition It can flow so as to which the first chip be wrapped up.For example, the material of substrate 410 can be prepreg, pure glue, ABF (Ajinomoto Build-up Film), membranaceous plastic packaging material (Epoxy Molding Compound Sheet), contain filling material The materials such as the viscose of material.
First chip 420 has a first surface 420a and relative with first surface 420a second surface 420b, and first The first surface 420a of chip 420 may include device region, chip circuit and conductive welding disk (not shown).
The second surface 420b of first chip 420 and side are encapsulated by substrate 410, and the first of the first chip 420 Surface 420a and substrate 410 top surface 410a are substantially flush.
Fan-out package structure 400 also includes the second chip being inverted on the first surface 420a of the first chip 420 450.Fig. 5 shows the cross-sectional view of the second chip 450 according to the present invention.Second chip 450 have first surface 450a, And the second surface 450b, the first surface 450a of second chip 450 relative with first surface 450a may include device region, core Piece circuit (not shown) and the solder bump 451 above chip circuit.Solder bump 451 can be soldered ball or weldering Post.
Fig. 4 is returned to, the solder bump 451 of the second chip 450 electrically connects with the conductive welding disk of the first chip 420.Second The outside of chip 450 has a plastic-sealed body 460, and plastic-sealed body 460 is by the second chip 450 and the first surface 420a of the first chip 420 And the top surface 410a of substrate 410 is encapsulated.The top surface 460a of plastic-sealed body 460 and the second chip 450 second surface 450b It is substantially flush or the slightly above second surface 450b of the second chip 450.
Have on the top surface 460a of plastic-sealed body 460 and/or the second surface 450b of the second chip 450 and reroute structure 430, reroute structure 430 and be used to the conductive welding disk on the first chip 420 being electrically connected to one or more solder bumps 440. In some embodiments of the invention, rerouting structure 430 may include conducting wire 431 and is arranged between conducting wire Dielectric 432.The conduction that one end of conducting wire 431 passes through the chip 420 of conductive through hole 461 and first in plastic-sealed body 460 Pad electrically connects.One or more external pads 433 are provided with the other end of conducting wire 431.One or more solders are convex Point 440 directly contacts with one or more external pads 433.In some other embodiment of the present invention, structure 430 is rerouted External pad 433 is may not include, one or more solder bumps 440 are formed directly into the top of conducting wire 431.
By reroute structure 430 can plan again the first chip 420 external pad position and and external circuit The route of connection.Due to that can make full use of the top surface 460a's of the plastic-sealed body 460 and/or second surface 450b of the second chip 450 Area, therefore greatly increased available for the surface area that arrangement is electrically interconnected, so that interconnection density maximizes, while soldered ball can be increased 440 size.
Form the process of fan-out package structure according to another embodiment of the invention with reference to Fig. 6 and Fig. 7 descriptions. Fig. 6 A to Fig. 6 F show to form the diagrammatic cross-section of the process of fan-out package structure according to another embodiment of the invention.Figure 7 show to form the flow chart of fan-out package structure according to another embodiment of the invention.
First, in step 710, make with reeded substrate 610, as shown in Figure 6A.In some embodiments of the present invention In, the modes such as injection, die casting can be used, are formed using resin or powder with reeded substrate.Substrate can be square piece or circle Piece.The material of substrate 610 can be flowed under extraneous heat treatment condition so as to which chip be wrapped up.For example, the material of substrate 610 can To be prepreg, pure glue, ABF (Ajinomoto Build-up Film), membranaceous plastic packaging material (Epoxy Molding Compound Sheet), the material such as viscose containing packing material.When the material of substrate 610 is prepreg, should use The mode of low temperature die casting is formed with reeded substrate, so that it is guaranteed that the semi-cured state of prepreg does not change.Substrate The shape of 610 further grooves can be similar to the shape of chip to be packaged, and be slightly larger than chip to be packaged.However, the concave of substrate 610 The shape not limited to this of groove, the shape of groove may differ from the shape of chip to be packaged.
Next, in step 720, the first chip 620 is placed on to the bottom of groove, as shown in Figure 6B.First chip 620 With the first surface 620a and second surface 620b relative with first surface 620a, the first surface of the first chip 620 620a may include device region, chip circuit and conductive welding disk (not shown).In the embodiment shown in Fig. 6 B, the first chip 620 first surface 620a is substantially flush with groove top, and the second surface 620b of the first chip 620 connects with bottom portion of groove Touch.
In step 730, the upside-down mounting of the second chip 650 is mounted on to the first surface 620a of the first chip 620, such as Fig. 6 C institutes Show.The first surface 650a of second chip 650 may include device region, chip circuit (not shown) and on chip circuit The solder bump 651 of side.Second chip 650 and the first chip 620 are formed by solder bump 651 to be interconnected.
Optionally, after stage 720 and before or after step 730, melt the groove of substrate 610, fill up Gap between first chip and groove, as shown in Figure 6 D.In some embodiments of the invention, the side of heating pressurization can be used Method, reach the glass transition temperature Tg of groove material, material softening flowing, gap is filled up under the auxiliary of pressure.Work as heating It is pressurized to certain time, the colloid in material is converted into solid state, so as to ensure that shape does not change.Pass through above-mentioned step Suddenly, the second surface 620b of the first chip 620 and side are encapsulated by substrate 610, the first surface of the first chip 620 620a and substrate 610 one side are substantially flush.
In the alternative embodiment of the present invention, the step of can melting without groove.But subsequently to the second chip During 650 progress plastic packaging, the groove for making substrate 610 using the temperature and pressure of plastic package process melts, and fills up the first chip and groove Between gap.
Next, in step 740, carry out plastic packaging process, the second chip 650 wrapped, and fill up the first chip 620 with Gap between second chip 650, as illustrated in fig. 6e.The top surface 660a of plastic-sealed body 660 and the second chip 650 second surface 650b is substantially flush or the slightly above second surface 650b of the second chip 650.
Next, in step 750, conductive through hole is formed in plastic-sealed body, and in the top surface and/or the second chip of plastic-sealed body Second surface on formed and reroute structure and one or more solder bumps, the final structure obtained shown in Fig. 6 F.Weight cloth Cable architecture is used to the conductive welding disk on the first chip being electrically connected to one or more solder bumps.For example, form conductive through hole It may include to form first medium layer on the top surface of plastic-sealed body with the concrete technology for rerouting structure, in first medium layer and plastic packaging Punching in vivo, until the conductive welding disk on the first chip of exposure, is then formed by techniques such as PVD, ALD, chemical plating or plating One or more layers conductive material, then removed by photoetching and lithographic technique and do not need conductive region, so as to form required conduction Circuit.Second dielectric layer is also optionally formed in conducting wire, and part second is removed by photoetching and lithographic technique and is situated between Matter layer reroutes the external pad of structure with exposure.
Fig. 8 shows the cross-sectional view of fan-out package structure 800 according to still another embodiment of the invention.It is fanned out to Type encapsulating structure 800 includes substrate 810 and the first chip 820 being embedded in substrate 810.Substrate 810, which has, to be used to accommodate The groove of first chip 820.After the first chip 820 is placed in into the groove, the material of substrate 810 is under extraneous heat treatment condition It can flow so as to which the first chip be wrapped up.For example, the material of substrate 810 can be prepreg, pure glue, ABF (Ajinomoto Build-up Film), membranaceous plastic packaging material (Epoxy Molding Compound Sheet), contain filling material The materials such as the viscose of material.
First chip 820 has a first surface 820a and relative with first surface 820a second surface 820b, and first The first surface 820a of chip 820 may include device region, chip circuit and conductive welding disk (not shown).
The second surface 820b of first chip 820 and side are encapsulated by substrate 810, and the first of the first chip 820 Surface 820a and substrate 810 top surface 810a are substantially flush.
Fan-out package structure 800 also includes being mounted on the first surface 820a of the first chip 820 by wire bonding mode On the second chip 850.Second chip 850 has first surface 850a and the second surface relative with first surface 850a 850b, the first surface 850a of the second chip 850 may include device region, chip circuit and conductive welding disk (not shown).The Conductive welding disk on first face 850a of two chips 850 is electrically connected to the conductive welding disk on the first chip 820 by lead.Second The second surface of chip 850 can be fixed on by intermediate layer on the first surface 820a of first chip 820.
There is plastic-sealed body 860 outside the second chip 850, plastic-sealed body 860 is by the second chip 850 and the first chip 820 First surface 820a and the top surface 810a of substrate 810 be encapsulated.
Have on the top surface 860a of plastic-sealed body 860 and reroute structure 830, reroute structure 830 and be used for the first chip Conductive welding disk on 820 is electrically connected to one or more solder bumps 840.In some embodiments of the invention, knot is rerouted The dielectric 832 that structure 830 may include conducting wire 831 and be arranged between conducting wire.One end of conducting wire 831 leads to The conductive through hole 861 crossed in plastic-sealed body 860 electrically connects with the conductive welding disk of the first chip 820.On the other end of conducting wire 831 It is provided with one or more external pads 833.One or more solder bumps 840 and one or more external pads 833 are direct Contact.In some other embodiment of the present invention, reroute structure 830 and may not include external pad 833, one or more weldering Material salient point 840 is formed directly into the top of conducting wire 831.
By reroute structure 830 can plan again the first chip 820 external pad position and and external circuit The route of connection.Due to that can make full use of the top surface 860a's of the plastic-sealed body 860 and/or second surface 850b of the second chip 850 Area, therefore greatly increased available for the surface area that arrangement is electrically interconnected, so that interconnection density maximizes, while soldered ball can be increased 840 size.
Fig. 9 shows the cross-sectional view of fan-out package structure 900 according to still a further embodiment.It is fanned out to Type encapsulating structure 900 is similar with the fan-out package structure 800 shown in Fig. 8, and difference is, in fan-out package structure In 900, the conductive welding disk that structure 930 is directly electrically connected to the second chip by one or more conductive through holes 962 is rerouted.
Form the mistake of fan-out package structure according to still another embodiment of the invention with reference to Figure 10 and Figure 11 descriptions Journey.Figure 10 A to Figure 10 F show to form the section signal of the process of fan-out package structure according to still another embodiment of the invention Figure.Figure 11 shows to form the flow chart of fan-out package structure according to still another embodiment of the invention.
Step 1110 is similar to step 720 with the step 710 shown in Fig. 7 to step 1120, for the purpose of simplifying the description, omits it Specifically describe.
In step 1130, the second chip 1050 is mounted on by the first surface 1020a of the first chip 1020 by wire bonding, As illustrated in figure 10 c.The first surface 1050a of second chip 1050 may include device region, chip circuit and conductive welding disk (in figure not Show).Second chip 1050 and the first chip 1020 are formed by lead to be interconnected.
Optionally, after step 1120 and before or after step 1130, melt the groove of substrate 1010, fill out Full gap between first chip and groove, as shown in Figure 10 D.In some embodiments of the invention, heating pressurization can be used Method, reach the glass transition temperature Tg of groove material, material softening flowing, gap filled up under the auxiliary of pressure.When It is pressurized to certain time, the colloid in material is converted into solid state, so as to ensure that shape does not change.By above-mentioned The second surface 1020b of first chip 1020 and side are encapsulated by step, substrate 1010, and the first of the first chip 1020 Surface 1020a and substrate 1010 top surface are substantially flush.
In the alternative embodiment of the present invention, the step of can melting without groove.But subsequently to the second chip 1050 carry out plastic packaging when, the groove for making substrate 1010 using the temperature and pressure of plastic package process melts, fill up the first chip with it is recessed Gap between groove.
Next, in step 1140, plastic packaging process is carried out, the second chip 1050 is wrapped, and fill up the first chip 1020 and the second gap between chip 1050, as shown in figure 10e.The top surface 1060a of plastic-sealed body 1060 and the second chip 1050 Second surface 1050b be substantially flush or the slightly above second surface 1050b of the second chip 1050.
Next, in step 1150, conductive through hole is formed in plastic-sealed body, and in the top surface 1060a of plastic-sealed body and/or Formed on the second surface of two chips and reroute structure and one or more solder bumps, the final knot obtained shown in Figure 10 F Structure.Structure is rerouted to be used to the conductive welding disk on the first chip being electrically connected to one or more solder bumps.Led for example, being formed Electric through-hole and the concrete technology of rewiring structure may include to form first medium layer on the top surface of plastic-sealed body, in first medium layer Punched with plastic-sealed body, until the conductive welding disk on the first chip of exposure, then passes through the works such as PVD, ALD, chemical plating or plating Skill forms one or more layers conductive material, then is removed by photoetching and lithographic technique and do not need conductive region, so as to be formed Need conducting wire.Second dielectric layer is also optionally formed in conducting wire, and part is removed by photoetching and lithographic technique Second dielectric layer reroutes the external pad of structure with exposure.
Although described above is various embodiments of the present invention, however, it is to be understood that they are intended only as example to present , and without limitation.For those skilled in the relevant art it is readily apparent that various combinations, modification can be made to it With change without departing from the spirit and scope of the present invention.Therefore, the width of the invention disclosed herein and scope should not be upper State disclosed exemplary embodiment to be limited, and should be defined according only to appended claims and its equivalent substitution.

Claims (10)

1. a kind of fan-out package structure, including：
Substrate, the substrate include groove；
The first chip being embedded in the groove of the substrate, first chip have first surface and with described first The relative second surface in surface, the first surface of first chip include device region, chip circuit and conductive welding disk, wherein institute State the material of substrate and can be flowed under extraneous heat treatment condition so as to by the second surface and side wrap of first chip, The first surface of first chip flushes with the top surface of substrate；
The second chip being mounted on by wire bonding on the first surface of first chip, second chip have first Face and second face relative with the first face, the first face of second chip include device region, chip circuit and conductive weldering Disk, the second face of second chip is fixed on the first surface of first chip, on the first face of second chip Conductive welding disk conductive welding disk on first chip is electrically connected to by lead；
Plastic-sealed body, the plastic-sealed body encapsulate the top surface of second chip, the first surface of first chip and substrate Get up；And
The rewiring structure being arranged on the plastic-sealed body, the rewiring structure pass through the conductive through hole through the plastic-sealed body Electrically connected with the conductive welding disk on the first surface of first chip.
2. fan-out package structure as claimed in claim 1, it is characterised in that the rewiring structure passes through through the modeling The conductive through hole of envelope body electrically connects with the conductive welding disk on the first face of second chip.
3. fan-out package structure as claimed in claim 1, it is characterised in that also include being arranged in the rewiring structure At least one solder bump, it is described rewiring structure the conductive welding disk electricity on the first surface of first chip is connected respectively It is connected to corresponding solder bump.
4. fan-out package structure as claimed in claim 3, it is characterised in that it is described rewiring structure include conducting wire with And the dielectric between conducting wire is arranged on, one end of the conducting wire and the conductive through hole electricity through the plastic-sealed body Connection, the other end of the conducting wire are electrically connected to corresponding solder bump.
5. a kind of manufacture method of fan-out package structure, including：
Make with reeded substrate；
First chip is placed on to the bottom of groove, first chip have first surface and with the first surface phase To second surface, the first surface of first chip includes device region, chip circuit and conductive welding disk, first chip First surface be substantially flush with groove top, and the second surface of first chip contacts with bottom portion of groove；
By wire bonding by the second chip attachment first chip first surface, second chip have first Face and second face relative with the first face, the first face of second chip include device region, chip circuit and conductive weldering Disk, the second face of second chip is fixed on the first surface of first chip, on the first face of second chip Conductive welding disk conductive welding disk on first chip is electrically connected to by lead；
Progress plastic packaging, the gap that second chip is wrapped up and filled up between first chip and second chip, its The top surface of middle plastic-sealed body is higher than the second face of second chip；And
Formed on the top surface of the plastic-sealed body and reroute structure, the rewiring structure passes through the conduction through the plastic-sealed body Through hole and the conductive welding disk electricity on first chip and/or the first surface of the second chip and/or the first face of the second chip Connection.
6. method as claimed in claim 5, it is characterised in that be mounted on institute before plastic packaging is carried out or by the second flip-chip Before the first surface for stating the first chip, the gap filled up between first chip and the groove.
7. method as claimed in claim 6, it is characterised in that the material of the substrate is selected from prepreg, pure glue, ABF, film Shape plastic packaging material, the viscose containing packing material, made using injection or die casting mode with reeded substrate；Fill up described first Gap between chip and the groove is reached the glass transition temperature Tg of groove material, served as a contrast using the method for heating pressurization The material softening flowing at bottom, gap is filled up under the auxiliary of pressure.
8. method as claimed in claim 7, it is characterised in that filling up the gap between first chip and the groove Afterwards, heating pressurization is continued so that the material solidification of the substrate.
9. method as claimed in claim 5, it is characterised in that also include forming at least one weldering in the rewiring structure Expect salient point.
10. method as claimed in claim 5, it is characterised in that forming rewiring structure includes：
First medium layer is formed on the top surface of the plastic-sealed body and/or the second face of second chip；
Punched in first medium layer and plastic-sealed body, until the conduction on exposure first chip and/or second chip Pad；
Form one or more layers conductive material；And
Removed by photoetching and lithographic technique and do not need conductive region, so as to form required conductive through hole and conducting wire.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110634824A (en) * 2018-06-22 2019-12-31 何崇文 Chip packaging structure and manufacturing method thereof
JP2020117672A (en) * 2019-01-28 2020-08-06 株式会社ダイセル Sheet-like prepreg for sealing fan-out package
CN118099107A (en) * 2024-04-24 2024-05-28 甬矽半导体(宁波)有限公司 Semiconductor packaging structure and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101246882A (en) * 2007-02-16 2008-08-20 育霈科技股份有限公司 Semiconductor assembly package structure with multiple chips and method thereof
CN102986314A (en) * 2010-07-06 2013-03-20 株式会社藤仓 Laminated wiring board and manufacturing method for same
CN103650134A (en) * 2011-10-20 2014-03-19 松下电器产业株式会社 Semiconductor device
CN105810647A (en) * 2016-04-22 2016-07-27 宜确半导体（苏州）有限公司 Radio-frequency switch integration module and integration method thereof, and radio-frequency front-end integrated circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101246882A (en) * 2007-02-16 2008-08-20 育霈科技股份有限公司 Semiconductor assembly package structure with multiple chips and method thereof
CN102986314A (en) * 2010-07-06 2013-03-20 株式会社藤仓 Laminated wiring board and manufacturing method for same
CN103650134A (en) * 2011-10-20 2014-03-19 松下电器产业株式会社 Semiconductor device
CN105810647A (en) * 2016-04-22 2016-07-27 宜确半导体（苏州）有限公司 Radio-frequency switch integration module and integration method thereof, and radio-frequency front-end integrated circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110634824A (en) * 2018-06-22 2019-12-31 何崇文 Chip packaging structure and manufacturing method thereof
CN110634824B (en) * 2018-06-22 2021-11-26 何崇文 Chip packaging structure and manufacturing method thereof
JP2020117672A (en) * 2019-01-28 2020-08-06 株式会社ダイセル Sheet-like prepreg for sealing fan-out package
JP7282535B2 (en) 2019-01-28 2023-05-29 株式会社ダイセル Sheet prepreg for encapsulating fan-out packages
CN118099107A (en) * 2024-04-24 2024-05-28 甬矽半导体(宁波)有限公司 Semiconductor packaging structure and preparation method thereof
CN118099107B (en) * 2024-04-24 2024-08-23 甬矽半导体(宁波)有限公司 Semiconductor packaging structure and preparation method thereof

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