CN118099107B - Semiconductor packaging structure and preparation method thereof - Google Patents
Semiconductor packaging structure and preparation method thereof Download PDFInfo
- Publication number
- CN118099107B CN118099107B CN202410494155.9A CN202410494155A CN118099107B CN 118099107 B CN118099107 B CN 118099107B CN 202410494155 A CN202410494155 A CN 202410494155A CN 118099107 B CN118099107 B CN 118099107B
- Authority
- CN
- China
- Prior art keywords
- layer
- wiring
- plastic package
- package body
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a semiconductor packaging structure and a preparation method thereof, relating to the technical field of chip packaging, the semiconductor packaging structure comprises a first plastic packaging body, a first wiring combination layer, a first chip and a second plastic packaging body, wherein the first wiring combination layer is arranged on the first plastic packaging body, the first chip is mounted on the first wiring combination layer, the second plastic package body is arranged on the first wiring combination layer and is coated outside the first chip, wherein materials of the first plastic package body and the second plastic package body are the same, and the first plastic package body at least covers one side surface of the first wiring combination layer so as to support the first wiring combination layer. Compared with the prior art, the invention has high-density integration, high-density interconnection and high reliability, avoids using a carrier wafer, omits a glue film layer, and avoids influencing the wiring conductivity by the residual glue film layer after the conventional carrier is stripped. And when wiring patterning is performed, no adhesive film layer exists, so that detachment can not be caused in the wet process, and the reliability of the wet process is ensured.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a semiconductor packaging structure and a preparation method thereof.
Background
With the rapid development of the semiconductor industry, fan-out wafer level package (FOWLP) structures are widely used in the semiconductor industry. The conventional technology generally adopts the steps of cutting off a single chip from a wafer, packaging the single chip on a carrier wafer, performing plastic packaging by using a plastic packaging body to reconstruct the wafer, and changing the pin end of the chip again by using a rewiring technology, and has the main advantages of high-density integration, small size of packaged products, excellent product performance, high signal transmission frequency and the like. The fan-out packaging technology mainly realizes multi-pin output, so that the output pin spacing is smaller.
The existing fan-out type wafer level packaging technology has the problem of wafer warpage, and a wiring layer is usually prepared after a carrier wafer is glued with a glue film, and finally, the operation of de-bonding and separation is carried out, so that the conductivity of subsequent wiring is easily affected by the residue of the glue film layer after bonding and separation. And when wiring patterning is performed, the wet process easily causes the film layer to be decomposed by the influence of chemicals and exposure, and even causes the carrier wafer to be separated from the bonded film layer.
Disclosure of Invention
The invention aims at providing a semiconductor packaging structure and a preparation method thereof, which can utilize a plastic package body as a supporting substrate, have high-density integration, high-density interconnection and high reliability, omit a glue film layer and avoid the influence of the residual glue film layer after stripping of a conventional carrier on wiring conductivity. And the wet process can not lead to detachment when the wiring patterning is performed, so that the reliability of the wet process is ensured.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a semiconductor package structure, comprising:
A first plastic package body;
The first wiring combination layer is arranged on the first plastic package body;
a first chip mounted on the first wiring combination layer;
the second plastic package body is arranged on the first wiring combination layer and is coated outside the first chip;
The first plastic package body and the second plastic package body are made of the same material, and the first plastic package body at least covers one side surface of the first wiring combination layer so as to support the first wiring combination layer.
In an alternative embodiment, the semiconductor package structure further includes a conductive pillar and a second wiring combination layer, the conductive pillar is disposed on the first wiring combination layer and is spaced from the first chip, and the conductive pillar is electrically connected to the first wiring combination layer; the second plastic package body is coated outside the conductive column, and one end of the conductive column, which is far away from the first plastic package body, is exposed out of the second plastic package body; the second wiring combination layer is arranged on the second plastic package body and is electrically connected with the first wiring combination layer through the conductive column, and one side, far away from the first wiring combination layer, of the second wiring combination layer is provided with a solder ball.
In an alternative embodiment, the first wiring combination layer includes a first dielectric layer, a first wiring layer, a second dielectric layer, a second wiring layer, a third dielectric layer and a first conductive layer, where the first dielectric layer is disposed on the surface of the first plastic package body, the first wiring layer is disposed in the first dielectric layer, the second dielectric layer is disposed on the surface of the first dielectric layer, the second wiring layer is disposed in the second dielectric layer and electrically connected with the first wiring layer, the third dielectric layer is disposed on the surface of the second dielectric layer, and the first conductive layer is disposed in the third dielectric layer and is exposed on the third dielectric layer, and the first conductive layer is electrically connected with the second wiring layer.
In an alternative embodiment, the conductive pillars are disposed on the third dielectric layer and electrically connected to the first conductive layer.
In an optional embodiment, the conductive pillar is disposed on the first dielectric layer and electrically connected to the first wiring layer, and the second dielectric layer and the third dielectric layer are wrapped on an end portion of the conductive pillar, which is close to the first plastic package body.
In an alternative embodiment, the first plastic package body is formed with a receiving groove, and the first wiring combination layer, the conductive post, the first chip and the second plastic package body are all received in the receiving groove.
In an optional embodiment, the first plastic package body includes a barrier base layer and a coating sidewall, the coating sidewall is disposed at an edge of the barrier base layer and forms the accommodating groove, the first wiring combination layer is disposed on a surface of the barrier base layer, and the coating sidewall is coated on the first wiring combination layer and the sidewall of the second plastic package body.
In an alternative embodiment, an end of the cladding sidewall far away from the barrier base layer is flush with a surface of a side of the second plastic package body far away from the barrier base layer.
In an alternative embodiment, the semiconductor package structure further includes a second chip, where the second chip is disposed on a surface of the first plastic package body, which is far away from the second plastic package body, and is electrically connected to the first wiring combination layer.
In an alternative embodiment, a base conductive layer is disposed in the first plastic package body, the base conductive layer penetrates through two side surfaces of the first plastic package body, the first wiring combination layer, and the second chip is electrically connected with the base conductive layer.
In a second aspect, the present invention provides a method for manufacturing a semiconductor package structure, for manufacturing a semiconductor package structure according to the foregoing embodiment, the method comprising:
Preparing a first plastic package body;
forming a first wiring combination layer on the surface of the first plastic package body;
attaching a first chip to the surface of the first wiring combination layer;
forming a second plastic package body on the surface of the first wiring combination layer, wherein the second plastic package body is coated outside the first chip;
The first plastic package body and the second plastic package body are made of the same material, and the first plastic package body at least covers one side surface of the first wiring combination layer so as to support the first wiring combination layer.
In an alternative embodiment, before the step of surface mounting the first chip on the surface of the first wiring combination layer, the manufacturing method includes:
arranging a conductive column on the first wiring combination layer;
the second plastic package body is coated outside the conductive column, and one end of the conductive column, which is far away from the first plastic package body, is exposed out of the second plastic package body.
In an alternative embodiment, after the step of forming the second plastic package on the surface of the first wiring combination layer, the manufacturing method further includes:
forming a second wiring combination layer on the surface of the second plastic package body;
wherein the second wiring combination layer is electrically connected with the first wiring combination layer through the conductive post.
The beneficial effects of the embodiment of the invention include, for example:
According to the semiconductor packaging structure and the preparation method thereof, the first wiring combination layer is arranged on the first plastic packaging body, the first chip is mounted on the first wiring combination layer in a pasting mode, and then the second plastic packaging body is arranged on the first wiring combination layer to cover the first chip, wherein materials of the first plastic packaging body and the second plastic packaging body are the same, and the first plastic packaging body at least covers one side surface of the first wiring layer, so that the first wiring combination layer can be supported. Compared with the prior art, the embodiment of the invention uses the first plastic package body as the supporting substrate, the first chip is attached after wiring is completed on the surface of the first plastic package body to form the first wiring combination layer, and finally the second plastic package body is used for plastic package. The high-density integrated circuit has high-density interconnection and high reliability, avoids using a carrier wafer, omits a glue film layer, and avoids influencing the wiring conductivity by the residual glue film layer after stripping of a conventional carrier. And when wiring patterning is performed, no adhesive film layer exists, so that detachment can not be caused in the wet process, and the reliability of the wet process is ensured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic view of a first semiconductor package structure according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a soldering structure of a semiconductor package according to an embodiment of the present invention;
fig. 3 is a schematic view of a second semiconductor package structure according to an embodiment of the present invention;
fig. 4a is a schematic diagram of a third semiconductor package structure according to an embodiment of the present invention;
Fig. 4b is a schematic diagram of a fourth semiconductor package structure according to an embodiment of the present invention;
fig. 5 is a schematic view of a fifth semiconductor package structure according to an embodiment of the present invention;
Fig. 6 is a schematic diagram of a sixth semiconductor package structure according to an embodiment of the present invention;
fig. 7 to 13 are process flow diagrams of a method for manufacturing a semiconductor package according to an embodiment of the present invention.
Icon: 100-a semiconductor package structure; 110-a first plastic package body; 111-a receiving groove; 112-a barrier base layer; 113-cladding the side walls; 114-a base conductive layer; 120-a first wiring combination layer; 121-a first dielectric layer; 122-a first wiring layer; 123-a second dielectric layer; 124-a second wiring layer; 125-a third dielectric layer; 126-a first conductive layer; 130-a first chip; 140-a second plastic package body; 150-conductive posts; 160-a second wiring combination layer; 161-fourth dielectric layer; 162-a third wiring layer; 163-a fifth dielectric layer; 164-a fourth wiring layer; 165-sixth dielectric layer; 166-a second conductive layer; 170-solder balls; 180-a second chip.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
As disclosed in the background art, in the existing fan-out wafer level packaging technology, a TSV-Less technology (without through silicon via) is generally adopted to reduce the manufacturing cost, a carrier wafer is used for packaging, a metal layer is electroplated again after a glue film is coated on the carrier wafer, then a wiring layer structure is prepared again, and finally, a bonding and separation operation is performed, and then the metal layer is removed by grinding. The conductive performance of the wiring is easily affected by the residual adhesive film layer after bonding separation. And when wiring patterning is performed, the wet method process is required to be performed for a plurality of times, so that the wet method can easily lead to decomposition of the adhesive film layer due to the influence of chemical agents and exposure, and even lead to detachment of the carrier wafer from the combined adhesive film layer.
In order to solve the above-mentioned problems, the embodiments of the present invention provide a novel semiconductor package structure and a method for manufacturing the same, and it should be noted that features in the embodiments of the present invention may be combined with each other without collision.
Referring to fig. 1, the embodiment of the invention provides a semiconductor package structure 100, which can use a plastic package body as a supporting substrate, has high density integration, high density interconnection and high reliability, and meanwhile, omits a glue film layer, and avoids the influence of the residual glue film layer after stripping of a conventional carrier on wiring conductivity. And the wet process can not lead to detachment when the wiring patterning is performed, so that the reliability of the wet process is ensured.
The semiconductor package structure 100 provided by the embodiment of the invention comprises a first plastic package body 110, a first wiring combination layer 120, a first chip 130, a second plastic package body 140, a conductive post 150 and a second wiring combination layer 160, wherein the first wiring combination layer 120 is arranged on the first plastic package body 110; the first chip 130 is mounted on the first wiring combination layer 120; the second plastic package body 140 is disposed on the first wiring combination layer 120 and is coated outside the first chip 130; the materials of the first plastic package body 110 and the second plastic package body 140 are the same, and the first plastic package body 110 at least covers one side surface of the first wiring combination layer 120 to support the first wiring combination layer 120. The conductive pillars 150 are disposed on the first wiring combination layer 120 and spaced apart from the first chip 130, and the conductive pillars 150 are electrically connected to the first wiring combination layer 120; the second plastic package body 140 is wrapped outside the conductive column 150, and one end of the conductive column 150, which is far away from the first plastic package body 110, is exposed out of the second plastic package body 140; the second wiring combination layer 160 is disposed on the second plastic package 140 and is electrically connected to the first wiring combination layer 120 through the conductive posts 150. And a side of the second wiring combination layer 160 remote from the first wiring combination layer 120 is provided with solder balls 170.
It should be noted that, the thickness of the first plastic package body 110 may be greater than 20 μm, and the plastic package material of the first plastic package body 110 may be made by adding a high thermal conductive material including, but not limited to, alumina thermal conductive powder or nano alumina to epoxy-based resin (epoxy-based resin) or silicon-based resin (silicone-based resin), and adding silica micropowder, so as to achieve the high thermal conductive performance of the first plastic package body 110. Specifically, the first molding compound 110 may be manufactured by pressure injection molding or liquid printing. In practice, the side with the solder balls 170 may be soldered to the substrate, as shown in fig. 2, and at the same time, after the upper board, the first plastic package 110 has a higher insulation property, so that the surface static electricity of the first wiring combination layer 120 is prevented from being gathered, and thus the static breakdown is prevented from affecting the conductive property.
It should be noted that, in the embodiment of the present invention, the first plastic package body 110 is used as a supporting substrate, the first chip 130 is attached after the wiring is completed on the surface of the first plastic package body 110 to form the first wiring combination layer 120, and finally the second plastic package body 140 is used for plastic packaging. The high-density integrated circuit has high-density interconnection and high reliability, avoids using a carrier wafer, omits a glue film layer, and avoids influencing the wiring conductivity by the residual glue film layer after stripping of a conventional carrier. And when wiring patterning is performed, no adhesive film layer exists, so that detachment can not be caused in the wet process, and the reliability of the wet process is ensured. In addition, by providing the conductive pillars 150, electrical contact between the first wiring combination layer 120 and the second wiring combination layer 160 can be realized, high-density integration and high-density interconnectivity can be realized, and the problem that the conventional process needs to perform back wiring again after bonding release is avoided, so that the process flow of the wiring layers is improved, and the bonding release process is simplified. And the arrangement of the conductive column 150 further improves the heat transfer efficiency and the overall heat dissipation efficiency.
In some embodiments, the first wiring assembly layer 120 includes a first dielectric layer 121, a first wiring layer 122, a second dielectric layer 123, a second wiring layer 124, a third dielectric layer 125, and a first conductive layer 126, the first dielectric layer 121 is disposed on a surface of the first molding body 110, the first wiring layer 122 is disposed in the first dielectric layer 121, the second dielectric layer 123 is disposed on a surface of the first dielectric layer 121, the second wiring layer 124 is disposed in the second dielectric layer 123 and electrically connected with the first wiring layer 122, the third dielectric layer 125 is disposed on a surface of the second dielectric layer 123, the first conductive layer 126 is disposed in the third dielectric layer 125 and is exposed to the third dielectric layer 125, and the first conductive layer 126 is electrically connected with the second wiring layer 124.
When actually preparing the first wiring combination layer 120, the first dielectric layer 121 may be formed by a spin coating process, then a photomask is covered on the first dielectric layer 121, an opening of a pattern layer is formed by an exposure and development process, then the first wiring layer 122 is formed by an electroplating process, then the second dielectric layer 123 and the second wiring layer 124 are formed by the same process, and finally the third dielectric layer 125 and the first conductive layer 126 are formed, specifically, the first conductive layer 126 may form a micro bump pad structure and protrude out of the third dielectric layer 125 during preparation, so as to facilitate subsequent chip mounting and preparation of the conductive pillars 150. In the exposure and development process, a wet process is generally required, and the bottom layer is the first plastic package 110 when the first dielectric layer 121 is opened, which can be used as a barrier layer, so that the problem that the carrier is easy to separate from the adhesive layer in the conventional process is solved due to the chemical agent and the decomposition of the adhesive layer when the first dielectric layer 121 is exposed to light.
It should be noted that, the first dielectric layer 121, the second dielectric layer 123, and the third dielectric layer 125 may be made of a dielectric material, such as silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, or the like, and at least one of spin coating, spray coating, printing, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. The first wiring layer 122, the second wiring layer 124, and the first conductive layer 126 may be formed using at least one of Ti, wu, ni, sn, ag, and the manufacturing method may be formed using at least one of sputtering, electroplating, electroless plating, physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), metal Organic Chemical Vapor Deposition (MOCVD), atomic Layer Deposition (ALD), low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), and the like.
In some embodiments, the second wiring combination layer 160 includes a fourth dielectric layer 161, a third wiring layer 162, a fifth dielectric layer 163, a fourth wiring layer 164, a sixth dielectric layer 165, and a second conductive layer 166, the fourth dielectric layer 161 is disposed on the surface of the second molding body 140, the third wiring layer 162 is disposed in the fourth dielectric layer 161 and electrically connected with the conductive pillars 150, the fifth dielectric layer 163 is disposed on the surface of the fourth dielectric layer 161, the fourth wiring layer 164 is disposed in the fifth dielectric layer 163 and electrically connected with the third wiring layer 162, the sixth dielectric layer 165 is disposed on the surface of the fifth dielectric layer 163, the second conductive layer 166 is disposed in the sixth dielectric layer 165 and exposed to the sixth dielectric layer 165, and the second conductive layer 166 is electrically connected with the fourth wiring layer 164 and is formed with solder balls 170. The preparation process and the material of the second wiring combination layer 160 may refer to the first wiring combination layer 120.
In some embodiments, conductive pillars 150 are disposed on third dielectric layer 125 and are electrically connected to first conductive layer 126. Specifically, the conductive pillars 150 may be formed after the preparation of the first dielectric layer 121, the second dielectric layer 123, the third dielectric layer 125, the first wiring layer 122, the second wiring layer 124, and the first conductive layer 126 is completed. Alternatively, the conductive pillars 150 may be directly formed by electroplating a metal layer from the micro bump pads formed by the first conductive layer 126, that is, the conductive pillars 150 may be formed by an electroplating process, and the conductive pillars 150 may be made of at least one of Ti, wu, and Cu. And the height of the conductive pillars 150 with respect to the third dielectric layer 125 may be greater than or equal to 100 μm.
Referring to fig. 3, in some embodiments, the conductive pillars 150 are disposed on the first dielectric layer 121 and electrically connected to the first wiring layer 122, and the second dielectric layer 123 and the third dielectric layer 125 are coated on the ends of the conductive pillars 150 near the first plastic package 110. Specifically, the conductive pillars 150 may be formed during the process of preparing the first wiring layer 120, alternatively, after the first wiring layer 122 is prepared, a metal layer may be electroplated on the first wiring layer 122 to form the conductive pillars 150, and then the second dielectric layer 123 and the second wiring layer 124 are prepared, where the second wiring layer 124 needs to be staggered with the conductive pillars 150. After the preparation of the first wiring combination layer 120 is completed, the second dielectric layer 123 and the third dielectric layer 125 are coated at the bottom end of the conductive column 150, so that an undercut phenomenon at the bottom of the conductive column 150 can be avoided, layering and leakage current phenomena at the bottom of the conductive column 150 are avoided, the insulating performance is improved, and the conductive column 150 can be effectively protected.
It should be noted that, after the preparation of the solder balls 170 on the second wiring combination layer 160 is completed, since the first chip 130 and the solder balls 170 are not on the same side and are separated by the second plastic package 140, the heat dissipation efficiency of the surface of the first chip 130 can be improved, the heat dissipation performance can be improved, and the arrangement of the second plastic package 140 can further improve the overall insulation performance, so as to prevent the dielectric material from being concentrated by external static electricity and causing the circuit layer of the first chip 130 to be impacted.
Referring to fig. 4a, in some embodiments, a receiving groove 111 is formed on the first plastic package body 110, and the first wiring combination layer 120, the conductive post 150, the first chip 130, and the second plastic package body 140 are all received in the receiving groove 111. Specifically, the accommodating groove 111 may be formed by directly preparing the accommodating groove 111 with a mold or by grooving the accommodating groove 110 with a laser, then preparing the first wiring combination layer 120, the conductive post 150, the first chip 130 and the second plastic package 140, namely, completing the mounting of the first chip 130 after preparing the multi-layer dielectric layer, the wiring layer and the conductive post 150 in the accommodating groove 111, and finally performing plastic packaging to form the second plastic package 140.
In some embodiments, the first plastic package 110 includes a barrier base layer 112 and a coating sidewall 113, the coating sidewall 113 is disposed at an edge of the barrier base layer 112 and forms the accommodating groove 111, the first wiring assembly layer 120 is disposed on a surface of the barrier base layer 112, and the coating sidewall 113 is coated on sidewalls of the first wiring assembly layer 120 and the second plastic package 140. Specifically, the barrier base layer 112 and the coating side wall 113 are integrally arranged, and the coating side wall 113 can be bonded and coated on the side walls of the first wiring combination layer 120 and the second plastic package body 140, so that side protection is realized, layering of multiple wiring layers is avoided, entry of moisture or humidity from the side wall in the preparation process of the multiple dielectric layers is avoided, and layering of the dielectric layers is further avoided. Moreover, as the containing grooves 111 are multiple, connecting rib structures are formed between the adjacent containing grooves 111 in the actual preparation process, the connecting rib structure can serve as a stress buffer structure, warping is further avoided, meanwhile, the connecting rib structures only need to be cut in the subsequent cutting process, and the phenomenon of wiring pulling caused by cutting the first wiring combination layer 120 in the subsequent cutting process is avoided.
In some embodiments, an end of the cladding sidewall 113 away from the barrier base layer 112 is flush with a side surface of the second molding body 140 away from the barrier base layer 112. Specifically, the depth of the accommodating groove is the sum of the thicknesses of the first wiring combination layer 120 and the second plastic package body 140, so that the second plastic package body 140 and the first plastic package body 110 can be flush, thereby realizing planarization, and facilitating the subsequent preparation of the second wiring combination layer 160. Of course, in other preferred embodiments, the end of the cladding sidewall 113 away from the barrier base layer 112 may be higher than the second molding body 140, so that the second wiring combination layer 160 can be accommodated in the accommodating groove 111.
In some embodiments, referring to fig. 4b, the first plastic package body 110 includes a coating sidewall 113, the coating sidewall 113 encloses to form the accommodating groove 111, and is coated on the sidewalls of the first wiring assembly layer 120 and the second plastic package body 140, so that a side of the first wiring assembly layer 120 away from the second plastic package body 140 is exposed to the coating sidewall 113. Specifically, when the first plastic package body 110 is manufactured, the surface of the first plastic package body 110 may be grooved to form the accommodating groove 111, and the accommodating groove does not penetrate through the first plastic package body 110, and after the first wiring combination layer 120 is formed on one side surface of the first plastic package body 110, the other side surface of the first plastic package body 110 may be ground, so that the coated side wall 113 only having the side wall is formed. In other preferred embodiments of the present invention, since the first wiring combination layer 120 is exposed out of the cladding sidewall 113, the surface of the first wiring combination layer 120 may be additionally provided with a wiring structure again, and the chips are attached, so that the number of packaged chips is increased, and the integration level of chip package is greatly improved.
Referring to fig. 5, in some embodiments, the semiconductor package structure 100 further includes a second chip 180, and the second chip 180 is disposed on a surface of the first plastic package body 110 away from the second plastic package body 140 and is electrically connected to the first wiring combination layer 120. Specifically, the first plastic package body 110 is provided with a base conductive layer 114, the base conductive layer 114 penetrates through two side surfaces of the first plastic package body 110, the first wiring combination layer 120, and the second chip 180 is electrically connected with the base conductive layer 114. By providing the second chip 180, the number of chips can be increased, thereby increasing the package integration level. The base conductive layer 114 may be in the shape of a cylinder, a rectangular column, or a polygonal column. Here, the grooves may be formed by laser grooving on the first plastic package body 110, and then the base conductive layer 114 is formed by using an electroplating process, where the position of the base conductive layer 114 corresponds to the position of the micro bump on the second chip 180, and simultaneously corresponds to the position of the first wiring layer 122. Compared with the direct mounting of the second chip 180, the arrangement of the base conductive layer 114 can avoid the undercut phenomenon caused by the direct soldering of the first wiring layer 122 of the metal structure and the micro bump. Meanwhile, the first chip 130 and the second chip 180 are mounted in opposite directions, that is, the first chip 130 and the second chip 180 are mounted face to face, which can cause the voltage at the first wiring combination layer 120 to rise, and for this, the arrangement of the first plastic package body 110 can also promote the insulation performance, so that the wiring layer is prevented from being broken down due to electrostatic influence, and meanwhile, the internal wiring layer is also prevented from being influenced by moisture. In addition, in the present embodiment, the distance between the first chip 130 and the second wiring combination layer 160 is H, so that the first chip 130 is not contacted with the second wiring combination layer 160 at the bottom, thereby greatly improving the heat dissipation performance and reducing the warpage problem caused by thermal shock of the wiring layer.
Referring to fig. 6, in some embodiments, the semiconductor package structure 100 includes a first plastic package body 110, a first wiring combination layer 120, a first chip 130, and a second plastic package body 140, the first wiring combination layer 120 being disposed on the first plastic package body 110; the first chip 130 is mounted on the first wiring combination layer 120; the second plastic package body 140 is disposed on the first wiring combination layer 120 and is coated outside the first chip 130; the materials of the first plastic package body 110 and the second plastic package body 140 are the same, and the first plastic package body 110 at least covers one side surface of the first wiring combination layer 120 to support the first wiring combination layer 120. The first plastic package body 110 is internally provided with a substrate conductive layer 114, the substrate conductive layer 114 penetrates through the surfaces of two sides of the first plastic package body 110, the first wiring combination layer 120 is electrically connected with the substrate conductive layer 114, one side, far away from the first wiring combination layer 120, of the substrate conductive layer 114 is also provided with a solder ball 170, and the solder ball 170 is electrically connected with the first wiring combination layer 120 through the substrate conductive layer 114. In addition, the first plastic package 110 is adopted in the embodiment, so that the insulation property of the first plastic package can be improved, and after the upper plate is arranged, the substrate voltage can be prevented from breaking through the first plastic package 110 to influence the conductive property of the wiring layer. In addition, the first plastic package 110 can also avoid static electricity accumulation, and further prevent static breakdown.
The embodiment of the present invention further provides a method for preparing the semiconductor package 100, which is used for preparing the semiconductor package 100, and the method for preparing the semiconductor package 100 includes the following steps:
S1: the first molding body 110 is prepared.
Referring to fig. 7, specifically, a plastic packaging process may be first used to make a substrate structure by using a plastic packaging material, where the plastic packaging material may be made by adding a high thermal conductive material to epoxy-based resin (epoxy-based resin) or silicon-based resin (silicone-based resin) and adding a filler such as silica micropowder, where the high thermal conductive material includes, but is not limited to, alumina thermal conductive powder or nano alumina, so as to achieve high thermal conductive performance of the plastic packaging material. Alternatively, the thickness of the plastic package may be 50 μm to 1000 μm.
In other preferred embodiments of the present invention, if the package structure shown in fig. 4a or fig. 4b is prepared, a receiving groove is further formed on the surface of the first plastic package body 110 by grooving, as shown in fig. 8, and then the subsequent process is completed in the receiving groove.
S2: a first wiring assembly layer 120 is formed on the surface of the first plastic package 110.
Referring to fig. 9 and 10, specifically, after the preparation of the first molding body 110 is completed, a dielectric material may be coated on the surface of the first molding body 110 by using a spin coating process to form a first dielectric layer 121, the dielectric material may be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, or the like, then a photomask is covered on the dielectric layer again, a pattern layer opening layer is formed by using an exposure and development process, an electroplating process is again used to form an electroplated metal layer on the pattern layer opening thereof to form a first wiring layer 122, then a spin coating process is again used to coat a dielectric material on the surface of the first dielectric layer 121 to form a second dielectric layer 123, the post-opening electroplating is performed to form a second wiring layer 124, and the preparation of the third dielectric layer 125 and the first conductive layer 126 may repeat the previous processes. The first dielectric layer 121, the second dielectric layer 123, and the third dielectric layer 125 may be formed by any one of spraying, printing, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. While the first wiring layer 122, the second wiring layer 124, and the first conductive layer 126 may also be formed by any one of sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD.
It should be noted that, the first conductive layer 126 may form a micro bump pad structure during the preparation process and protrude from the third dielectric layer 125, so as to facilitate the subsequent chip mounting and the preparation of the conductive pillars 150. In the exposure and development process, a wet process is generally required, and the bottom layer is the first plastic package 110 when the first dielectric layer 121 is opened, which can be used as a barrier layer, so that the problem that the carrier is easy to separate from the adhesive layer in the conventional process is solved due to the chemical agent and the decomposition of the adhesive layer when the first dielectric layer 121 is exposed to light. It should be further noted that, in some embodiments, after the first wiring combination layer 120 is completed, at least part of the first plastic package body 110 may be removed by using a polishing technique, as shown in fig. 5, the bottom may be removed, so as to retain the coated sidewall 113 of the sidewall, or the first plastic package body 110 may be directly polished to be removed.
S3: a conductive pillar 150 is disposed on the first wiring combination layer 120.
With continued reference to fig. 10, specifically, the conductive pillars 150 are electrically connected to the first wiring combination layer 120, and the conductive pillars 150 may be formed by directly electroplating on the micro bump pads formed by the first conductive layer 126, and the conductive pillars 150 may be made of at least one of Ti, wu, and Cu. And the height of the conductive pillars 150 with respect to the third dielectric layer 125 may be greater than or equal to 100 μm.
S4: the first chip 130 is mounted on the surface of the first wiring layer 120.
Specifically, referring to fig. 11, a first chip 130 is mounted on the micro bump pad formed by the first conductive layer 126 using a flip chip mounting process, and then soldered by a reflow soldering process, where an underfill process may be optionally used to form an underfill to protect the solder structure.
S5: a second molding body 140 is formed on the surface of the first wiring combination layer 120.
Referring to fig. 12, specifically, the second plastic package body 140 is coated outside the first chip 130, after the mounting of the first chip 130 is completed, the second plastic package body 140 may be formed on the surface of the first wiring combination layer 120 by using a plastic package process, and then the second plastic package body 140 and the conductive column 150 are polished to be flush by using a polishing process, so that the top surface of the conductive column 150 is exposed, so that the second plastic package body 140 is coated outside the conductive column 150, and one end of the conductive column 150 far away from the first plastic package body 110 is exposed to the second plastic package body 140. The materials of the first plastic package body 110 and the second plastic package body 140 are the same, and the first plastic package body 110 at least covers one side surface of the first wiring combination layer 120 to support the first wiring combination layer 120.
S6: a second wiring combination layer 160 is formed on the surface of the second molding body 140.
Referring to fig. 13, in particular, the second wiring combination layer 160 is electrically connected to the first wiring combination layer 120 through the conductive posts 150, and the manufacturing process and materials of the second wiring combination layer 160 may refer to the first wiring combination layer 120. After the second wiring combination layer 160 is formed, solder balls 170 may be formed on the surface of the second conductive layer 166 through a ball mounting process.
After the preparation of the second wiring combination layer 160 and the solder balls 170 is completed, the second wiring combination layer 160, the second molding body 140, and the first wiring combination layer 120 may be cut along the dicing streets, thereby forming a single product.
In summary, in the semiconductor package structure 100 and the method for manufacturing the same provided in the present embodiment, the first wiring assembly layer 120 is disposed on the first plastic package body 110, the first chip 130 is attached to the first wiring assembly layer 120, and then the second plastic package body 140 is disposed on the first wiring assembly layer 120 to encapsulate the first chip 130, where the materials of the first plastic package body 110 and the second plastic package body 140 are the same, and the first plastic package body 110 covers at least one side surface of the first wiring assembly layer 122, so as to support the first wiring assembly layer 120. Compared with the prior art, the embodiment of the invention uses the first plastic package body 110 as the supporting substrate, completes the wiring on the surface of the first plastic package body 110 to form the first wiring combination layer 120, then attaches the first chip 130, and finally performs the plastic package through the second plastic package body 140. The high-density integrated circuit has high-density interconnection and high reliability, avoids using a carrier wafer, omits a glue film layer, and avoids influencing the wiring conductivity by the residual glue film layer after stripping of a conventional carrier. And when wiring patterning is performed, no adhesive film layer exists, so that detachment can not be caused in the wet process, and the reliability of the wet process is ensured.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (14)
1. A semiconductor package structure, comprising:
A first plastic package body;
The first wiring combination layer is arranged on the first plastic package body;
a first chip mounted on the first wiring combination layer;
the second plastic package body is arranged on the first wiring combination layer and is coated outside the first chip;
The first plastic package body and the second plastic package body are made of the same material, and the first plastic package body at least covers one side surface of the first wiring combination layer so as to support the first wiring combination layer.
2. The semiconductor package according to claim 1, further comprising a conductive pillar and a second wiring combination layer, the conductive pillar being disposed on the first wiring combination layer and spaced apart from the first chip, and the conductive pillar being electrically connected to the first wiring combination layer; the second plastic package body is coated outside the conductive column, and one end of the conductive column, which is far away from the first plastic package body, is exposed out of the second plastic package body; the second wiring combination layer is arranged on the second plastic package body and is electrically connected with the first wiring combination layer through the conductive column, and one side, far away from the first wiring combination layer, of the second wiring combination layer is provided with a solder ball.
3. The semiconductor package according to claim 2, wherein the first wiring combination layer includes a first dielectric layer, a first wiring layer, a second dielectric layer, a second wiring layer, a third dielectric layer, and a first conductive layer, the first dielectric layer is disposed on a surface of the first molding body, the first wiring layer is disposed in the first dielectric layer, the second dielectric layer is disposed on a surface of the first dielectric layer, the second wiring layer is disposed in the second dielectric layer and electrically connected to the first wiring layer, the third dielectric layer is disposed on a surface of the second dielectric layer, the first conductive layer is disposed in the third dielectric layer and exposed to the third dielectric layer, and the first conductive layer is electrically connected to the second wiring layer.
4. The semiconductor package according to claim 3, wherein the conductive pillars are disposed on the third dielectric layer and electrically connected to the first conductive layer.
5. The semiconductor package according to claim 3, wherein the conductive pillar is disposed on the first dielectric layer and electrically connected to the first wiring layer, and the second dielectric layer and the third dielectric layer are wrapped on an end portion of the conductive pillar, which is close to the first plastic package body.
6. The semiconductor package according to claim 2, wherein the first molding compound has a receiving groove formed therein, and the first wiring assembly layer, the conductive pillars, the first chip, and the second molding compound are all received in the receiving groove.
7. The semiconductor package according to claim 6, wherein the first plastic package includes a barrier base layer and a cladding sidewall, the cladding sidewall is disposed at an edge of the barrier base layer and forms the accommodating groove, the first wiring combination layer is disposed on a surface of the barrier base layer, and the cladding sidewall is clad on sidewalls of the first wiring combination layer and the second plastic package.
8. The semiconductor package according to claim 7, wherein an end of the cladding sidewall away from the barrier base layer is flush with a surface of the second molding body away from the barrier base layer.
9. The semiconductor package according to claim 1, further comprising a second chip disposed on a side surface of the first plastic package body remote from the second plastic package body and electrically connected to the first wiring assembly layer.
10. The semiconductor package according to claim 9, wherein a base conductive layer is disposed in the first plastic package, the base conductive layer penetrates through two side surfaces of the first plastic package, the first wiring combination layer is electrically connected to the base conductive layer, and the second chip is electrically connected to the base conductive layer.
11. The semiconductor package according to claim 1, wherein a base conductive layer is disposed in the first plastic package body, the base conductive layer penetrates through two side surfaces of the first plastic package body, the first wiring combination layer is electrically connected with the base conductive layer, a solder ball is further disposed on a side, away from the first wiring combination layer, of the base conductive layer, and the solder ball is electrically connected with the first wiring combination layer through the base conductive layer.
12. A method for manufacturing a semiconductor package structure according to claim 1, characterized in that the method comprises:
Preparing a first plastic package body;
forming a first wiring combination layer on the surface of the first plastic package body;
attaching a first chip to the surface of the first wiring combination layer;
forming a second plastic package body on the surface of the first wiring combination layer, wherein the second plastic package body is coated outside the first chip;
The first plastic package body and the second plastic package body are made of the same material, and the first plastic package body at least covers one side surface of the first wiring combination layer so as to support the first wiring combination layer.
13. The method of manufacturing a semiconductor package according to claim 12, wherein before the step of surface mounting the first chip on the first wiring combination layer, the method of manufacturing includes:
arranging a conductive column on the first wiring combination layer;
the second plastic package body is coated outside the conductive column, and one end of the conductive column, which is far away from the first plastic package body, is exposed out of the second plastic package body.
14. The method of manufacturing a semiconductor package according to claim 13, wherein after the step of forming the second molding body on the surface of the first wiring combination layer, the method further comprises:
forming a second wiring combination layer on the surface of the second plastic package body;
wherein the second wiring combination layer is electrically connected with the first wiring combination layer through the conductive post.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410494155.9A CN118099107B (en) | 2024-04-24 | 2024-04-24 | Semiconductor packaging structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410494155.9A CN118099107B (en) | 2024-04-24 | 2024-04-24 | Semiconductor packaging structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118099107A CN118099107A (en) | 2024-05-28 |
| CN118099107B true CN118099107B (en) | 2024-08-23 |
Family
ID=91160201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410494155.9A Active CN118099107B (en) | 2024-04-24 | 2024-04-24 | Semiconductor packaging structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118099107B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107342264A (en) * | 2017-07-21 | 2017-11-10 | 华进半导体封装先导技术研发中心有限公司 | Fan-out package structure and its manufacture method |
| CN113809029A (en) * | 2021-10-12 | 2021-12-17 | 长电集成电路(绍兴)有限公司 | Embedded three-dimensional stacked wafer-level fan-out packaging structure and manufacturing method thereof |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8642385B2 (en) * | 2011-08-09 | 2014-02-04 | Alpha & Omega Semiconductor, Inc. | Wafer level package structure and the fabrication method thereof |
| US11177142B2 (en) * | 2017-11-30 | 2021-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for dicing integrated fan-out packages without seal rings |
| US12125775B2 (en) * | 2020-11-11 | 2024-10-22 | Nepes Co., Ltd. | Semiconductor package and method for manufacturing the same |
| CN117546288A (en) * | 2021-10-29 | 2024-02-09 | 华为技术有限公司 | Fan-out chip packaging structure and preparation method |
| CN114512464B (en) * | 2022-04-19 | 2022-08-02 | 甬矽半导体(宁波)有限公司 | Fan-out type packaging structure and preparation method thereof |
| CN114649286B (en) * | 2022-05-19 | 2022-09-27 | 甬矽电子(宁波)股份有限公司 | Fan-out type packaging structure and fan-out type packaging method |
| CN116031168A (en) * | 2022-12-28 | 2023-04-28 | 成都复锦功率半导体技术发展有限公司 | Chip packaging structure and preparation method thereof |
-
2024
- 2024-04-24 CN CN202410494155.9A patent/CN118099107B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107342264A (en) * | 2017-07-21 | 2017-11-10 | 华进半导体封装先导技术研发中心有限公司 | Fan-out package structure and its manufacture method |
| CN113809029A (en) * | 2021-10-12 | 2021-12-17 | 长电集成电路(绍兴)有限公司 | Embedded three-dimensional stacked wafer-level fan-out packaging structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118099107A (en) | 2024-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN210006732U (en) | Chip packaging structure | |
| US9947625B2 (en) | Wiring board with embedded component and integrated stiffener and method of making the same | |
| US10177130B2 (en) | Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener | |
| US9147667B2 (en) | Semiconductor device with face-to-face chips on interposer and method of manufacturing the same | |
| US9230901B2 (en) | Semiconductor device having chip embedded in heat spreader and electrically connected to interposer and method of manufacturing the same | |
| US7413925B2 (en) | Method for fabricating semiconductor package | |
| US9142502B2 (en) | Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits | |
| US20090014876A1 (en) | Wafer level stacked package having via contact in encapsulation portion and manufacturing method thereof | |
| KR101532816B1 (en) | Semiconductor packages and methods of packaging semiconductor devices | |
| US20150115433A1 (en) | Semiconducor device and method of manufacturing the same | |
| US20090072357A1 (en) | Integrated shielding process for precision high density module packaging | |
| TWI861669B (en) | Integrated circuit package and method of forming same | |
| KR20050037430A (en) | Semiconductor package device and method of formation and testing | |
| KR20010018694A (en) | Manufacturing method for three demensional stack chip package | |
| TW202127549A (en) | Fanout integration for stacked silicon package assembly | |
| CN114141637A (en) | Fan-out type chip packaging method and fan-out type chip packaging structure | |
| KR101631406B1 (en) | Semiconductor package and manufacturing method thereof | |
| CN114512464B (en) | Fan-out type packaging structure and preparation method thereof | |
| CN118099107B (en) | Semiconductor packaging structure and preparation method thereof | |
| CN113725198A (en) | Semiconductor package | |
| CN116387169B (en) | Packaging method and packaging structure | |
| CN113078148B (en) | Semiconductor packaging structure, method, device and electronic product | |
| US8148206B2 (en) | Package for high power integrated circuits and method for forming | |
| KR102058247B1 (en) | Semiconductor Package of using the Printed Circuit Board | |
| KR102040171B1 (en) | Semiconductor Package of using the Printed Circuit Board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |