CN105679679B - A kind of preparation method of GaN base notched gates MISFET - Google Patents

Abstract

The present invention provides a semiconductor device preparation technology, in particular to a method for preparing a GaN-based groove gate MISFET, comprising the following steps: firstly provide an AlGaN/GaN heterojunction material required for groove preparation, and in the material A layer of dielectric layer is deposited on the surface as a mask layer, and the dielectric layer in the gate area is removed by photolithography and development technology and wet etching to realize the patterning of the mask layer, and the AlGaN in the gate area is removed by using the reverse process of the growth reaction of GaN material To obtain grooves, a thin layer of high-quality AlN is deposited in-situ, and then a gate dielectric layer is prepared to cover the source, drain, and gate electrodes, and finally a groove-gate MISFET with a stacked structure of AlN/gate dielectric layer is formed. The invention has a simple process, can well solve the damage to the gate area caused by traditional dry or wet etching of the groove, and can form a high-quality MIS interface to improve the device performance of the groove gate MISFET, such as reducing the gate Leakage current and on-resistance and improved threshold voltage stability, etc.

Description

A preparation method of GaN-based groove gate MISFET

technical field

The present invention relates to the technical field of semiconductor devices, and more specifically, to a method for preparing a GaN-based groove gate MISFET.

Background technique

Gallium nitride (GaN) material has the advantages of large band gap, high breakdown electric field strength, high electron saturation drift velocity, high thermal conductivity, etc., and is very suitable for making high-power, high-frequency, high-temperature power electronic devices. In the field of power electronics applications, in order to meet the fail-safe requirements, field-effect transistor (FET) devices must achieve normally-off (also known as enhanced) operation, and in some cases the threshold voltage needs to be at least 4-5V. For the conventional AlGaN/GaN heterojunction field effect transistor (HFET), due to the existence of two-dimensional electron gas (2DEG) with high concentration and high mobility at the interface, the device is still in the on state even when the external gate voltage is zero. (normally open device). In order to solve these problems, an insulated gate field effect transistor (MISFET) using MIS structure is an effective technical route.

On the premise of retaining the 2DEG concentration in the access region (without sacrificing the conduction characteristics of the device), the GaN-based recessed gate MISFET device can reduce or even completely eliminate the 2DEG under the gate at zero bias, and can use the MIS structure gate to realize high threshold voltage. However, the conventional groove preparation is to etch the AlGaN barrier layer under the gate using inductively coupled plasma (ICP) or reactive ion etching (RIE) equipment. The use of plasma will cause damage to the crystal lattice in the channel region, thereby affecting the reliability and stability of the MIS interface. In addition, the selective etching ratio of AlGaN and GaN materials is small, so it is difficult to realize the self-stop of etching, and the process repeatability is poor. These two points limit the improvement of the channel mobility of the hybrid MISFET, thereby increasing the on-resistance of the device.

Digital wet etching uses multiple oxidations and chemical solution etching to obtain process-controllable normally-off recessed gate MISFET devices, and can effectively remove plasma damage. However, the edge of the groove is not neat, the gate region has a tapered AlGaN residue, and a large number of etching holes can also be observed on the surface of the GaN channel layer. Using selective area epitaxy to prepare grooves can also remove plasma damage in the gate region and improve the MIS interface characteristics, but the epitaxy process is more complicated. Therefore, it is necessary to seek a selective region growth interface protection method to overcome the shortcomings of the traditional process, so as to obtain higher mobility and threshold voltage. Since the epitaxy of GaN-based materials is realized in a quasi-equilibrium state where the synthesis rate is slightly greater than the decomposition rate, when there is only nitrogen, hydrogen or a mixed gas of nitrogen and hydrogen in the chemical vapor deposition system without a growth source, it can be adjusted by adjusting The growth parameters make the decomposition rate of the GaN-based material slightly higher than the synthesis rate, so that the AlGaN epitaxial layer in the gate region is decomposed layer by layer along the reverse process of the growth reaction with the assistance of the mask to obtain grooves.

Contents of the invention

In order to overcome at least one defect described in the above-mentioned prior art, the present invention provides a method for preparing a GaN-based groove gate MISFET, which can well solve the problem caused by the traditional dry or wet etching of the groove on the gate region. The damage can form a high-quality MIS interface to improve the device performance of the groove gate MISFET.

In order to solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a method for preparing a GaN-based groove gate MISFET, wherein the groove is obtained by removing AlGaN in the gate region by using the reverse process of the GaN material growth reaction, and by Depositing a thin layer of AlN to improve the quality of the MIS interface; specifically includes the following steps:

S1, growing a stress buffer layer on the substrate;

S2, growing a GaN epitaxial layer on the stress buffer layer;

S3, growing an AlGaN barrier layer on the GaN epitaxial layer (3);

S4, depositing a layer of SiO ₂ on the AlGaN barrier layer as a mask layer;

S5, removing the mask layer in the gate area by photolithography and wet etching;

S6, removing the AlGaN barrier layer in the gate region;

S7, growing AlN thin layer in situ;

S8, depositing a gate insulating dielectric layer;

S9, complete device isolation by dry etching, and simultaneously etch out source and drain ohmic contact regions;

S10, evaporating source and drain ohmic contact metals on the source and drain regions;

S11, evaporating gate metal on the gate region on the dielectric layer at the groove.

Specifically, in the step S6, the AlGaN in the gate region is removed by using the reverse process of the GaN material growth reaction to obtain the groove; in the step S7, a thin layer of AlN is deposited in situ to improve the quality of the MIS interface.

The substrate is any one of Si substrate, sapphire substrate, silicon carbide substrate and GaN self-supporting substrate.

The stress buffer layer is any one or combination of AlN, AlGaN, GaN; the thickness of the stress buffer layer is 10 nm-100 μm.

The GaN epitaxial layer is an unintentionally doped GaN epitaxial layer or a doped high-resistance GaN epitaxial layer, and the doping element of the doped high-resistance layer is carbon or iron; the thickness of the GaN epitaxial layer is 100 nm to 100 nm. μm.

The epitaxial layer is an AlGaN barrier layer, the thickness of the AlGaN barrier layer is 5-50 nm, and the concentration of aluminum components can be changed.

The AlGaN barrier layer material can also be one of AlInN, InGaN, AlInGaN, AlN or any combination of several.

A thin AlN layer can also be inserted between the AlGaN barrier layer and the GaN layer, with a thickness of 0-10 nm.

The epitaxial layer is a high-quality AlN layer with a thickness of 0-10 nm; the insulating dielectric layer is Al ₂ O ₃ , HfO ₂ , SiO ₂ or SiN, etc., with a thickness of 1-100 nm; the AlN/dielectric Layer stack structure.

The source and drain materials are Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy; the gate material is Ni/Au alloy, Pt/Al alloy, Pd/Au alloy or TiN/Ti/Au alloy;

The stress buffer layer in step S1, the GaN epitaxial layer in step S2, the AlGaN epitaxial layer in step S3, and the AlN thin layer in step S7 are grown by metal organic chemical vapor deposition or molecular beam epitaxy. Quality film forming method; the growth method of the mask layer in the step S4 is plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition or magnetron sputtering; the groove etching in the step S6 The method is to decompose the AlGaN epitaxial layer layer by layer by using nitrogen gas, hydrogen gas or a mixed gas of nitrogen gas and hydrogen gas in a metal organic chemical vapor deposition system.

Alternatively, the invention may be expressed by means of the method steps described below.

The reverse process of GaN material growth reaction is used to remove the AlGaN in the gate region to obtain grooves, and the quality of the MIS interface is improved by in-situ deposition of a thin layer of AlN. Specifically include the following steps:

1. Provide AlGaN/GaN heterojunction materials that require grooved gate etching;

2. Depositing a dielectric layer on the material to form a mask layer;

3. Using photolithography and developing technology on the mask layer to reveal the gate region;

4. Use a chemical solution to remove the mask material in the gate area, retain the mask material in other areas, and realize the patterning of the mask layer;

5. With the aid of the mask pattern, realize groove etching.

6. With the aid of the mask pattern, a thin layer of AlN is grown in-situ in the groove area.

Further, in the step 1, the substrate is a multi-layer epitaxial layer substrate with different compositions.

In said step 2, the dielectric layer is formed by plasma enhanced chemical vapor deposition or atomic layer deposition or physical vapor deposition or magnetron sputtering. The dielectric layer is SiO ₂ or SiN.

In the step 3, the photoresist is positive or negative photoresist.

In the step 4, the chemical solution used for removing the medium layer is an aqueous solution of hydrofluoric acid or a mixed solution of hydrofluoric acid and ammonium fluoride.

In the step 5, the groove etching is metal organic chemical vapor deposition or molecular beam epitaxy. The reaction gas is H ₂ , N ₂ , or a mixed gas of H ₂ and N ₂ .

In the step 6, the in-situ growth method of the AlN thin layer is metal organic chemical vapor deposition or molecular beam epitaxy.

Compared with the prior art, the beneficial effect is: the present invention provides a method for preparing a GaN-based grooved gate MISFET, since the gate region AlGaN is removed by using the reverse process of the GaN material growth reaction to obtain the groove, which can be well Solve the damage to the gate area caused by conventional dry or wet etching of grooves. The method does not need to use chemical solvents, and can avoid corrosion holes and wet etching residues in the groove gate area. In addition, the quality of the MIS interface and the device performance of the recess gate MISFET can be further improved by forming a high-quality AlN thin layer in situ.

Description of drawings

1-11 are process schematic diagrams of the device manufacturing method in Embodiment 1 of the present invention.

FIG. 12 is a schematic diagram of the device structure of Embodiment 2 of the present invention.

FIG. 13 is a schematic diagram of the device structure of Embodiment 3 of the present invention.

FIG. 14 is a schematic diagram of the device structure of Embodiment 4 of the present invention.

FIG. 15 is a schematic diagram of the device structure of Embodiment 5 of the present invention.

Detailed ways

The accompanying drawings are for illustrative purposes only, and should not be construed as limitations on this patent; in order to better illustrate this embodiment, certain components in the accompanying drawings will be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art It is understandable that some well-known structures and descriptions thereof may be omitted in the drawings. The positional relationship described in the drawings is for illustrative purposes only, and should not be construed as a limitation on this patent.

Example 1

As shown in Figure 11, it is a schematic diagram of the device structure of this embodiment, and its structure includes a substrate 1, a stress buffer layer 2, a GaN epitaxial layer 3, and an AlGaN barrier layer 4 from bottom to top, and grooves are formed by reactive etching. A thin AlN layer 5 is grown, a gate insulating dielectric layer 6 is formed, a source 7 and a drain 8 are formed at both ends, and a gate 9 is deposited on the insulating layer 6 at the groove channel.

The manufacturing method of the device field effect transistor of the above-mentioned GaN-based grooved gate MISFET is shown in Figure 1-Figure 11, including the following steps:

S1, using a metal organic chemical vapor deposition method to grow a layer of stress buffer layer 2 on the Si substrate 1, as shown in Figure 1;

S2. Using a metal organic chemical vapor deposition method to grow a GaN epitaxial layer 3 on the stress buffer layer 2, as shown in FIG. 2 ;

S3. Using a metal organic chemical vapor deposition method, grow an AlGaN barrier layer 4 on the GaN epitaxial layer 3, as shown in FIG. 3 ;

S4. Deposit a layer of SiO ₂ by plasma-enhanced chemical vapor phase as the mask layer 10, as shown in FIG. 4 ;

S5, select area etching by photolithography method, remove the mask layer 10 in the gate area, as shown in Figure 5;

S6, using a metal organic chemical vapor deposition method to form a grooved gate through the reverse process of the GaN material growth reaction, as shown in FIG. 6 ;

S7. Using a metal-organic chemical vapor deposition method to grow a high-quality AlN thin layer 5 in situ, as shown in FIG. 7 ;

S8. Remove the mask layer 10, and form a stacked structure of AlN/Al ₂ O ₃ dielectric layer 6 by using an atomic layer deposition method, as shown in FIG. 8 ;

S9. Use ICP to complete device isolation, and simultaneously etch the source and drain ohmic contact regions, as shown in FIG. 9 ;

S10, Ti/Al/Ni/Au alloy is vapor-deposited on the source and drain regions as the ohmic contact metal of the source 7 and the drain 8, as shown in FIG. 10 ;

S11. Evaporate Ni/Au alloy on the insulating layer in the recessed gate area as the gate 9 metal, as shown in FIG. 11 .

So far, the entire fabrication process of the device is completed. FIG. 11 is a schematic diagram of the device structure of Embodiment 1.

Example 2

Figure 12 is a schematic diagram of the device structure of this embodiment, which differs from that of Embodiment 1 only in that the recessed gate in Embodiment 2 is obtained by epitaxial growth and reverse reactive etching, but there is no in-situ grown high-quality AlN TLC.

Example 3

FIG. 13 is a schematic diagram of the device structure of this embodiment, which differs from the structure of Embodiment 1 only in that in Embodiment 1, the AlGaN barrier layer in the entire gate region is etched away to form grooves. A conductive channel is created between the AlN/dielectric layer and the GaN epitaxial layer. In this embodiment, a certain thickness of the AlGaN barrier layer can be retained by controlling the etching time, and the channel mobility and output current can be improved because the channel has a higher two-dimensional electron gas concentration at the heterojunction interface.

Example 4

Figure 14 is a schematic diagram of the device structure of this embodiment, which differs from the structure of Embodiment 1 and Example 3 only in that in this embodiment, the entire AlGaN barrier layer can be removed by controlling the etching time and the GaN epitaxial layer A certain thickness is overetched. A conductive channel is created between the AlN/dielectric layer and the GaN epitaxial layer.

Example 5

FIG. 15 is a schematic diagram of the device structure of this embodiment, which is different from Embodiment 1 in that Embodiment 1 is a lateral conduction type MISFET, and Embodiment 4 is a vertical conduction type device. Specifically, the GaN epitaxial layer in Example 4 is an n-type doped epitaxial layer, and the substrate material is low-resistance silicon, GaN heavily doped free-standing substrate, and the like.

Example 6

The structural difference between this embodiment and Embodiment 1 is only that in this embodiment, a high-quality SiN thin layer is grown in-situ with a thickness of 0-10 nm after the recessed gate is obtained by epitaxial growth and reverse reactive etching.

In addition, it should be noted that the drawings of the above embodiments are only for illustrative purposes, and thus are not necessarily drawn to scale.

Apparently, the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, rather than limiting the implementation of the present invention. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. All modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the claims of the present invention.

Claims (10)

1. a kind of preparation method of GaN base notched gates MISFET, which is characterized in that utilize the inverse process of GaN material growth response Area of grid AlGaN is removed and obtains groove, and MIS interface qualities are promoted by depositing Al N thin layers in place；It is specific include with Lower step：

S1, in substrate（1）Upper growth stress buffer layer（2）；

S2, GaN epitaxial layer is grown on stress-buffer layer（3）；

S3, in GaN epitaxial layer（3）Upper growth AlGaN potential barrier（4）；

S4, one layer of SiO is deposited in AlGaN potential barrier₂, as mask layer（10）；

S5, the method by photoetching and wet etching remove the mask layer of area of grid（10）；

S6, the AlGaN potential barrier for removing area of grid（4）；

S7, growing AIN thin layer in place（5）；

S8, deposition gate insulator dielectric layer（6）；

S9, dry etching complete device isolation, while etch source electrode and drain ohmic contact region；

S10, the source electrode on source electrode and drain region vapor deposition（7）And drain electrode（8）Metal ohmic contact；

S11, grid is deposited in area of grid on groove dielectric layer（9）Metal.

2. a kind of preparation method of GaN base notched gates MISFET according to claim 1, it is characterised in that：The step In rapid S6, area of grid AlGaN is removed using the inverse process of GaN material growth response and obtains groove；The step S7 In, depositing Al N thin layers in place promote MIS interface qualities.

3. a kind of preparation method of GaN base notched gates MISFET according to claim 1, it is characterised in that：The lining Bottom（1）For any one of Si substrates, Sapphire Substrate, silicon carbide substrates, GaN self-supported substrates.

4. a kind of preparation method of GaN base notched gates MISFET according to claim 1, it is characterised in that：Described should Power buffer layer（2）For any of AlN, AlGaN, GaN or combination；Stress buffer layer thickness is 10 nm ~ 100 μm.

5. a kind of preparation method of GaN base notched gates MISFET according to claim 1, it is characterised in that：The GaN Epitaxial layer（3）For the GaN epitaxial layer of unintentional doping or the high resistant GaN epitaxial layer of doping, the high resistant GaN epitaxial layer of the doping Doped chemical be carbon or iron；GaN epitaxial layer thickness is 100 nm ~ 100 μm.

6. a kind of preparation method of GaN base notched gates MISFET according to claim 1, it is characterised in that：Described AlGaN potential barrier（4）Thickness is 5-50 nm, and aluminium concentration of component alterable.

7. a kind of preparation method of GaN base notched gates MISFET according to claim 1, it is characterised in that：Described AlGaN potential barrier（4）Material can be replaced one kind or arbitrary several combination in AlInN, InGaN, AlInGaN, AlN.

8. a kind of preparation method of GaN base notched gates MISFET according to claim 1, it is characterised in that：Described AlGaN potential barrier（4）AlN thin layers are inserted between GaN layer, thickness is 0-10 nm.

9. a kind of preparation method of GaN base notched gates MISFET according to claim 1, it is characterised in that：The AlN Thin layer（5）Thickness is 0-10 nm；The insulating medium layer（6）For Al₂O₃、HfO₂、SiO₂Or SiN, thickness are 1-100 nm；Shape Into AlN/ dielectric layer stacked structures.

10. a kind of preparation method of GaN base notched gates MISFET according to claim 1, it is characterised in that：The source Pole（7）And drain electrode（8）Material is Ti/Al/Ni/Au alloys, Ti/Al/Ti/Au alloys, Ti/Al/Mo/Au alloys or Ti/Al/ Ti/TiN alloys；Grid（9）Material is Ni/Au alloys, Pt/Al alloys, Pd/Au alloys or TiN/Ti/Au alloys；

Stress-buffer layer in the step S1（2）, GaN epitaxial layer in step S2（3）, AlGaN potential barrier in step S3 （4）And the AlN thin layers in step S7（5）Growing method be Metalorganic Chemical Vapor Deposition or molecular beam epitaxy；Institute State mask layer in step S4（10）Growing method for plasma enhanced chemical vapor deposition method, atomic layer deposition method, physics Vapour deposition process or magnetron sputtering method；The removal area of grid method of the step S6 is in metal organic chemical vapor deposition system Using the mixed gas of nitrogen, hydrogen or nitrogen and hydrogen AlGaN potential barrier is made successively to decompose in system.