CN102709320B - GaN-based MISFET device with vertical conduction and its manufacturing method - Google Patents

Abstract

The invention relates to a longitudinally-conductive GaN (gallium nitride)-substrate MISFET (metal insulated semiconductor field-effect transistor) device which comprises a grid electrode, a source electrode, a drain electrode, an insulation layer, a conductive GaN substrate and an epitaxial layer formed on the conductive GaN substrate. The epitaxial layer sequentially includes a first n-shaped light-doped GaN layer, a secondary growth masking media layer, a non-doped GaN layer and a heterogeneous-media potential barrier layer from bottom to top. A groove channel is formed in the middle of the epitaxial layer, the insulation layer is covered on the surface of the groove channel and the heterogeneous-media potential barrier layer, and the grid electrode is covered on the groove channel on the insulation layer. Source electrode areas are formed at two ends of an etching insulation layer, ohm metals are evaporated in the source electrode areas and form the source electrodes contacting with the heterogeneous-media potential barrier layer, and the drain electrode is disposed on the back of the conductive GaN substrate. In the manufacturing method, the insulated media masking layer is directly used as a current baffle layer, a high-quality low-conduction resistance access area is formed in the grate electrode etching area by the side extension technology, and the longitudinally-conductive GaN MISFET device which is stable is obtained.

Description

GaN-based MISFET device with vertical conduction and its manufacturing method

technical field

The invention relates to the field of semiconductor devices, in particular to a vertically conducting GaN-based MISFET device and a manufacturing method thereof.

Background technique

The third-generation wide-bandgap semiconductor materials represented by GaN have excellent material performance characteristics such as wide bandgap, high breakdown electric field strength, high saturation electron drift velocity, high thermal conductivity, and high concentration of two-dimensional electron gas at the heterogeneous interface. Compared with Si materials, GaN is more suitable for making power electronic devices with high power, high capacity and high switching speed. Compared with traditional Si devices, GaN devices can carry higher power density and have higher energy conversion efficiency, which can reduce the volume and weight of the entire system, thereby reducing system cost.

At present, from the perspective of the device structure realized by GaN heterostructure power electronic devices, it is mainly divided into lateral conduction devices and vertical conduction devices.

Since the substrate materials for initial GaN epitaxial growth are mainly insulating sapphire substrates and high-resistance Si substrates, the current HFET devices are basically lateral conduction devices. The lateral conduction device directly uses the AlGaN/GaN heterojunction 2DEG channel as the device conduction channel, which can achieve fast turn-on, turn-off and low on-resistance under relatively low operating voltage; but in a high-voltage operating environment , due to the relative concentration of the electric field between the gate and the drain, it is especially easy to form an electric field edge effect at the edge of the gate, and the device is easy to break down. By increasing the gate-to-drain distance, a high device breakdown voltage is achieved, but at the same time, the on-resistance of the device is also increased, which reduces the utilization efficiency of the chip. The use of surface passivation technology, electrode field plate technology and other technologies can alleviate the above contradictions to a certain extent, but there is no essential change in the shortcomings of the uneven electric field distribution of lateral structure devices that limit the withstand voltage characteristics of devices.

In order to realize the operation of GaN-based electronic devices under high voltage conditions, vertical conduction devices are an ideal technical solution. As for vertical conduction devices, in recent years, with the development of GaN homogeneous substrates, GaN heterostructure vertical vertical conduction devices have also been reported one after another.

The vertical conduction power electronic device structure is actually the structure commonly used in Si material high-voltage MOS devices at present. In the vertical conduction Si power device, the N-type doped layer forming the source and drain is separated by a P-type doped layer. Open, the source, gate and drain are respectively located on the upper and lower poles of the device, and the PN junction between the drain and the gate can withstand high operating voltage. When the positive voltage is applied to the gate, and the contact surface between the insulating gate and the P-type layer forms an electron inversion layer, the device is turned on. Compared with the above-mentioned planar structure device, the advantage of this device structure is that the device current is distributed vertically in the device, the electric field distribution is more uniform, and the breakdown voltage of the device is effectively improved.

The technical development route of GaN high-power power electronic devices expanding to high-power applications is also similar to Si material power electronic devices, that is, the transformation from lateral conduction devices to vertical conduction devices. With the continuous maturity of GaN homoepitaxial technology and the reduction of GaN substrate manufacturing cost, it provides strong support for the realization of vertical conduction electronic devices on GaN substrates. Compared with heterogeneous epitaxial substrates, homogeneous GaN substrates have obvious advantages. The lattice matching with the GaN epitaxial layer improves the crystal quality of the GaN epitaxial layer, simplifies the growth process, and avoids the growth of a complex stress buffer layer, compared with the heterogeneous epitaxial substrate. The main advantages of homoepitaxial are: 1) no lattice mismatch; 2) high thermal conductivity, small thermal mismatch; 3) high electrical conductivity, small leakage current, and simplified device process.

Compared with the lateral conduction device, the vertical conduction device realized by the homogeneous substrate: 1) It improves the chip power per unit area and increases the chip utilization efficiency; 2) The effective contact area of the electrode is large, and the current expansion area in the longitudinal direction is large, achieving high power , high current output density; 3) low dislocation density, which can effectively reduce device gate leakage current, improve material carrier mobility, increase device breakdown voltage, and reduce current collapse effect; 4) at the same time in high-power working environment Under this condition, the device generates a large amount of heat by itself, and the homoepitaxial thermal conductivity is excellent, which is beneficial to the heat dissipation of the device.

GaN homogeneous substrate vertical conduction structure of the field effect transistor has launched some research. In the latest research results, Masakazu KANECHIKA of Toyota Corporation and others fabricated a depletion-type vertical current channel electronic device (Current Aperture Vertical Electron Transistor) on a GaN self-supporting substrate, and the device achieved a threshold voltage of -16V. The on-resistance is 2.6mΩ cm2; see literature Masakazu KANECHIKA, Masahiro SUGIMOTO et al. A Vertical Insulated Gate AlGaN/GaN Heterojunction Field-Effect Transistor; Japanese Journal of Applied Physics, Vol.46, No.21, pp. L503– L505, 2007. In addition, Srabanti Chowdhury, Brian L. Swenson et al. of the University of California, on a similar structure, used fluorine ion processing technology to realize an enhanced vertical device (CAVET) with a threshold voltage of 0.6V; see the literature Srabanti Chowdhury, Brian L. Swenson et al. al. Enhancement and Depletion Mode AlGaN/GaN CAVET With Mg-Ion-Implanted GaN as Current Blocking Layer; IEEE ELECTRON DEVICE LETTERS, VOL.29, NO.6, 2008.

According to the latest research results, the vertical conduction structure MISFET based on AlGaN/GaN heterojunction and insulated gate structure can achieve low on-resistance, high voltage, large conduction current and other characteristics, while the P-type current blocking layer technology has a significant effect on reducing the quality of the upper GaN lattice, which will lead to a decrease in channel mobility and thus affect device performance. There is a depletion effect, which reduces the concentration of the two-dimensional electron gas and further affects the conduction performance of the device.

Contents of the invention

The technical problem solved by the invention is to overcome the deficiencies of the prior art, and provide a GaN vertical conduction MISFET device with simple process and higher stability and a manufacturing method thereof.

In order to solve the problems of the technologies described above, the technical scheme adopted in the present invention is as follows:

A GaN-based MISFET device with vertical conduction, comprising a gate, a source, a drain, an insulating layer, a conductive GaN substrate, and an epitaxial layer formed on the conductive GaN substrate, and the epitaxial layer sequentially includes from bottom to top The first n-type lightly doped GaN layer, the secondary growth mask dielectric layer, the non-doped GaN layer and the heterojunction barrier layer, the groove channel is formed in the middle of the epitaxial layer, the groove channel and the heterostructure The surface of the barrier layer is covered with an insulating layer, the gate is covered at the groove channel on the insulating layer, the source region is formed by etching both ends of the insulating layer, and the source region is evaporated to form an ohmic metal and a heterojunction barrier layer The contacted source and drain are placed on the back of the conductive GaN substrate.

The thickness of the first n-type lightly doped GaN layer is 1-50 μm.

The secondary growth mask dielectric layer is SiO ₂ , SiNx, Al ₂ O ₃ , AlN, HfO ₂ , MgO, Sc ₂ O ₃ , Ga ₂ O ₃ , AlHfOx or HfSiON, and the thickness of the insulating layer is 1-100 nm.

The thickness of the non-doped GaN layer is 10-500nm.

The material of the heterostructure barrier layer includes one or more combinations of the following: AlGaN, AlInN, AlInGaN and AlN; the thickness of the heterostructure barrier layer is 1-50nm.

The material of the insulating layer is SiO ₂ , SiNx, Al ₂ O ₃ , AlN, HfO ₂ , MgO, Sc ₂ O ₃ , Ga ₂ O ₃ , AlHfOx or HfSiON, and the thickness of the insulating layer is 1-100 nm; the source and drain The material is selected from the following group of materials, which includes but not limited to: Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy; the gate material is selected from the following Selected from a group of materials, the group of materials includes but not limited to: Ni/Au alloy, Pt/Al alloy, Pd/Au alloy.

At the same time, the present invention also provides a method for fabricating a GaN-based MISFET device with a vertical structure, which includes the following steps:

growing a first n-type lightly doped GaN layer on a conductive GaN substrate;

forming a secondary growth mask dielectric layer on the first n-type lightly doped GaN layer;

Using photolithography technology to selectively etch the secondary growth mask dielectric layer to remove the secondary growth mask dielectric layer in the gate region;

Laterally grow a non-doped GaN layer on the selective gate region of the etched device;

Growing a heterostructure barrier layer on the undoped GaN layer;

Growing a dielectric layer on the heterojunction barrier layer as a mask layer for dry etching;

Use photolithography technology to selectively etch the mask layer of the gate area; use dry etching to etch groove channels in the gate area;

Depositing an insulating substance on the exposed contact interface composed of the surface of the groove channel and the surface of the heterostructure barrier layer, as the insulating layer of the gate;

Using photolithography technology, the source ohmic contact area is etched on the surface of the insulating layer, the source ohmic contact metal is evaporated on the source area, and the ohmic contact metal drain is evaporated on the conductive GaN substrate surface;

Evaporate the gate on the gate insulating layer.

In the manufacturing method of the present invention, the secondary growth mask dielectric layer is directly used as the current blocking layer, and the gate area is etched selectively, and a non-doped GaN layer is grown in the etched region until the thickness of the non-doped GaN layer exceeds the dielectric layer At this time, the non-doped GaN layer begins to grow on the secondary growth mask dielectric layer until it is flattened to a certain thickness. A high-quality non-doped GaN layer can be obtained on the current blocking layer by using lateral epitaxial growth technology. Thus effectively reducing the lattice quality of the upper epitaxial layer, increasing the two-dimensional electron gas mobility in the access region, effectively reducing the on-resistance, and realizing the natural formation of the gate vertical conductive channel, increasing the device gate threshold voltage, and simplifying the device process , improving device reliability and repeatability.

The steps The first n-type lightly doped GaN layer in the step Non-doped GaN layer, step The growth method of the heterojunction barrier layer includes but not limited to metal organic chemical vapor deposition or molecular beam epitaxy.

The steps The secondary growth mask dielectric layer and steps in The growth methods of the insulating layer include but are not limited to plasma enhanced chemical vapor deposition, atomic deposition, physical vapor deposition or magnetron sputtering.

Another structure of the device of the present invention is: after the secondary growth mask dielectric layer is etched, first grow a P-type GaN layer in the groove area until the growth is close to the height of the secondary growth mask dielectric layer on both sides , switch the growth conditions immediately, and grow the non-doped GaN layer, which will effectively improve the vertical channel conduction voltage and increase the threshold voltage of the entire device.

Compared with the prior art, the technical scheme of the present invention directly uses the insulating dielectric mask layer as the secondary selective growth mask layer. By growing a high-quality lateral epitaxial non-doped GaN layer, a high-quality, low-on-resistance access region is realized, avoiding the GaN lattice in the access region caused by the diffusion of P-type impurities due to the use of a P-type barrier layer Due to the influence of lower quality, the natural formation of the vertical conductive channel of the gate is realized, and a vertical conduction MISFET device is prepared.

Description of drawings

1-10 is a schematic diagram of the device preparation method of Embodiment 1 of the present invention;

11-13 are schematic diagrams of the device structure of Embodiment 2 of the present invention;

Fig. 14 is the structural representation of the finished product of embodiment 2.

Detailed ways

The technical solution of the present invention will be further described below in conjunction with the accompanying drawings.

Example 1

As shown in Figure 11, it is a schematic diagram of the device structure of this embodiment, including a gate 10, a source 8, a drain 9, an insulating layer 7, a conductive GaN substrate 1 and an epitaxial layer thereon, and the epitaxial layer includes a first N-type lightly doped GaN layer 2, secondary growth mask dielectric layer 3, non-doped GaN layer 4 and heterostructure barrier layer 5, the middle part of the non-doped GaN layer 4 forms a barrier for gate conduction The grooved channel 12, the surface of the grooved channel 12 and the heterostructure barrier layer 5 cover the insulating layer 7, the gate 10 covers the grooved channel 12 on the insulating layer, and the two ends of the insulating layer 7 are etched to form In the source region, ohmic metal is evaporated on the source region to form the source 8 in contact with the heterostructure barrier layer 5, and the drain 9 is placed on the back of the conductive GaN substrate.

The fabrication method of the GaN-based MISFET device with vertical conduction is shown in Figure 1-10, including the following steps:

A first n-type lightly doped GaN layer 2 is grown on the conductive GaN substrate 1 by molecular beam epitaxy, with a thickness of 1-50 μm, as shown in FIG. 1 ;

On the first n-type lightly doped GaN layer 2, an insulating dielectric layer is grown by plasma-enhanced chemical vapor deposition as the secondary growth mask dielectric layer 3, and the thickness of the secondary growth mask dielectric layer 3 is 50- 500nm, as shown in Figure 2;

Using photolithography technology, selectively etching the secondary growth mask dielectric layer 3, and removing the secondary growth mask dielectric layer in the gate region; as shown in Figure 3;

A high-quality non-doped GaN layer 4 is laterally epitaxially grown on the etched device by selecting the gate region, and the thickness of the non-doped GaN layer is 60-1000 nm as shown in FIG. 4 ;

Growing a heterostructure barrier layer 5 on the non-doped GaN layer 4, the thickness of the heterostructure barrier layer is 1-50nm, as shown in FIG. 5;

A layer of dielectric layer 6 is grown on the heterojunction barrier layer as a mask layer for dry etching; as shown in Figure 6;

Use photolithography technology to selectively etch the mask layer of the gate area; use dry etching to etch a groove in the gate area, revealing the surface composed of the groove channel surface and the heterostructure barrier layer surface The contact interface of the insulating layer is shown in Figure 7 and Figure 8;

An insulating substance is deposited on the contact interface as the insulating layer 7 of the gate, and the thickness of the insulating layer is 1-100 nm, as shown in FIG. 9 ;

Using photolithography technology, the source ohmic contact area is etched on the surface of the insulating layer, the source ohmic contact metal 8 is evaporated on the source area, and the drain ohmic contact metal 9 is evaporated on the conductive GaN substrate surface, as shown in the figure as shown in 10;

A gate metal 10 is evaporated on the gate insulating layer, as shown in FIG. 11 . So far, the fabrication process of the whole device is completed. FIG. 8 is a schematic diagram of the device structure of Embodiment 1.

Example 2

Figure 14 is a schematic diagram of the device structure of this embodiment, which is similar to the structure of Embodiment 1, the only difference is that after the secondary growth mask dielectric layer 3 is etched, a P-type GaN layer is first grown in the groove region 11. When the growth is close to the height of the insulating dielectric mask layers on both sides, as shown in FIG. 12 , immediately switch the growth conditions to grow the non-doped GaN layer 4 , as shown in FIG. 13 . This will effectively improve the conduction voltage of the vertical channel and increase the threshold voltage of the entire device.

Claims (10)

1. the GaN base MISFET device of a longitudinal conducting, comprise grid (10), source electrode (8), drain electrode (9), insulating barrier (7), conduction GaN substrate (1) and be formed at the epitaxial loayer conducting electricity on GaN substrate (1), described epitaxial loayer comprises the first N-shaped light dope GaN layer (2) from lower to upper successively, diauxic growth mask dielectric layer (3), non-Doped GaN layer (4) and heterostructure barrier layer (5), described epitaxial loayer middle part forms recess channel (12), the surface coverage insulating barrier (7) of recess channel (12) and heterostructure barrier layer (5), the recess channel (12) that grid (10) is covered on insulating barrier (7) is located, formation source region, etching insulating barrier (7) two ends, place, source region evaporation ohmic metal forms the source electrode (8) contacting with heterostructure barrier layer (5), drain electrode (9) is placed in conduction GaN substrate (1) back side.

2. the GaN base MISFET device of longitudinal conducting according to claim 1, is characterized in that, the thickness of described the first N-shaped light dope GaN layer (2) is 1-50 μ m.

3. the GaN base MISFET device of longitudinal conducting according to claim 1, is characterized in that, described diauxic growth mask dielectric layer (3) is SiO ₂, SiNx, Al ₂o ₃, AlN, HfO ₂, MgO, Sc ₂o ₃, Ga ₂o ₃, AlHfOx or HfSiON, thickness of insulating layer is 1-100nm.

4. the GaN base MISFET device of longitudinal conducting according to claim 1, is characterized in that, the thickness of described non-Doped GaN layer (4) is 10-500nm.

5. the GaN base MISFET device of longitudinal conducting according to claim 1, is characterized in that, described heterostructure barrier layer (5) material comprises the combination of following one or more: AlGaN, AlInN, AlInGaN and AlN; Heterostructure barrier layer (5) thickness is 1-50nm.

6. the GaN base MISFET device of longitudinal conducting according to claim 1, is characterized in that, described insulating barrier (7) material is SiO ₂, SiNx, Al ₂o ₃, AlN, HfO ₂, MgO, Sc ₂o ₃, Ga ₂o ₃, AlHfOx or HfSiON, insulating barrier (7) thickness is 1-100nm; Source electrode (8) and drain electrode (9) material are from organizing material and select with next, and this group material includes but not limited to: Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy; Grid material is from organizing material and select with next, and this group material includes but not limited to: Ni/Au alloy, Pt/Al alloy, Pd/Au alloy.

7. make a method for the GaN base MISFET device of longitudinal conducting claimed in claim 1, it is characterized in that, comprise the following steps:

at the upper growth of conduction GaN substrate (1) the first N-shaped light dope GaN layer (2);

at the upper diauxic growth mask dielectric layer (3) that forms of the first N-shaped light dope GaN layer (2);

adopt photoetching technique, selective etch diauxic growth mask dielectric layer (3), the diauxic growth mask dielectric layer of removal area of grid;

on device after etching, select the non-Doped GaN layer of area of grid laterally overgrown (4);

at the upper growth of non-Doped GaN layer (4) heterostructure barrier layer (5);

at heterostructure barrier layer (5) somatomedin layer (6), as the mask layer of dry etching;

adopt photoetching technique, select the mask layer in etching grid region, region; Utilization is dry-etched in area of grid and etches recess channel (12);

at the contact interface deposition megohmite insulant being formed by recess channel (12) surface and heterostructure barrier layer (5) surface manifesting, as the insulating barrier (7) of grid;

adopt photoetching technique, in insulating barrier (7) surface etch, go out source electrode ohmic contact region, source electrode metal ohmic contact on the evaporation of source electrode ohmic contact region, metal ohmic contact drain electrode (9) on conduction GaN substrate surface evaporation;

evaporation grid (10) on gate insulator.

8. the GaN base MISFET device manufacture method of longitudinal conducting according to claim 7, is characterized in that described step in the first N-shaped light dope GaN layer, step non-Doped GaN layer, step the growing method of middle heterostructure barrier layer includes but not limited to Metalorganic Chemical Vapor Deposition or molecular beam epitaxy.

9. the GaN MISFET device manufacture method of longitudinal conducting according to claim 7, is characterized in that described step in diauxic growth mask dielectric layer and step in the growing method of dielectric layer include but not limited to plasma enhanced chemical vapor deposition method, atomic deposition method, physical vaporous deposition or magnetron sputtering method.

10. the GaN MISFET device manufacture method of longitudinal conducting according to claim 7, is characterized in that step in, after described diauxic growth mask dielectric layer (3) is etched, first at recess region growth P-type GaN layer (11), until grow while approaching both sides diauxic growth mask dielectric layers (3) height, switch growth conditions, carry out the growth of non-Doped GaN layer (4).