CN109560120B - GaN normally-off MISFET device with vertical grooves grown in selective area and manufacturing method thereof - Google Patents

Abstract

The invention relates to a GaN normally-off type MISFET device with vertical growth grooves in a selected region and a manufacturing method thereof, comprising a conductive GaN substrate and an epitaxial layer, and the epitaxial layer includes an n-type lightly doped GaN layer and an intrinsic GaN layer and a layer thereon. The secondary epitaxial layer grown in the selected region, the secondary epitaxial layer is the electron blocking layer, the low-voltage GaN layer, the undoped epitaxial GaN layer and the heterostructure barrier layer from bottom to top, and the groove channel is formed after the secondary epitaxial growth. , the surface of the groove channel and the heterostructure barrier layer is covered with an insulating layer, the gate is covered at the groove channel on the insulating layer, the source region is formed by etching both ends of the insulating layer, and the source region is etched to p The type barrier layer forms the base region, the ohmic metal is evaporated in the base region to form a short connection with the source, the ohmic metal is evaporated in the source region to form the source in contact with the heterojunction barrier layer, and the ohmic contact metal of the drain is placed. on the backside of the conductive GaN substrate. The invention improves the switch control ability of the device, reduces the on-resistance of the device, and improves the reliability of the device.

Description

A GaN normally-off MISFET device with vertical grooves grown in selected regions and its manufacturing method

technical field

The present invention relates to the technical field of semiconductor devices, and more particularly, to a GaN normally-off MISFET device with vertical growth grooves in selected regions and a manufacturing method thereof.

Background technique

GaN semiconductor materials have the advantages of large band gap, high breakdown electric field, high saturation electron drift velocity and high thermal conductivity, as well as the existence of two-dimensional electron gas (2DEG) with high concentration and high electron mobility at the heterojunction interface, Compared with Si materials, it is more suitable for the preparation of power electronic devices with high power, large capacity and high switching speed, and becomes an ideal substitute for the next generation of power switching devices.

GaN power switching devices are divided into lateral conduction devices and vertical conduction devices in terms of device structure. The lateral conduction device directly uses the AlGaN/GaN heterojunction 2DEG channel as the device conduction channel, and its active area is concentrated on the surface of the device epitaxial layer, and the source, gate and drain of the device are designed on the same plane of the device . This design structure is a commonly used device structure for GaN-based HFET devices at present, and the device can achieve low on-resistance and high switching frequency under low voltage. However, in the high-voltage working environment, lateral conduction GaN devices have great problems, such as (1) the electric field fringing effect is easily formed at the gate edge, and the device is easy to break down; (2) In addition, due to the ionization of defect states on the surface of the heterostructure barrier layer And the effects of acceptor trap ionization in the GaN epitaxial layer will cause the current collapse of the device and degrade the device performance. The vertical conduction device has obvious advantages over the lateral device: 1. Its source is located on the heterojunction barrier layer, and the drain is located under the conductive substrate. The gate is used to control the vertical conduction channel, which improves the power of the chip per unit area and increases the power of the device. The utilization efficiency of the chip is increased; ②The current is longitudinally distributed in the device, the electric field distribution is more uniform, and the breakdown voltage of the device is effectively improved; ③The high field area is inside the material, away from the surface, which can weaken the influence of the surface state and slow down the current collapse effect. Therefore, vertical conduction GaN switching devices are more suitable for application in high-power, high-voltage working environments.

At present, vertical conduction structure MISFETs based on AlGaN/GaN heterojunctions and insulated gate structures can achieve characteristics such as low on-resistance, high voltage, and large on-current. There are currently three mainstream structures, Fin FET, electronic hole type, and groove type. Among them, the electron hole structure has the advantage of high channel mobility, but it often faces the problem of Mg diffusion in the electron blocking layer (p-GaN) and the problem that it is difficult to achieve normally-off operation. Fin FET can effectively realize normally-off devices without introducing Mg-doped p-GaN, but the problems of the structure's withstand voltage performance and low channel mobility caused by etching need to be solved urgently. The groove structure can realize both high withstand voltage and normally-off devices through thick drift layers, and is a potential solution to realize vertical power devices. However, the problems still faced are as follows: groove etching damage results in low channel mobility. Electron blocking layer Mg diffusion problem. Selected area growth (SAG) can avoid groove etching damage by forming U-shaped trench gate structure by means of secondary epitaxial growth, and has made great progress in the preparation of high-performance lateral conduction normally-off GaN field effect transistors. However, using this scheme faces the following problems when preparing vertical devices: secondary growth interface defects, electron blocking layer Mg diffusion.

SUMMARY OF THE INVENTION

In order to overcome at least one of the above-mentioned defects in the prior art, the present invention provides a GaN normally-off MISFET device with vertical growth grooves in a selected region and a manufacturing method thereof. High control ability, stable and reliable performance.

In order to solve the above-mentioned technical problems, the technical solution adopted in the present invention is: a GaN normally-off MISFET device with vertical grooves in selected regions, the device includes a gate electrode, a source electrode, a drain electrode, an insulating layer, a conductive GaN substrate and An epitaxial layer thereon, the epitaxial layer includes a primary epitaxially grown n-type lightly doped GaN layer and an intrinsic GaN layer and a secondary epitaxial layer grown in a selected region thereon, the secondary epitaxial layer from bottom to top is Electron blocking layer, low voltage GaN layer, undoped GaN layer and heterostructure barrier layer, groove channel is formed after secondary epitaxial growth, the surface of groove channel and heterostructure barrier layer is covered with insulating layer, gate The electrode covers the groove channel on the insulating layer, the source region is formed by etching both ends of the insulating layer, the source region is etched to the electron blocking layer to form the base region, and ohmic metal is evaporated at the base region to form and source Short-circuiting, ohmic metal is evaporated in the source region to form a source in contact with the heterojunction barrier layer, and the ohmic contact metal of the drain is placed on the backside of the conductive GaN substrate.

The invention improves the problem of low electron mobility of the electron blocking layer in the prior art solution, and repairs two interfaces: the electron blocking layer and the secondary growth interface, and the electron blocking layer and the channel interface. The low-doped intrinsic GaN layer is grown by primary epitaxy to improve the secondary epitaxy interface to realize the growth of high-quality electron blocking layer, thereby improving the switching control ability of the device. A low-voltage GaN layer is grown at the interface between the current blocking layer and the upper heterojunction channel, which not only effectively suppresses the high temperature diffusion of Mg and improves the surface of p-GaN, but also improves the electron mobility of the heterojunction channel.

Further, the grooves are V-shaped or U-shaped.

Further, the conductive GaN substrate is a heavily doped GaN substrate, and the conductive GaN substrate can also be composed of a low-resistance silicon substrate or a low-resistance silicon carbide and a conductive buffer layer; the heavily-doped GaN substrate , whose doping concentration is above 10 ¹⁸ , and is lightly doped below this value; the thickness of the n-type lightly doped GaN layer is 1-50 μm.

Further, an n-type heavily doped GaN layer is also included between the n-type lightly doped GaN layer and the secondary epitaxial layer, the thickness of which is 10-100 nm.

Further, the material of the low-pressure GaN layer is low-pressure GaN, and the thickness is 1-500 nm.

Further, the material of the electron blocking layer is a p-type doped GaN layer or a doped high-resistance GaN layer, and can also be a p-type doped AlGaN layer or a doped high-resistance AlGaN layer, and the doped high-resistance layer The doping elements of the GaN layer and the AlGaN layer include but are not limited to carbon or iron, the thickness of the electron blocking layer is 10-500 nm; the thickness of the undoped GaN layer is 10-500 nm;

Further, an AlN layer is grown between the undoped GaN layer and the heterostructure barrier layer, and the thickness of the AlN layer is 1-10 nm.

Further, the heterostructure barrier layer material includes but is not limited to one or any combination of AlGaN, AlInN, InGaN, AlInGaN, AlN, and the heterostructure barrier layer thickness is 5-50 nm .

Further, the insulating layer material includes but is not limited to one or any of SiO ₂ , SiN _x , Al ₂ O ₃ , AlN, HfO ₂ , MgO, Sc ₂ O ₃ , Ga ₂ O ₃ , AlHfO _x or HfSiON Several stacking combinations, the thickness of the insulating layer is 1-100 nm; the source and drain materials include but are not limited to Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy or Ti/Al /Mo/Au alloy, other metals or alloys that can achieve ohmic contact can be used as source and drain materials; the gate materials include but are not limited to Ni/Au alloy, Pt/Al alloy or Pd/Au alloy , and other metals or alloys that can achieve high threshold voltage can be used as gate materials.

The present invention also provides a GaN normally-off MISFET device with vertical grooves in the selected region, comprising the following steps:

S1. One-time epitaxial growth of an n-type lightly doped GaN layer on a conductive GaN substrate; an intrinsic GaN layer;

S2, growing a layer of SiO ₂ on the intrinsic GaN layer as a mask layer;

S3, through the method of photolithography, the mask layer formed on the gate region is retained;

S4, secondary epitaxial growth of an electron blocking layer, a low-voltage GaN layer, an undoped GaN layer and a heterostructure barrier layer in a selected area to form a groove gate;

S5, removing the mask layer above the gate region;

S6, depositing the insulating layer of the gate on the heterojunction barrier layer and the groove;

S7. The device isolation is completed by dry etching, and the base ohmic contact area is etched on the insulating layer at the same time; and the base ohmic contact metal is evaporated on the base area

S8, etching the source ohmic contact region on the insulating layer;

S9, evaporating source ohmic contact metal on the source region, and evaporating drain ohmic contact metal on the backside of the conductive GaN substrate;

S10, evaporating gate metal on the gate region on the insulating layer at the groove.

Further, the growth methods of the n-type lightly doped GaN layer and the intrinsic GaN layer in the step S1 and the electron blocking layer, the low-voltage GaN layer, the undoped GaN layer and the heterostructure barrier layer in the step S4 are as follows: Metal organic chemical vapor deposition or molecular beam epitaxy;

Further, the growth methods of the mask layer in the step S2 and the insulating layer in the step S5 are plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition or magnetron sputtering.

Compared with the prior art, the beneficial effect is that the device adopts the secondary epitaxial growth technology, and on the n-type lightly doped GaN layer and the intrinsic GaN layer, the electron blocking layer, the low-voltage GaN layer and the undoped GaN layer are secondary epitaxially grown. layer and heterojunction barrier layer, the use of low-voltage GaN layer effectively improves the channel mobility, and the channel sidewall is grown in situ through secondary epitaxy, which protects the p-type layer and the mis interface and the p-type and upper layers. The interface quality of the heterojunction can reduce the leakage of the current blocking layer. At the same time, the use of the primary growth of the intrinsic GaN layer completely reduces the interface state problem of the secondary growth and overcomes the influence of the background doping during the secondary growth. These improvements together The threshold voltage stability of the device is improved, and the leakage problem of each electrode is reduced.

Description of drawings

1-9 are process schematic diagrams of the device manufacturing method according to Embodiment 1 of the present invention;

10 is a schematic diagram of a device structure according to Embodiment 2 of the present invention;

11 is a schematic diagram of a device structure according to Embodiment 3 of the present invention;

FIG. 12 is a secondary epitaxy SEM structure diagram of the present invention.

Detailed ways

The accompanying drawings are for illustrative purposes only, and should not be construed as limiting the present invention; in order to better illustrate the present embodiment, some parts of the accompanying drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art It is understandable to the artisan that certain well-known structures and descriptions thereof may be omitted from the drawings. The positional relationships described in the drawings are only for exemplary illustration, and should not be construed as limiting the present invention.

This experimental group has verified the cross-sectional morphology in the related research work of the secondary epitaxy growth of GaN: as shown in Figure 12 is the secondary epitaxy SEM structure diagram, it can be clearly seen in Figure 12 that the secondary epitaxy contains a 60 The sidewall of the angle and the distribution of each layer on the sidewall also reflect from the side that a channel layer and a heterojunction grown on it can be grown in situ through secondary growth. It is foreseeable To be able to reduce the channel resistance and improve the threshold voltage stability and other beneficial properties.

Example 1

FIG. 9 is a schematic diagram of the device structure of this embodiment, the device includes a gate electrode, a source electrode, a drain electrode, an insulating layer 11, a conductive GaN substrate 1 and an epitaxial layer thereon, and the epitaxial layer includes one epitaxial growth The n-type lightly doped GaN layer 2 and the intrinsic GaN layer 3 and the secondary epitaxial layer grown in the selected area thereon, the secondary epitaxial layer from bottom to top is the electron blocking layer 4, the low-voltage GaN layer 5, the non-doped GaN layer The hetero GaN layer 6 and the heterostructure barrier layer 7, the groove channel is formed after the secondary epitaxial growth, the surface of the groove channel and the heterostructure barrier layer 7 is covered with the insulating layer 11, and the gate is covered on the insulating layer 11 At the groove channel above, the source region is formed by etching both ends of the insulating layer 11, the source region is etched to the electron blocking layer 4 to form the base region, and the ohmic metal 9 is evaporated at the base region to form a short connection with the source. As a result, ohmic metal 8 is evaporated in the source region to form a source electrode in contact with the heterojunction barrier layer, and the drain ohmic contact metal 10 is placed on the backside of the conductive GaN substrate 1 .

Specifically, the groove channel is U-shaped, and the conductive GaN substrate 1 is a heavily doped GaN substrate.

The thickness of the n-type lightly doped GaN layer 2 is 1-50 μm; an intrinsic GaN layer 3 is also included between the n-type lightly doped GaN layer 2 and the secondary epitaxial layer, and the thickness is 10-100 nm. The material of the low-voltage GaN layer 5 is low-pressure GaN with a thickness of 1-500 nm; the material of the electron blocking layer 4 is a p-type doped GaN layer or a p-type doped AlGaN layer; the thickness of the electron blocking layer 4 is 10-500 nm; The thickness of the undoped GaN layer 6 is 10-500 nm.

The material of the heterostructure barrier layer 7 is one or any combination of AlGaN, AlInN, InGaN, AlInGaN, and AlN, and the thickness of the heterostructure barrier layer 7 is 5-50 nm.

The insulating layer 11 is made of SiO2, SiNx, Al2O3, AlN, HfO2, MgO, Sc2O3, Ga2O3, AlHfOx or HfSiON, and the thickness of the insulating layer 11 is 1-100 nm; the source and drain electrodes are Ti/Al/Ni/Au alloys , Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy; the gate material is Ni/Au alloy, Pt/Al alloy or Pd/Au alloy.

The fabrication method of the above-mentioned vertically conducting GaN normally-off MISFET device is shown in Figures 1 to 9, including the following steps:

S1, using a metal organic chemical vapor deposition method, grow a layer of n-type lightly doped GaN layer 2 and an intrinsic GaN layer 3 on the conductive GaN substrate 1, as shown in FIG. 1;

S2, by plasma-enhanced chemical vapor deposition of a layer of SiO ₂ as the mask layer 14, as shown in FIG. 2;

S3, select area etching by photolithography, and retain the mask layer 14 above the gate area, as shown in FIG. 3;

S4, using the metal organic chemical vapor deposition method, select the region to re-epitaxially grow the electron blocking layer 4, the low-voltage GaN layer 5, the undoped GaN layer 6 and the heterostructure barrier layer 7 to form a groove gate, as shown in Figure 4 shown;

S5, using an etching method to remove the mask layer 14 above the gate region, as shown in FIG. 5 ;

S6, using plasma enhanced chemical vapor deposition method, deposit a layer of high-K dielectric insulating layer 11 on the surface of the heterojunction barrier layer and the groove gate region, as shown in FIG. 6 ;

S7. Use ICP to complete the device isolation, and at the same time etch the base ohmic contact area on the insulating layer 11 on the heterojunction barrier layer, and use the evaporation process to evaporate Ni/Au alloy on the base area as the base. ohmic contact and as shown in Figure 7

S8. Use ICP to complete device isolation, and at the same time etch the source ohmic contact area on the insulating layer 11 on the heterojunction barrier layer, and use the evaporation process to evaporate Ti/Al/Ni/Au alloy on the source area As the ohmic contact of the source, Ti/Al/Ni/Au alloy is also evaporated on the back of the conductive GaN substrate 1 as the ohmic contact of the drain, as shown in Figure 8;

S9, the gate metal 12Ni/Au alloy is vapor-deposited on the insulating layer 11 in the groove gate region as the gate, as shown in FIG. 9 .

So far, the whole device fabrication process is completed. FIG. 9 is a schematic diagram of the device structure of Embodiment 1. FIG.

Example 2

FIG. 10 shows a schematic diagram of the device structure of this embodiment, which is similar to the structure of Embodiment 1, except that an AlN layer 15 is inserted into the undoped GaN layer 6 and the heterostructure barrier layer 7. The AlN layer 15 can improve 2DEG mobility at the heterostructure channel.

Example 3

FIG. 11 is a schematic diagram of the device structure of this example, which is similar to Embodiment 1, except that the conductive GaN substrate 1 is replaced by a low-resistance silicon substrate or a low-resistance silicon carbide 17 and a conductive buffer layer 16, which is inexpensive to use. The silicon substrate can reduce the cost of the device, and the above-mentioned low resistance refers to the resistivity of the silicon substrate ρ < 20 Ω·cm.

In addition, it should be noted that the drawings of the above embodiments are for illustrative purposes only, and therefore are not necessarily drawn to scale.

Obviously, the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, rather than limiting the embodiments of the present invention. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. Any modifications, equivalent replacements and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the claims of the present invention.

Claims (10)

1. A GaN normally-off MISFET device with vertical grooves in selected regions, the device comprising a gate electrode, a source electrode, a drain electrode, an insulating layer (11), a conductive GaN substrate (1) and an epitaxial layer thereon, The epitaxial layer comprises a primary epitaxially grown n-type lightly doped GaN layer (2) and an intrinsic GaN layer (3) and a secondary epitaxial layer grown in a selected region thereon, the secondary epitaxial layer from bottom to top is The electron blocking layer (4), the low-voltage GaN layer (5), the undoped GaN layer (6) and the heterostructure barrier layer (7), after the secondary epitaxial growth, a groove channel, a groove channel and a heterostructure are formed. The surface of the material structure barrier layer (7) is covered with the insulating layer (11), the gate electrode is covered at the groove channel on the insulating layer (11), the two ends of the insulating layer (11) are etched to form source regions, and the etching The base region is formed from the source region to the electron blocking layer (4), the ohmic metal is evaporated at the base region to form a short connection with the source, and the ohmic metal is evaporated in the source region to form a source in contact with the heterojunction barrier layer , the drain ohmic contact metal (10) is placed on the backside of the conductive GaN substrate (1). 2 . The GaN normally-off MISFET device with vertical grooves for selective region growth according to claim 1 , wherein the grooves are U-shaped. 3 . 3 . The GaN normally-off MISFET device with vertical selected region growth grooves according to claim 2 , wherein the conductive GaN substrate ( 1 ) is a heavily doped GaN substrate, or a low-density GaN substrate. 4 . It is composed of a resistive silicon substrate or low-resistance silicon carbide and a conductive buffer layer. 4 . The GaN normally-off MISFET device with vertical selected region growth grooves according to claim 2 , wherein the thickness of the n-type lightly doped GaN layer ( 2 ) is 1-50 μm; 5 . An intrinsic GaN layer (3) is also contained between the n-type lightly doped GaN layer (2) and the secondary epitaxial layer, the thickness of which is 10-100 nm. 5. A GaN normally-off MISFET device with vertical selected region growth grooves according to claim 3 or 4, characterized in that: the material of the low-voltage GaN layer (5) is low-pressure GaN, and the thickness is 1-500 mm nm; the material of the electron blocking layer (4) is a p-type doped GaN layer or a p-type doped AlGaN layer; the thickness of the electron blocking layer (4) is 10-500 nm; the undoped GaN layer The thickness of the layer (6) is 10-500 nm. 6 . The GaN normally-off MISFET device with vertical selected region growth grooves according to claim 5 , characterized in that: between the undoped GaN layer ( 6 ) and the heterostructure barrier layer ( 7) An AlN layer (15) is also grown between, and the thickness of the AlN layer (15) is 1-10 nm. 7 . The GaN normally-off MISFET device with vertical growth grooves in the selected region according to claim 6 , wherein the material of the heterostructure barrier layer ( 7 ) is AlGaN, AlInN, InGaN, AlInGaN, One or any combination of AlN, the thickness of the heterostructure barrier layer (7) is 5-50 nm. 8 . The GaN normally-off MISFET device with vertical selected region growth grooves according to claim 7 , wherein the insulating layer ( 11 ) is made of SiO ₂ , SiN _x , Al ₂ O ₃ , and AlN. 9 . , HfO ₂ , MgO, Sc ₂ O ₃ , Ga ₂ O ₃ , AlHfO _x or HfSiON, the insulating layer (11) has a thickness of 1-100 nm; the source and drain materials are Ti/Al/Ni/ Au alloy, Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy; the gate material is Ni/Au alloy, Pt/Al alloy or Pd/Au alloy. 9. a kind of manufacture method of the vertical GaN normally-off MISFET device of a kind of selective area growth groove according to claim 1, is characterized in that, comprises the following steps: S1. One-time epitaxial growth of an n-type lightly doped GaN layer (2) and an intrinsic GaN layer (3) on a conductive GaN substrate (1); S2. A layer of SiO ₂ is grown on the intrinsic GaN layer (3) as a mask layer (14); S3. By means of photolithography, the mask layer (14) formed over the gate region is retained; S4. Secondary epitaxial growth of an electron blocking layer (4), a low-voltage GaN layer (5), an undoped GaN layer (6) and a heterostructure barrier layer (7) in a selected area to form a groove gate; S5. Remove the mask layer (14) over the gate region; S6. The insulating layer (11) of the gate is deposited on the heterojunction barrier layer and the groove; S7. Dry etching is used to complete the device isolation, and at the same time, the base ohmic contact region is etched on the insulating layer (11); and the base ohmic contact metal (9) is evaporated on the base region. S8. Etch the source ohmic contact region on the insulating layer (11); S9. The source ohmic contact metal (8) is evaporated on the source region, and the drain ohmic contact metal (10) is evaporated on the backside of the conductive GaN substrate (1); S10. Evaporating gate metal (12) on the gate region of the insulating layer (11) at the groove. 10 . The method for fabricating a GaN normally-off MISFET device with vertical growth grooves in a selected region according to claim 9 , wherein the n-type lightly doped GaN layer ( 2 ) in the step S1 , the present The growth method of the GaN layer (3) and the electron blocking layer (4), the low voltage GaN layer (5), the undoped GaN layer (6) and the heterostructure barrier layer (7) in step S4 is metal organic chemistry Vapor deposition or molecular beam epitaxy; The growth methods of the mask layer (14) in the step S2 and the insulating layer (11) in the step S5 are plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition or magnetron sputtering.

Images