CN104638010B - A kind of GaN normally-off MISFET devices laterally turned on and preparation method thereof - Google Patents

Abstract

The invention relates to a lateral conduction GaN normally-off MISFET device, which comprises a substrate, an epitaxial layer grown on the substrate, a gate, a source electrode, a drain electrode and an insulating layer. The epitaxial layer includes a stress buffer layer and a GaN epitaxial layer grown by primary epitaxial growth, and a secondary epitaxial layer grown on it in a selective region, and the secondary epitaxial layer is an impurity filter layer, a non-doped epitaxial GaN layer from bottom to top and the heterostructure barrier layer, the second epitaxial growth forms the groove channel, the surface of the groove channel and the heterostructure barrier layer covers the insulating layer, the gate covers the groove channel on the insulating layer, and the engraved Both ends of the insulating layer are etched to form source and drain regions, and metal is evaporated on the source and drain regions to form the source and drain in ohmic contact with the heterostructure barrier layer. The device of the present invention has simple structure, high process repeatability and reliability, and can effectively inhibit the diffusion of impurities at the secondary growth interface to the secondary epitaxial layer, thereby effectively reducing the scattering of impurities in 2DEG in the secondary growth heterostructure channel and improving its migration. The rate reduces the on-resistance of the device, so that the device can obtain high output current density and high switching ratio.

Description

A GaN normally-off MISFET device with lateral conduction and its manufacturing method

technical field

The present invention relates to the technical field of semiconductor devices, in particular to a GaN normally-off MISFET device with lateral conduction and a manufacturing method thereof.

Background technique

GaN semiconductor materials have superior properties such as large band gap, high breakdown electric field, large saturated electron drift velocity and high thermal conductivity, and there is a two-dimensional electron gas with high concentration and high electron mobility at the AlGaN/GaN heterojunction interface ( 2DEG), compared with Si materials, it is more suitable for the preparation of power electronic devices with high power, large capacity and high switching speed, and becomes an ideal substitute for the next generation of power switching devices.

In power electronic devices based on converter technology, the power switching transistors that control the converter process are normally off (also known as enhanced), which is the basis for ensuring the "failure safety" of power electronic circuits. However, the high concentration of two-dimensional electron gas generated by the polarization field in the AlGaN/GaN heterojunction makes it difficult for the conductive channel in the field effect transistor to be blocked by the depletion region formed by the Schottky contact, achieving stable performance. The normally-off GaN power switching device is still a difficult point recognized by the international scientific and technological circles and industrial circles. At present, GaN-based normally-off field effect transistors are mainly made of heterojunction. The main methods are: concave gate structure, thin barrier layer structure, gate fluoride plasma implantation, growth of InGaN layer under the gate, gate The p-type AlGaN layer (or p-type GaN layer) and the like are grown under the pole. The recessed gate structure and gate fluoride plasma implantation, which are mainstream technologies, will inevitably cause damage to the material due to the plasma etching and implantation methods, thereby deteriorating the working performance and reliability of the device. However, other implementation methods also have their own disadvantages.

In recent years, there have been related reports on the process of realizing lateral conduction GaN normally-off field effect transistors by using selective area growth technology (SAG) (see literature: Yuhua Wen, Zhiyuan He, Jialin Li, et al.Enhancement-mode AlGaN /GaN heterostructure field effect transistors fabricated by selective area growth technique. APPLIED PHYSICS LETTERS 98,072108 (2011) and literature Yao Yao, Zhiyuan He, Fan Yang, et al. Normally-off GaNrecessed-gate MOSFET fabricated by selective area growth. Applied technology Express 7, 016502 (2014)). Selected area growth technology is used to design and prepare lateral conduction GaN normally-off field effect transistors, which avoids damage to the lattice at the concave gate by plasma etching or fluorine ion treatment, and improves device performance. Secondary epitaxial growth of high-quality heterostructure channels is the basis for ensuring low on-state resistance and high switching ratio characteristics of the device, and is one of the keys in the preparation method and structural design of this device. However, in the secondary growth, there is often a background doping of impurity elements. For example, W. Lee et al. from the Georgia Institute of Technology in the United States have reported that there is a high concentration of Si impurities at the secondary growth interface of GaN, which has a great influence on the concentration and mobility of the heterostructure channel 2DEG (see literature: W. Lee, J.-H. Ryou, D.Yoo, et al. Optimization of Fe doping at the regrowth interface of GaN for applications to III-nitride-based heterostructure field-effect transistors. APPLIED PHYSICS LETTERS 90, 093509(2007)). Especially in the lateral conduction GaN normally-off field effect transistor prepared by selective area growth technology, the secondary growth heterostructure channel (conductive active layer) is very close to the secondary growth interface, and it is very easy to be destroyed by the secondary growth interface. Background dopant element contamination leads to device performance degradation.

Contents of the invention

The purpose of the present invention is mainly to improve the performance of the heterostructure channel of the secondary epitaxial growth in the prior art scheme, improve the mobility of the heterostructure channel 2DEG, and provide a method capable of achieving low on-resistance and high output current density. 1. A horizontal conduction GaN normally-off MISFET device with high switching ratio and superior performance and a manufacturing method thereof.

The invention adopts a selective region growth method to prepare a lateral conduction normally-off GaN field effect transistor. Selected area growth generally requires a patterned mask layer to select the region to be grown. Usually, the main steps of forming a patterned mask layer include: first deposit a layer of SiO ₂ on the substrate GaN epitaxial layer as a mask layer, and then pass The photolithography process forms a photoresist protective layer with a certain pattern on the _SiO2 mask layer, and then uses an etching process to remove the exposed _SiO2 Mask layer, then organic cleaning removes the photoresist protective layer, and finally The SiO ₂ retained on the GaN epitaxial layer is a patterned mask layer, and the non-doped GaN layer and heterostructure barrier layer can be regrown in the GaN epitaxial layer region (secondary growth interface) without a mask layer. However, the following problems will be encountered in the process of this masking process: it is difficult to etch the _SiO2 clean when using an etching process to remove the _SiO2 mask layer, and there will be a large amount of residue on the secondary growth interface. During the secondary epitaxial growth, the SiO2 Residual impurity elements are easily diffused into the secondary growth heterostructure channel at high temperature, which seriously scatter the channel 2DEG, resulting in a significant decrease in 2DEG mobility.

In the manufacturing method of the present invention, a layer of impurity filter layer is first grown by secondary epitaxy, and the impurity filter layer can effectively reduce the pollution of the heterogeneous structure channel grown by secondary epitaxy by the upward diffusion of impurities at the secondary growth interface, and the secondary epitaxy High-quality heterojunction channels are grown, resulting in improved device performance.

In order to solve the above technical problems, the technical solution adopted by the present invention is: a GaN normally-off MISFET device with lateral conduction, its structure includes a substrate, a stress buffer layer, a GaN epitaxial layer, and a secondary epitaxial growth layer from bottom to top. The impurity filter layer and the non-doped GaN layer and the heterostructure barrier layer, the second epitaxial growth forms grooves, the exposed surface of the groove channel and the heterostructure barrier layer is covered with an insulating layer, and the heterostructure barrier layer A source electrode and a drain electrode are formed at both ends of the layer, and a gate electrode is covered on the insulating layer at the channel of the groove.

The groove has a U-shaped or trapezoidal structure.

The substrate is any one of Si substrate, sapphire substrate and silicon carbide substrate.

The stress buffer layer is any one or combination of AlN, AlGaN, GaN; the thickness of the stress buffer layer is 100 nm~10 μm.

The GaN epitaxial layer is an unintentionally doped GaN epitaxial layer or a doped high-resistance GaN epitaxial layer, and the doping element of the doped high-resistance layer is carbon or iron; the thickness of the GaN epitaxial layer is 100 nm to 5 μm .

The material of the impurity filter layer is aluminum-containing nitride, including but not limited to one or any combination of AlGaN, AlInN, AlInGaN, AlN, with a thickness of 1-500 nm, and the concentration of aluminum components can be changed.

The thickness of the non-doped GaN layer is 10-500 nm; the heterostructure barrier layer material includes but not limited to one or any combination of AlGaN, AlInN, InGaN, AlInGaN, AlN, the The thickness of the heterostructure barrier layer is 5-50 nm.

An AlN layer is also grown between the non-doped GaN layer and the heterostructure barrier layer, and the thickness of the AlN layer is 1-10 nm.

The insulating layer material includes but not limited to one or any of SiO ₂ , SiN _x , Al ₂ O ₃ , AlN, HfO ₂ , MgO, Sc ₂ O ₃ , Ga ₂ O ₃ , AlHfO _x or HfSiON stacking combination, the thickness of the insulating layer is 1-100 nm;

The source and drain materials include but are not limited to Ti/Al/Ni/Au alloys, Ti/Al/Ti/Au alloys or Ti/Al/Mo/Au alloys, and various other metals or alloys capable of ohmic contact Both can be used as source and drain materials; the gate material includes but not limited to Ni/Au alloy, Pt/Al alloy or Pd/Au alloy, and various other metals or alloys that can achieve high threshold voltage can be used as gate pole material.

A method of manufacturing a GaN normally-off MISFET device with lateral conduction, comprising the following steps:

S1, growing a stress buffer layer on the Si substrate;

S2, growing a high-resistance GaN epitaxial layer on the stress buffer layer;

S3, depositing a layer of SiO ₂ on the high-resistance GaN epitaxial layer as a mask layer;

S4. Reserving the mask layer formed on the gate region by photolithography;

S5. Secondary epitaxial growth of an impurity filter layer, a non-doped GaN layer and a heterostructure barrier layer in a selected region to form a recessed gate;

S6, removing the mask layer above the gate region;

S7, depositing an insulating layer of the gate on the heterojunction barrier layer and the groove;

S8. Complete device isolation by dry etching, and simultaneously etch source and drain ohmic contact regions on the insulating layer;

S9, evaporating source and drain ohmic contact metals on the source and drain regions;

S10, evaporating gate metal on the gate region on the insulating layer at the groove.

The growth methods of the stress buffer layer and GaN epitaxial layer in steps S1 and S2 and the impurity filter layer, non-doped GaN layer and heterostructure barrier layer in step S5 are metal organic chemical vapor deposition or molecular beam Epitaxy;

The mask layer in step S3 and the insulating layer in step S7 are grown by plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition or magnetron sputtering.

Compared with the prior art, the beneficial effect is that the present invention proposes a GaN normally-off MISFET device with lateral conduction and its manufacturing method. The device adopts the secondary epitaxial growth technology. The impurity filter layer, non-doped GaN layer and heterojunction barrier layer are epitaxially grown, and the impurity filter layer is used to block impurities to effectively prevent impurities at the secondary growth interface from diffusing to the secondary epitaxial layer in a high-temperature growth environment, thereby Reduce the scattering of 2DEG impurities in the heterostructure, improve the mobility, and enable the device to obtain low on-resistance, high output current density, and high switching ratio characteristics.

Description of drawings

1-10 is a schematic diagram of the device manufacturing method of Embodiment 1 of the present invention;

11 is a schematic diagram of the device structure of Embodiment 2 of the present invention;

Fig. 12 is an experimental data diagram of the thin-layer AlGaN impurity filter layer controlling the Si impurity in the GaN epitaxial structure.

Detailed ways

The accompanying drawings are for illustrative purposes only, and should not be construed as limitations on this patent; in order to better illustrate this embodiment, certain components in the accompanying drawings will be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art It is understandable that some well-known structures and descriptions thereof may be omitted in the drawings. The positional relationship described in the drawings is for illustrative purposes only, and should not be construed as a limitation on this patent.

The experimental group has verified the function of the impurity filter layer in the research work related to the heterogeneous epitaxial growth of GaN on Si substrates: the curve (a) in Figure 12 shows the Si impurities in the GaN epitaxial structure after adding a thin layer of AlGaN impurity filter layer Concentration, the curve (b) in Figure 12 is the Si impurity concentration in the epitaxial structure grown without the thin AlGaN impurity filter layer. Obviously, after adding the AlGaN impurity filter layer, the Si impurity concentration in the epitaxial structure is reduced by about an order of magnitude compared with the epitaxial structure without the impurity filter layer, indicating that the AlGaN impurity filter layer can significantly inhibit the upward diffusion of Si elements into the epitaxial structure. The realization of the function of the impurity filter layer is mainly due to the fact that its lattice constant is smaller than that of the GaN layer, which limits the diffusion ability of impurity atoms.

Example 1

Figure 10 is a schematic diagram of the device structure of this embodiment, and its structure includes a substrate 1, a stress buffer layer 2, a GaN epitaxial layer 3, an impurity filter layer 4 grown by secondary epitaxial growth, and a non-doped GaN layer from bottom to top. Layer 5 and heterostructure barrier layer 6, the second epitaxial growth forms grooves, the groove channel and the exposed surface of heterostructure barrier layer 6 cover an insulating layer 7, and the two ends of heterostructure barrier layer 6 A source 8 and a drain 9 are formed, and a gate 10 is covered on the insulating layer 8 at the groove channel.

The fabrication method of the above-mentioned GaN normally-off MISFET device with lateral conduction is shown in Figure 1-Figure 10, including the following steps:

S1. A stress buffer layer (2) is grown on the Si substrate (1) by metal-organic chemical vapor deposition, as shown in FIG. 1 ;

S2. Using a metal-organic chemical vapor deposition method to grow a high-resistance GaN epitaxial layer (3) on the stress buffer layer (2), as shown in FIG. 2 ;

S3. Depositing a layer of SiO ₂ by plasma-enhanced chemical vapor phase as a mask layer (11), as shown in FIG. 3 ;

S4. Etching a selected area by a photolithography method, and retaining the mask layer (11) above the gate area, as shown in FIG. 4 ;

S5. Using the metal-organic chemical vapor deposition method, the impurity filter layer (4), the non-doped GaN layer (5) and the heterostructure barrier layer are selectively grown on the substrate with the mask layer (11) for secondary epitaxial growth (6), forming a groove grid, as shown in FIG. 5 ;

S6, using an etching method to remove the mask layer (11) above the gate region, as shown in Figure 6;

S7. Deposit a layer of high-K dielectric insulating layer (7) on the surface of the heterojunction barrier layer (6) and the grooved gate area by plasma-enhanced chemical vapor deposition, as shown in FIG. 7 ;

S8. Use ICP to complete device isolation, and at the same time, etch the source and drain ohmic contact regions at both ends of the insulating layer (7) on the heterojunction barrier layer (6), as shown in FIG. 8 ;

S9. Evaporate Ti/Al/Ni/Au alloy on the source and drain regions as the ohmic contact metal of the source (8) and drain (9), as shown in FIG. 9 ;

S10. Evaporate Ni/Au alloy on the insulating layer in the grooved gate area as the gate (10) metal, as shown in FIG. 10 .

So far, the fabrication process of the whole device is completed. FIG. 10 is a schematic diagram of the device structure of Embodiment 1.

Example 2

As shown in Figure 11 is a schematic diagram of the device structure of this embodiment, which is similar to the structure of Embodiment 1, the only difference is that an AlN layer 12 is inserted between the non-doped GaN layer 5 and the heterostructure barrier layer 6, and the AlN layer The 2DEG mobility at the heterostructure channel can be improved.

In addition, it should be noted that the drawings of the above embodiments are only for illustrative purposes, and thus are not necessarily drawn to scale.

Apparently, the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, rather than limiting the implementation of the present invention. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. All modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the claims of the present invention.

Claims (8)

1. A method for fabricating a laterally conducting GaN normally-off MISFET device, characterized in that the laterally conducting GaN normally-off MISFET device comprises a substrate (1) and a stress buffer layer ( 2), a GaN epitaxial layer (3), an impurity filter layer (4) grown by secondary epitaxial growth, a non-doped GaN layer (5) and a heterostructure barrier layer (6), the GaN epitaxial layer (3), The impurity filter layer (4) of the secondary epitaxial growth is in direct contact, and the secondary epitaxial growth forms grooves, the groove channel and the heterostructure barrier layer (6) and the exposed surface is covered with an insulating layer (7), and the heterostructure A source (8) and a drain (9) are formed at both ends of the barrier layer (6), and the insulating layer (7) at the groove channel is covered with a gate (10); The fabrication method of the laterally conducting GaN normally-off MISFET device comprises the following steps: S1. Growing a stress buffer layer (2) on the Si substrate (1); S2. Growing a high-resistance GaN epitaxial layer on the stress buffer layer (3); S3, depositing a layer of SiO ₂ on the high-resistance GaN epitaxial layer as a mask layer (11); S4. Reserving the mask layer (11) formed on the gate region by photolithography; S5. Secondary epitaxial growth of the impurity filter layer (4), non-doped GaN layer (5) and heterostructure barrier layer (6) in selected regions to form a grooved gate; S6. Removing the mask layer (11) above the gate region; S7, depositing an insulating layer (7) of the gate on the heterostructure barrier layer and the groove; S8. Complete device isolation by dry etching, and simultaneously etch source and drain ohmic contact regions on the insulating layer (7); S9, evaporating source (8) and drain (9) ohmic contact metals on the source and drain ohmic contact regions; S10, evaporating the gate (10) metal on the gate region on the insulating layer at the groove. 2 . The method for manufacturing a GaN normally-off MISFET device with lateral conduction according to claim 1 , wherein the groove is in a U-shaped or ladder-shaped structure. 3 . 3. The method for manufacturing a GaN normally-off MISFET device with lateral conduction according to claim 1, characterized in that: the stress buffer layer (2) is any one or a combination of AlN, AlGaN, and GaN ; The thickness of the stress buffer layer is 100 nm~10 μm. 4. A method for fabricating a lateral conduction GaN normally-off MISFET device according to claim 1, characterized in that: the GaN epitaxial layer (3) is an unintentionally doped GaN epitaxial layer or doped A high-resistance GaN epitaxial layer, the doping element of the doped high-resistance GaN epitaxial layer is carbon or iron; the thickness of the GaN epitaxial layer is 100 nm to 10 μm. 5. The method for manufacturing a GaN normally-off MISFET device with lateral conduction according to claim 1, characterized in that: the material of the impurity filter layer (4) is aluminum-containing nitride, and the aluminum-nitrogen-containing The compound is one or any combination of AlGaN, AlInN, AlInGaN, AlN, the thickness is 1-500 nm, and the concentration of aluminum components can be changed. 6. The method for fabricating a lateral conduction GaN normally-off MISFET device according to claim 1, characterized in that: the thickness of the non-doped GaN layer (5) is 10-500 nm; the The material of the heterostructure barrier layer (6) is one or any combination of AlGaN, AlInN, InGaN, AlInGaN, AlN, and the thickness of the heterostructure barrier layer (6) is 5-50 nm; An AlN layer (12) is also grown between the non-doped GaN layer (5) and the heterostructure barrier layer (6), and the thickness of the AlN layer (12) is 1-10 nm. 7. The method for manufacturing a GaN normally-off MISFET device with lateral conduction according to claim 1, characterized in that: the material of the insulating layer (7) is SiO ₂ , SiN _x , Al ₂ O ₃ , AlN, HfO ₂ , MgO, Sc ₂ O ₃ , Ga ₂ O ₃ , AlHfO _x or HfSiON, the thickness of the insulating layer (7) is 1-100 nm; the source (8) and drain (9) materials are Ti /Al/Ni/Au alloy, Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy; the material of the gate (10) is Ni/Au alloy, Pt/Al alloy or Pd/Au alloy. 8. A method for fabricating a GaN normally-off MISFET device with lateral conduction according to claim 1, characterized in that: the stress buffer layer (2) and the GaN epitaxial layer (3) in the steps S1 and S2 ) and the impurity filter layer (4), non-doped GaN layer (5) and heterostructure barrier layer (6) in step S5 are grown by metal-organic chemical vapor deposition or molecular beam epitaxy; The mask layer in step S3 and the insulating layer in step S7 are grown by plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition.