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CN111223933A - Novel epitaxial layer structure for improving threshold voltage of GaN enhanced MOSFET - Google Patents

Novel epitaxial layer structure for improving threshold voltage of GaN enhanced MOSFET Download PDF

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CN111223933A
CN111223933A CN201811422595.4A CN201811422595A CN111223933A CN 111223933 A CN111223933 A CN 111223933A CN 201811422595 A CN201811422595 A CN 201811422595A CN 111223933 A CN111223933 A CN 111223933A
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threshold voltage
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epitaxial layer
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王茂俊
陶明
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Peking University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

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Abstract

本发明公开了一种提高GaN增强型MOSFET阈值电压的新型外延层结构及基于该结构的器件制备方法，涉及电力电子器件及功率开关领域。新型结构自下而上包括：衬底、GaN缓冲层、本征GaN层、Mg掺杂P型GaN层、GaN沟道层和AlGaN势垒层。在该结构上用凹槽栅工艺形成钝化层、凹槽栅、平面隔离、绝缘栅介质层、欧姆接触以及栅和源漏欧姆金属电极即可制备出高阈值电压增强型GaN MOSFET。本发明在本征GaN层中插入P型GaN层，将其完全刻蚀后，沟道反型区域除了本征GaN层还有P型GaN层，由此可以极大提高器件的阈值电压。有利于解决GaN增强型器件在实际应用中的可靠性问题，扩宽了其在功率开关领域的应用。

Figure 201811422595

The invention discloses a novel epitaxial layer structure for improving the threshold voltage of a GaN enhanced MOSFET and a device preparation method based on the structure, and relates to the fields of power electronic devices and power switches. The new structure includes from bottom to top: substrate, GaN buffer layer, intrinsic GaN layer, Mg-doped P-type GaN layer, GaN channel layer and AlGaN barrier layer. On the structure, a passivation layer, a groove gate, a plane isolation, an insulating gate dielectric layer, an ohmic contact, and a gate and source-drain ohmic metal electrodes are formed by a groove gate process to prepare a high threshold voltage enhancement mode GaN MOSFET. In the present invention, a P-type GaN layer is inserted into the intrinsic GaN layer, and after it is completely etched, the channel inversion region has a P-type GaN layer in addition to the intrinsic GaN layer, thereby greatly improving the threshold voltage of the device. It is beneficial to solve the reliability problem of the GaN enhancement type device in practical application, and broaden its application in the field of power switch.

Figure 201811422595

Description

Novel epitaxial layer structure for improving threshold voltage of GaN enhanced MOSFET
Technical Field
The invention belongs to the technical field of microelectronics, and relates to the field of power electronic devices and power switches based on compound semiconductor materials.
Background
The wide-bandgap semiconductor GaN is considered to be a very important field of next-generation high-efficiency power switch because of its outstanding material properties, such as high breakdown field strength, high electron saturation mobility and the likePromising competitors. In addition, due to the extremely strong spontaneous polarization effect, a concentration as high as 10 naturally exists at the conventional AlGaN/GaN heterojunction interface13cm-2The mobility of the 2DEG can reach 2000cm2The advantage of/V.S is that the GaN power electronic device based on the AlGaN/GaN heterojunction can have faster switching speed, but at the same time, the conventional heterojunction high mobility transistor (HEMT) is a depletion mode device, namely, the device is in a normal open state and the threshold voltage of the device is a negative value under zero gate voltage. In practical applications, however, enhancement mode devices are indispensable for safe operation of power electronic systems in order to ensure that the devices have operating currents only when biased with a positive gate voltage. Therefore, many researchers at home and abroad are working on realizing the high-performance enhanced GaN HEMT.
At present, two ways are mainly used for realizing enhancement operation of a GaN-based device, namely, a low-voltage enhancement type silicon-based MOSFET and a high-voltage depletion type GaN device are integrated and packaged into a system capable of realizing enhancement operation by adopting a cascode structure; and the other is that an enhanced high-voltage GaN power device is directly adopted. The cascode structure has the advantages that the cascode structure is mainly controlled on a silicon-based MOSFET, and the grid of the GaN-based device is not directly controlled, so that the system has no working current when in zero bias, and can be quickly opened by utilizing the normally-open GaN-based device when in forward bias above threshold voltage. After all, the grid control does not directly act on the GaN-based device, the conversion efficiency control of the power switch is not good, and this will greatly affect the safe operation of the system and the ripple noise, so the high-voltage enhanced GaN power device with direct grid control still needs to be necessary.
The enhanced GaN power device is mainly realized by the following two methods: 1. a P-Type GaN layer grows on the surface of an AlGaN/GaN heterojunction, and the thickness and doping of the P-Type GaN layer are reasonably designed to effectively exhaust 2DEG at a heterojunction interface, so that a normally-off GaN power device is realized. 2. The thickness of the AlGaN layer in the gate region is reduced, inherent positive polarization charges under the gate are eliminated, and the 2DEG at the heterojunction interface is exhausted, so that the normally-off GaN power device is realized.
Disclosure of Invention
In order to overcome the defects of the method 2 for realizing the enhanced GaN power device technology, the invention provides a novel epitaxial layer structure by focusing on the design of the AlGaN/GaN heterojunction epitaxial layer structure, and the AlGaN barrier layer is removed by adopting a traditional dry etching process which is simple and easy to realize, so that the enhanced GaN power device with positive threshold voltage can be prepared.
The novel epitaxial layer structure provided by the invention comprises from bottom to top: a substrate, a GaN buffer layer, an intrinsic GaN layer, a Mg doped P-type GaN layer, an intrinsic GaN channel layer, and an intrinsic AlGaN barrier layer, as shown in fig. 1. This novel epitaxial layer structure has inserted one deck Mg in the intrinsic GaN layer of 2DEG below and has doped P type GaN layer, adopt traditional bars groove etching process, the bars below sculpture is below P-type GaN layer, form the channel of bars below, compare the channel that forms behind traditional epitaxial layer structure removal AlGaN barrier layer, the P-type GaN channel of both sides has been had more in this structure, that is to say, the device is opened completely, not only need the inversion on intrinsic GaN layer, still need the inversion of P-type GaN channel, the threshold voltage of device will be bigger than the enhancement mode device that traditional epitaxial layer structure prepared from this.
According to the technical thought, the simple MOS gate trench type device (as shown in figure 2) based on the novel epitaxial layer structure is subjected to simulation verification by means of a sentourus TCAD simulation tool, the obtained device transfer characteristic is shown in figure 3, and the threshold voltage is about 5V (linear extrapolation extraction), so that the gate trench type device is greatly improved compared with the gate trench type device under the traditional structure, and the feasibility of the invention is verified through preliminary simulation verification. In order to realize the growth of the novel epitaxial layer and ensure the performance of the device, the thickness and doping concentration of the inserted P-type GaN layer need to be reasonably designed, and in addition, the distance between the P-type GaN layer and the GaN channel layer needs to be reasonably designed in order to avoid the influence of the P-type GaN on the GaN channel layer. The influence of the above items is comprehensively considered, and the key layer-by-layer composition and material types of the novel epitaxial layer structure are as follows:
the substrate material is one of the following materials: si, SiC, sapphire.
The doping concentration of the Mg-doped P-type GaN layer is as follows: 5E 16-2E 18cm-3。
The thickness of the Mg-doped P-type GaN layer is 50 nm-300 nm. .
The thickness of the intrinsic GaN channel layer on the Mg-doped P-type GaN layer is as follows: 100nm to 300 nm.
The invention provides a simple and easy-to-realize technological method based on the GaN novel epitaxial layer structure to prepare a GaN enhanced MOSFET, which comprises the following steps:
(1) growing a GaN buffer layer, an intrinsic GaN layer, a Mg-doped P-type GaN layer, an intrinsic GaN channel layer and an intrinsic AlGaN barrier layer on the substrate in sequence;
(2) growing a medium passivation layer on the AlGaN barrier layer by PECVD, ICPCVD or LPCVD;
(3) photoetching a grid pattern, firstly etching the medium passivation layer, then etching the GaN layer until the P-type GaN layer is completely etched, and etching the GaN layer at the temperature of 650-800 ℃ and N2Annealing for 15 minutes in protective gas to activate the P-type GaN;
(4) photoetching and etching (or ion implantation) are carried out on the GaN wafer of the P-type GaN at the position of the annealing activation channel to form an active region table board;
(5) photoetching a GaN wafer with a prepared active region table board, etching a source-drain ohmic electrode region, preparing a plurality of layers of metal through electron beam evaporation or magnetron sputtering to form a source electrode and a drain electrode, and annealing in protective gas at 800-900 ℃ for 30 seconds to form ohmic contact;
(6) after ohmic contact is formed, putting the wafer into atomic layer deposition equipment, growing an insulated gate dielectric layer on the surface of the wafer, then photoetching a source and drain region ohmic contact hole, and removing the insulated gate dielectric layer to expose the source and drain ohmic contact;
(7) and photoetching a gate electrode area, growing a gate electrode material by using electron beam evaporation or magnetron sputtering, then carrying out stripping process treatment on the device to form a gate electrode, and finally carrying out annealing treatment on the whole wafer in a nitrogen environment to finish the preparation of the whole device.
The material of the medium passivation layer in the above process method may be any one of the following materials: si3N4、SiO2、SiON。
In the above process, the source and the drain are: alloys of one or more of titanium, aluminum, nickel, gold, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, tungsten, and the like.
In the above process, the insulated gate dielectric layer is any one of the following materials: si3N4、Al2O3、AlN、HfO2、SiO2、HfTiO、Sc2O3、Ga2O3、MgO、SiNO。
The gate metal in the above process is a combination of one or more of the following conductive materials: platinum, iridium, nickel, gold, molybdenum, palladium, selenium, beryllium, TiN, polysilicon, ITO.
The invention has the advantages that from the material structure design angle of the compound semiconductor, a novel AlGaN/GaN heterojunction structure is provided, an enhanced device with larger threshold voltage can be realized on the structure by the simplest grid groove etching process, and the absolute turn-off state of the device under zero bias is ensured, so that the problem of the related reliability of the GaN device in practical application is hopefully solved.
Drawings
The figures will illustrate in more detail the novel epitaxial layer structure proposed by the present invention and an example of the fabrication of a GaN enhancement device based on this epitaxial layer structure. The drawings illustrate the following:
FIG. 1 is a schematic structural diagram of a cross section of a novel epitaxial layer structure proposed by the present invention;
fig. 2 is a schematic cross-sectional structure diagram (simulation structure of a sentaurus TCAD device) of a simple MOS gate trench GaN enhancement device based on the novel epitaxial layer structure;
FIG. 3 is a device transfer characteristic curve obtained by computer simulation of the device structure of FIG. 2 using sentaurus TCAD simulation software;
fig. 4 to 9 are schematic cross-sectional views of devices after each step of manufacturing a gate trench type GaN enhancement mode device based on the epitaxial layer structure provided by the present invention, and reflect an embodiment of the present invention.
Detailed Description
Hereinafter, the fabrication of a gate trench type GaN enhancement device based on the novel epitaxial layer structure proposed by the present invention will be described in detail with reference to the accompanying drawings, so that the specific implementation method, process flow and core technical points of the present invention can be more clearly understood. This example is only one implementation of the present invention, i.e., the proposed structure of the present invention should not be limited to the examples set forth herein. The scope of the invention is fully conveyed to those skilled in the art based on this example.
Fig. 1 shows a novel epitaxial layer structure provided by the present invention, which comprises a substrate, a GaN buffer layer, an intrinsic GaN layer, a Mg-doped P-type GaN layer, an intrinsic GaN channel layer, and an intrinsic AlGaN barrier layer from bottom to top. One specific implementation example of the GaN enhancement device fabrication by the gate trench etch process based on this structure includes the following specific steps:
(1) growing a layer of Si on the AlGaN/GaN heterojunction structure wafer shown in the attached figure 1 by PECVD, ICPCVD or LPCVD3N4A passivation layer for improving the reliability of the final device, wherein the cross-sectional view of the structure is shown in FIG. 4;
(2) on the basis of the structure shown in FIG. 4, first, Si in the gate trench region is removed by RIE etching machine3N4Removing GaN in the gate groove region by an ICP etching machine, etching the lower part of the gate to be below the P-type GaN layer to form a channel below the gate, and finally performing N treatment at 650-800 deg.C2Annealing in protective gas for 15 min to activate P-type GaN, and forming a structural cross-sectional view as shown in FIG. 5;
(3) forming an active region, and photoetching and etching (or ion implantation) the GaN wafer of the P-type GaN at the position of the annealed activation channel to form an active region table board;
(4) then, photoetching source-drain ohmic pattern in the active region, and removing Si covering the source-drain ohmic pattern by using RIE etcher3N4Then evaporating Ti/Al/Ni/Au four metals by electron beams, preparing a source-drain ohmic metal electrode by adopting a stripping process, and finally performing rapid annealing for 30 seconds in a nitrogen atmosphere at 870 ℃ to form ohmic contact, wherein the schematic sectional structure diagram is shown in figure 6;
(5) on the basis of the step (4), Al grows on the surface of the wafer2O3An insulated gate dielectric layer forming the structure shown in fig. 7;
(6) removing Al covering the source-drain ohmic contact by wet etching based on the structure shown in FIG. 72O3(as shown in fig. 8), then, growing Ni/Au alloy in the gate area by electron beam evaporation, and then continuing to form a gate metal electrode by using a stripping process to form a T-shaped gate structure, as shown in fig. 9. Finally in N2Annealing the whole wafer in the atmosphere, and annealing at 400 ℃ for 10 min.
(7) Compared with a conventional enhanced device, the enhanced GaN MOSHEMT prepared by the process steps has larger threshold voltage and can ensure the absolute off state degree under zero bias.

Claims (11)

1.一种提高GaN增强型MOSFET阈值电压的新型外延层结构，自下而上包括：衬底、GaN缓冲层、本征GaN层、Mg掺杂P型GaN层、本征GaN沟道层以及本征AlGaN势垒层。在该新型外延层结构上用最传统的凹槽栅工艺形成钝化层、凹槽栅、平面隔离、绝缘栅介质层、欧姆接触以及栅和源漏欧姆金属电极即可形成高阈值电压的增强型GaN MOSFET。1. A novel epitaxial layer structure for improving the threshold voltage of GaN enhancement mode MOSFET, comprising from bottom to top: substrate, GaN buffer layer, intrinsic GaN layer, Mg-doped P-type GaN layer, intrinsic GaN channel layer and Intrinsic AlGaN barrier layer. On the new epitaxial layer structure, the most traditional groove gate process is used to form passivation layer, groove gate, plane isolation, insulating gate dielectric layer, ohmic contact and gate and source-drain ohmic metal electrodes to form the enhancement of high threshold voltage type GaN MOSFETs. 2.根据权利要求1所述的提高GaN增强型MOSFET阈值电压的新型外延层结构，其特征在于：其中的衬底材料为Si、SiC、蓝宝石。2 . The novel epitaxial layer structure for increasing the threshold voltage of GaN enhancement mode MOSFET according to claim 1 , wherein the substrate material is Si, SiC, or sapphire. 3 . 3.根据权利要求1所述的提高GaN增强型MOSFET阈值电压的新型外延层结构，其特征在于：所述Mg掺杂P型GaN层掺杂浓度为：5E16～2E18cm-3。3 . The novel epitaxial layer structure for increasing the threshold voltage of GaN enhancement mode MOSFET according to claim 1 , wherein the doping concentration of the Mg-doped P-type GaN layer is 5E16˜2E18 cm −3 . 4 . 4.根据权利要求1所述的提高GaN增强型MOSFET阈值电压的新型外延层结构，其特征在于：所述Mg掺杂P型GaN层厚度为：50nm～300nm。4 . The novel epitaxial layer structure for increasing the threshold voltage of GaN enhancement mode MOSFET according to claim 1 , wherein the thickness of the Mg-doped P-type GaN layer is 50 nm to 300 nm. 5 . 5.根据权利要求1所述的提高GaN增强型MOSFET阈值电压的新型外延层结构，其特征在于：所述Mg掺杂P型GaN层上面的本征GaN沟道层厚度为：100nm～300nm。5 . The novel epitaxial layer structure for increasing the threshold voltage of GaN enhancement mode MOSFET according to claim 1 , wherein the thickness of the intrinsic GaN channel layer on the Mg-doped P-type GaN layer is 100 nm to 300 nm. 6 . 6.根据权利要求1所述的提高GaN增强型MOSFET阈值电压的新型外延层结构，在其上用凹槽栅工艺形成的增强新GaN MOSFET，其特征在于：所述介质钝化层的材料为以下材料中的任意一种：Si3N4、AlN、Al2O3、SiO2。6. The novel epitaxial layer structure of improving the threshold voltage of GaN enhanced MOSFET according to claim 1, the enhanced new GaN MOSFET formed by groove gate technology on it, is characterized in that: the material of the dielectric passivation layer is Any of the following materials: Si 3 N 4 , AlN, Al 2 O 3 , SiO 2 . 7.根据权利要求1所述的提高GaN增强型MOSFET阈值电压的新型外延层结构，在其上用凹槽栅工艺形成的增强新GaN MOSFET，其特征在于：凹槽栅的形成方法为以下方法中的任意一种：ICP刻蚀、湿法腐蚀。7. the novel epitaxial layer structure of improving the threshold voltage of GaN enhancement mode MOSFET according to claim 1, the enhanced new GaN MOSFET formed by groove gate technology on it, it is characterized in that: the formation method of groove gate is following method Any one of: ICP etching, wet etching. 8.根据权利要求1所述的提高GaN增强型MOSFET阈值电压的新型外延层结构，在其上用凹槽栅工艺形成的增强新GaN MOSFET，其特征在于：在650℃～800℃之间于N2保护气体中退火15分钟，激活P-type GaN。8. The novel epitaxial layer structure for improving the threshold voltage of GaN enhancement mode MOSFET according to claim 1, and the enhanced new GaN MOSFET formed by groove gate technology on it, characterized in that: between 650°C and 800°C Annealing in N2 protective gas for 15 minutes activates P-type GaN. 9.根据权利要求1所述的提高GaN增强型MOSFET阈值电压的新型外延层结构，在其上用凹槽栅工艺形成的增强新GaN MOSFET，其特征在于：所述绝缘栅介质层为以下材料中的任意一种：Si3N4、Al2O3、AlN、HfO2、SiO2、HfTiO、Sc2O3、Ga2O3、MgO、SiNO。9. The novel epitaxial layer structure of improving the threshold voltage of GaN enhancement mode MOSFET according to claim 1, the enhanced new GaN MOSFET formed by groove gate technology on it, is characterized in that: the insulating gate dielectric layer is the following material Any one of: Si 3 N 4 , Al 2 O 3 , AlN, HfO 2 , SiO 2 , HfTiO, Sc 2 O 3 , Ga 2 O 3 , MgO, SiNO. 10.根据权利要求1所述的提高GaN增强型MOSFET阈值电压的新型外延层结构，在其上用凹槽栅工艺形成的增强新GaN MOSFET，其特征在于：所述源极和漏极为：钛、铝、镍、金、铂、铱、钼、钽、铌、钴、锆、钨等中的一种或多种的合金。10. The novel epitaxial layer structure for improving the threshold voltage of GaN enhancement mode MOSFET according to claim 1, and the enhanced new GaN MOSFET formed by groove gate technology on it, characterized in that: the source electrode and the drain electrode are: titanium , an alloy of one or more of aluminum, nickel, gold, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, tungsten, etc. 11.根据权利要求1所述的提高GaN增强型MOSFET阈值电压的新型外延层结构，在其上用凹槽栅工艺形成的增强新GaN MOSFET，其特征在于：所述栅极金属为以下导电材料的一种或多种的组合：铂、铱、镍、金、钼、钯、硒、铍、TiN、多晶硅、ITO。11. The novel epitaxial layer structure for improving the threshold voltage of GaN enhancement mode MOSFET according to claim 1, the enhanced new GaN MOSFET formed by groove gate technology on it, is characterized in that: the gate metal is the following conductive material A combination of one or more of: platinum, iridium, nickel, gold, molybdenum, palladium, selenium, beryllium, TiN, polysilicon, ITO.
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FR3111473A1 (en) * 2020-06-16 2021-12-17 Commissariat A L'energie Atomique Et Aux Energies Alternatives Transistor
CN114628513A (en) * 2021-11-04 2022-06-14 中国科学院微电子研究所 Gallium nitride device based on medium patterning technology and preparation method thereof
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