CN106531789A - Method for achieving enhanced HEMT through polarity control and enhanced HEMT - Google Patents
Method for achieving enhanced HEMT through polarity control and enhanced HEMT Download PDFInfo
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
- H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
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- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
- H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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Abstract
本发明公开了一种增强型HEMT,包括主要由第一、第二半导体层组成的异质结构和与异质结构连接的源、漏、栅电极;该源、漏电极通过形成于异质结构中的二维电子气电连接,该栅电极分布于源、漏电极之间;分布于栅电极正下方的第一、第二半导体层的局部区域的组成材料均具有设定极性,使得当在栅电极施加零偏压或者没有施加偏压时,于栅电极正下方的异质结构局部区域内无二维电子气的积累,而当在栅电极电压大于阈值电压时,能够于栅电极正下方的异质结构局部区域内形成二维电子气。本发明还公开一种通过极性控制实现增强型HEMT的方法。本发明具有工艺简单,重复性高,器件性能稳定优良,成本低廉,易于进行大规模生产等优点。
The invention discloses an enhanced HEMT, comprising a heterostructure mainly composed of first and second semiconductor layers and source, drain and gate electrodes connected to the heterostructure; the source and drain electrodes are formed on the heterostructure The two-dimensional electrons in the gas-electric connection, the gate electrode is distributed between the source and drain electrodes; the constituent materials of the local regions of the first and second semiconductor layers distributed directly below the gate electrode have a set polarity, so that when When zero bias or no bias is applied to the gate electrode, there is no accumulation of two-dimensional electron gas in the local region of the heterostructure directly below the gate electrode, and when the gate electrode voltage is greater than the threshold voltage, it can A two-dimensional electron gas forms in the local region of the underlying heterostructure. The invention also discloses a method for realizing enhanced HEMT through polarity control. The invention has the advantages of simple process, high repeatability, stable and excellent device performance, low cost, easy mass production and the like.
Description
技术领域technical field
本发明涉及一种增强型HEMT(high electron mobility transistor)器件及其制备方法,特别涉及一种通过调控栅电极下方所生长的半导体材料的极性,利用极化电场的改变实现增强HEMT器件的方法,属于微电子工艺领域。The present invention relates to an enhanced HEMT (high electron mobility transistor) device and a preparation method thereof, in particular to a method for realizing an enhanced HEMT device by adjusting the polarity of a semiconductor material grown under a gate electrode and utilizing a change in a polarization electric field , belonging to the field of microelectronic technology.
背景技术Background technique
HEMT器件是充分利用半导体的异质结构(Heterostructure)结构形成的二维电子气而制成的,与Ⅲ-Ⅵ族(如AlGaAs/GaAs HEMT)相比,Ⅲ族氮化物半导体由于压电极化和自发极化效应,在异质结构(如AlGaN/GaN)中能够形成高浓度的二维电子气。所以在使用Ⅲ族氮化物制成的HEMT器件中,势垒层一般不需要进行掺杂。同时,Ⅲ族氮化物具有大的禁带宽度、较高的饱和电子漂移速度、高的临界击穿电场和极强的抗辐射能力等特点,能够满下一代电力电子系统对功率器件更大功率、更高频率、更小体积和更高温度的工作的要求。HEMT devices are made by making full use of the two-dimensional electron gas formed by the semiconductor heterostructure (Heterostructure) structure. Compared with III-VI (such as AlGaAs/GaAs HEMT), III-nitride semiconductors are due to piezoelectric polarization And the spontaneous polarization effect, a high-concentration two-dimensional electron gas can be formed in the heterostructure (such as AlGaN/GaN). Therefore, in HEMT devices made of group III nitrides, the barrier layer generally does not need to be doped. At the same time, group III nitrides have the characteristics of large band gap, high saturated electron drift velocity, high critical breakdown electric field and strong radiation resistance, which can meet the requirements of the next generation power electronic system for higher power devices. , higher frequency, smaller volume and higher temperature requirements.
现有的Ⅲ族氮化物半导体HEMT器件作为高频器件或者高压大功率开关器件使用时,特别是作为功率开关器件时,增强型HEMT器件与耗尽型HEMT器件相比更有助于提高系统的安全性、降低器件的损耗和简化设计电路。目前实现增强型HEMT主要的方法有薄的势垒层、凹栅结构、P型盖帽层和F处理等技术,但这些技术都存在不足。例如,薄的势垒层技术不需使用刻蚀工艺,所以带来的损伤小,但是由于较薄的势垒层,器件的饱和电流较小。又例如,F等离子处理也能实现增强型HEMT器件,并且不需要刻蚀,但是F的等离子体在注入的过程中也会刻蚀势垒层,造成器件性能的降低。When the existing group III nitride semiconductor HEMT devices are used as high-frequency devices or high-voltage high-power switching devices, especially as power switching devices, the enhancement mode HEMT device is more helpful to improve the system performance than the depletion mode HEMT device. Safety, reduce device loss and simplify circuit design. At present, the main methods for realizing enhanced HEMT include thin barrier layer, concave gate structure, P-type capping layer and F treatment, etc., but these technologies all have deficiencies. For example, the thin barrier layer technology does not need to use an etching process, so the damage caused is small, but due to the thinner barrier layer, the saturation current of the device is smaller. For another example, F plasma treatment can also realize an enhanced HEMT device, and does not require etching, but F plasma will also etch the barrier layer during the implantation process, resulting in a decrease in device performance.
因而,业界亟待发展出一种易于实施,重复性好,且能有效保证器件性能的增强型HEMT器件的实现方法。Therefore, the industry urgently needs to develop an implementation method of an enhanced HEMT device that is easy to implement, has good repeatability, and can effectively guarantee device performance.
发明内容Contents of the invention
针对现有技术的不足,本发明的主要目的在于提出一种通过极性控制实现增强型HEMT的方法及增强型HEMT。Aiming at the deficiencies of the prior art, the main purpose of the present invention is to provide a method for realizing an enhanced HEMT through polarity control and the enhanced HEMT.
为实现前述发明目的,本发明采用的技术方案包括:In order to realize the aforementioned object of the invention, the technical solutions adopted in the present invention include:
在一些实施例中提供了一种增强型HEMT,包括:主要由作为沟道层的第一半导体层和作为势垒层的第二半导体层组成的异质结构,以及,与所述异质结构连接的源、漏、栅电极;所述源、漏电极通过形成于异质结构中的二维电子气电连接,所述栅电极分布于源、漏电极之间;其中,分布于栅电极正下方的第一半导体层的局部区域的组成材料及第二半导体层的局部区域的组成材料均具有设定极性,使得当在所述栅电极施加零偏压或者没有施加偏压时,于所述栅电极正下方的异质结构局部区域内无二维电子气的积累,而当在所述栅电极电压大于阈值电压时,能够于所述栅电极正下方的异质结构局部区域内形成二维电子气。In some embodiments, an enhanced HEMT is provided, comprising: a heterostructure mainly composed of a first semiconductor layer as a channel layer and a second semiconductor layer as a barrier layer, and, with the heterostructure Connected source, drain, and gate electrodes; the source and drain electrodes are electrically connected through two-dimensional electrons formed in the heterogeneous structure, and the gate electrodes are distributed between the source and drain electrodes; The constituent materials of the partial region of the first semiconductor layer below and the constituent materials of the partial region of the second semiconductor layer all have a set polarity, so that when zero bias voltage or no bias voltage is applied to the gate electrode, There is no accumulation of two-dimensional electron gas in the local region of the heterostructure directly below the gate electrode, and when the voltage of the gate electrode is greater than the threshold voltage, a two-dimensional electron gas can be formed in the local region of the heterostructure directly below the gate electrode. Dimensional electron gas.
在一些实施例中,分布于栅电极正下方的第一半导体层的局部区域的组成材料及第二半导体层的局部区域的组成材料的极性均与第一半导体层内其余区域的组成材料及第二半导体层内其余区域的组成材料的极性相反。In some embodiments, the polarities of the constituent materials of the partial regions of the first semiconductor layer and the constituent materials of the partial regions of the second semiconductor layer distributed directly under the gate electrode are the same as those of the constituent materials and the constituent materials of the remaining regions in the first semiconductor layer. The polarity of the constituent materials of the remaining regions within the second semiconductor layer is reversed.
在一些实施例中提供了一种通过极性控制实现增强型HEMT的方法,其包括:In some embodiments there is provided a method of implementing an enhanced HEMT through polarity control, comprising:
在衬底上依次生长主要由作为沟道层的第一半导体层和作为势垒层的第二半导体层组成的异质结构,且使分布于栅电极正下方的第一半导体层的局部区域的组成材料及第二半导体层的局部区域的组成材料均具有设定极性,从而使得当在所述栅电极施加零偏压或者没有施加偏压时,于所述栅电极正下方的异质结构局部区域内无二维电子气的积累,而当在所述栅电极电压大于阈值电压时,能够于所述栅电极正下方的异质结构局部区域内形成二维电子气;A heterostructure mainly composed of a first semiconductor layer as a channel layer and a second semiconductor layer as a barrier layer is sequentially grown on the substrate, and the local area of the first semiconductor layer distributed directly under the gate electrode is made Both the constituent material and the constituent material of the partial region of the second semiconductor layer have a set polarity, so that when zero bias voltage or no bias voltage is applied to the gate electrode, the heterostructure directly below the gate electrode There is no accumulation of two-dimensional electron gas in the local area, and when the voltage of the gate electrode is greater than the threshold voltage, two-dimensional electron gas can be formed in the local area of the heterostructure directly below the gate electrode;
以及,制作源、漏、栅电极,并使所述源、漏电极能够通过形成于所述异质结构中的二维电子气电连接,且使所述栅电极分布于源、漏电极之间。And, making source, drain, and gate electrodes, and enabling the source and drain electrodes to be electrically connected through the two-dimensional electron gas formed in the heterostructure, and distributing the gate electrodes between the source and drain electrodes .
与现有技术相比,本发明的优点包括:通过在材料生长过程中控制材料的极性而实现了增强型HEMT器件(例如增强型GaN基HEMT器件),优选的,其中材料极性的控制是通过对衬底进行图形化处理而实现,其可有效的保证异质结构处材料的晶体质量,从而使器件的整体性能不受到或者受到较小的影响,并且在实现增强型HEMT的过程中没有引入等离子体的刻蚀,较小了器件的损伤,具有工艺简单,重复性高,成本低廉,易于进行大规模生产等特点。Compared with the prior art, the advantages of the present invention include: an enhanced HEMT device (such as an enhanced GaN-based HEMT device) is realized by controlling the polarity of the material during the material growth process, preferably, wherein the control of the polarity of the material It is realized by patterning the substrate, which can effectively ensure the crystal quality of the material at the heterostructure, so that the overall performance of the device is not or slightly affected, and in the process of realizing the enhanced HEMT Etching without introducing plasma reduces device damage, and has the characteristics of simple process, high repeatability, low cost, and easy mass production.
附图说明Description of drawings
图1是普通耗尽型GaN HEMT器件的局部结构示意图;Figure 1 is a schematic diagram of the local structure of a common depletion-mode GaN HEMT device;
图2是普通增强型GaN HEMT器件的局部结构示意图;Figure 2 is a schematic diagram of a local structure of a common enhancement mode GaN HEMT device;
图3是本发明一典型实施方案采用极性控制实现增强型HEMT的结构示意图;Fig. 3 is a schematic structural diagram of a typical implementation of the present invention using polarity control to realize enhanced HEMT;
图4是本发明一典型实施方案采用极性控制实现增强型MISHEMT的结构示意图;Fig. 4 is a schematic structural diagram of a typical embodiment of the present invention adopting polarity control to realize enhanced MISHEMT;
图5是本发明一典型实施方案采用极性控制实现增强型HEMT的能带示意图;Fig. 5 is a schematic diagram of the energy band of an enhanced HEMT realized by using polarity control in a typical embodiment of the present invention;
附图标记说明:衬底1、氮化镓2、氮化铝3、势垒层4、源电极5、漏电极6、二维电子气7、栅电极8、种子层9、氮极性区域10、栅介质11。Description of reference numerals: substrate 1, gallium nitride 2, aluminum nitride 3, barrier layer 4, source electrode 5, drain electrode 6, two-dimensional electron gas 7, gate electrode 8, seed layer 9, nitrogen polar region 10. Gate dielectric 11.
具体实施方式detailed description
下文将对本发明的技术方案作更为详尽的解释说明。但是,应当理解,在本发明范围内,本发明的上述各技术特征和在下文(如实施例)中具体描述的各技术特征之间都可以互相组合,从而构成新的或优选的技术方案。限于篇幅,在此不再一一累述。The technical solution of the present invention will be explained in more detail below. However, it should be understood that within the scope of the present invention, the above-mentioned technical features of the present invention and the technical features specifically described in the following (such as embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, we will not repeat them here.
本发明的一个方面涉及了一种增强型HEMT。在一些实施例中,所述增强型HEMT包括:主要由作为沟道层的第一半导体层和作为势垒层的第二半导体层组成的异质结构,以及,与所述异质结构连接的源、漏、栅电极;所述源、漏电极通过形成于异质结构中的二维电子气电连接,所述栅电极分布于源、漏电极之间。其中,分布于栅电极正下方的第一半导体层的局部区域的组成材料及第二半导体层的局部区域的组成材料均具有设定极性,使得当在所述栅电极施加零偏压或者没有施加偏压时,于所述栅电极正下方的异质结构局部区域内无二维电子气的积累,而当在所述栅电极电压大于阈值电压时,能够于所述栅电极正下方的异质结构局部区域内形成二维电子气。One aspect of the invention relates to an enhanced HEMT. In some embodiments, the enhanced HEMT includes: a heterostructure mainly composed of a first semiconductor layer serving as a channel layer and a second semiconductor layer serving as a barrier layer, and a Source, drain, and gate electrodes; the source and drain electrodes are electrically connected through two-dimensional electrons formed in the heterostructure, and the gate electrode is distributed between the source and drain electrodes. Wherein, the constituent materials of the partial region of the first semiconductor layer and the constituent materials of the partial region of the second semiconductor layer distributed directly under the gate electrode all have a set polarity, so that when zero bias is applied to the gate electrode or there is no When a bias voltage is applied, there is no accumulation of two-dimensional electron gas in the local region of the heterostructure directly below the gate electrode, and when the voltage of the gate electrode is greater than the threshold voltage, the heterostructure directly below the gate electrode can A two-dimensional electron gas is formed in the local region of the material structure.
需说明的是,前述的“栅电极下方”主要是指栅电极在异质结构上正投影所覆盖的区域。It should be noted that the aforementioned "below the gate electrode" mainly refers to the area covered by the orthographic projection of the gate electrode on the heterostructure.
在一些实施例中,分布于栅电极正下方的第一半导体层的局部区域的组成材料及第二半导体层的局部区域的组成材料的极性均与第一半导体层内其余区域的组成材料及第二半导体层内其余区域的组成材料的极性相反。In some embodiments, the polarities of the constituent materials of the partial regions of the first semiconductor layer and the constituent materials of the partial regions of the second semiconductor layer distributed directly under the gate electrode are the same as those of the constituent materials and the constituent materials of the remaining regions in the first semiconductor layer. The polarity of the constituent materials of the remaining regions within the second semiconductor layer is reversed.
在一些实施例中,于所述栅电极与所述异质结构之间还分布有栅介质层,即形成增强型MIS(metal-insulator-semiconductor)HEMT结构。In some embodiments, a gate dielectric layer is distributed between the gate electrode and the heterostructure, that is, an enhanced MIS (metal-insulator-semiconductor) HEMT structure is formed.
在一些较为具体的实施例中,所述增强型HEMT可以包括:主要由GaN层和AlxGa(1-x)N(0<x≤1)层组成的异质结构,以及,与所述异质结构连接的源、漏、栅电极;所述源、漏电极分布在AlxGa(1-x)N层上,并且通过形成于异质结构中的二维电子气电连接,栅电极设于源、漏电极之间;分布于栅电极正下方的GaN层的局部区域的组成材料和AlxGa(1-x)N层的局部区域的组成材料均为N性极化材料,而所述GaN层内其余区域的组成材料及所述AlxGa(1-x)N层内其余区域的组成材料均为Ga性极化材料。In some more specific embodiments, the enhanced HEMT may include: a heterostructure mainly composed of a GaN layer and an AlxGa (1-x) N (0<x≤1) layer, and, with the The source, drain, and gate electrodes connected by the heterostructure; the source and drain electrodes are distributed on the AlxGa (1-x) N layer, and are electrically connected through the two-dimensional electron gas formed in the heterostructure, and the gate electrode It is arranged between the source and drain electrodes; the constituent materials of the local area of the GaN layer distributed directly below the gate electrode and the constituent materials of the local area of the Al x Ga (1-x) N layer are all N polarized materials, and The constituent materials of the remaining regions in the GaN layer and the constituent materials of the remaining regions in the Al x Ga (1-x) N layer are all Ga polarized materials.
在一些实施例中,所述源、漏电极位于AlxGa(1-x)N层表面并且通过欧姆接触与所述二维电子气电连接。In some embodiments, the source and drain electrodes are located on the surface of the AlxGa (1-x) N layer and are electrically connected to the two-dimensional electrons through an ohmic contact.
在一些实施例中,分布于所述栅电极下方的半导体材料(尤其是组成所述异质结构的半导体材料)的极性与分布于栅电极下方以外的区域的半导体材料极性相反。In some embodiments, the polarity of the semiconductor material distributed under the gate electrode (especially the semiconductor material constituting the heterostructure) is opposite to the polarity of the semiconductor material distributed in regions other than under the gate electrode.
在一些实施例中,当栅电极是零偏压时,所述HEMT栅下的材料极性为氮极性,二维电子气无法形成,器件处于断开状态,而当在栅电极加正向电压时,所述HEMT在栅电极下端积累电子,器件处于处于开启状态。In some embodiments, when the gate electrode is at zero bias, the polarity of the material under the HEMT gate is nitrogen polarity, the two-dimensional electron gas cannot be formed, and the device is in an off state. When the voltage is high, the HEMT accumulates electrons at the lower end of the gate electrode, and the device is in an on state.
在一些实施例中,在所述HEMT工作时,所述源电极和漏电极分别与电源的低电位和高电位连接。In some embodiments, when the HEMT is working, the source electrode and the drain electrode are respectively connected to the low potential and the high potential of the power supply.
在一些实施例中,于形成异质结构第一、第二半导体层之间还可设有插入层等,其材质可以是AlN等,但不限于此。In some embodiments, an insertion layer or the like may be provided between the first and second semiconductor layers forming the heterostructure, and its material may be AlN, etc., but not limited thereto.
在一些较为典型的具体实施例中,一种增强型HEMT的异质结构主要由GaN/AlxGa(1-x)N(0<x≤1)组成,源、漏电极位于AlxGa(1-x)N表面并且通过欧姆接触与二维电子气相连接,栅电极设于源、漏电极之间,并且栅电极下方的GaN和AlxGa(1-x)N材料为N面材料,在此区域内,由于材料极性的改变,在材料内部产生的极化电场方向发生改变,在异质结构处无法形成电子的积累,而在栅电极以外的区域,材料为镓性极化,所以在异质结构界面处会产生二维电子气。因此,可以实现HEMT器件在零栅偏压的时候处于关断状态,达到由常开型HEMT器件向常关型HEMT器件的转变。In some more typical specific embodiments, the heterostructure of an enhanced HEMT is mainly composed of GaN/Al x Ga (1-x) N (0<x≤1), and the source and drain electrodes are located on Al x Ga ( 1-x) The N surface is connected to the two-dimensional electron gas phase through an ohmic contact, the gate electrode is arranged between the source and drain electrodes, and the GaN and Al x Ga (1-x) N materials below the gate electrode are N-face materials, In this area, due to the change of the polarity of the material, the direction of the polarization electric field generated inside the material changes, and the accumulation of electrons cannot be formed at the heterostructure, while in the area outside the gate electrode, the material is gallium polarized, Therefore, a two-dimensional electron gas will be generated at the interface of the heterostructure. Therefore, it is possible to realize that the HEMT device is in an off state when the gate bias voltage is zero, thereby achieving the transition from a normally-on HEMT device to a normally-off HEMT device.
前述的GaN/AlxGa(1-x)N(0<x≤1)异质结结构也可替换为GaN/InAlN等异质结构,或业界所知的其它适用的异质结构。The aforementioned GaN/ AlxGa (1-x) N (0<x≤1) heterojunction structure can also be replaced by a heterostructure such as GaN/InAlN, or other suitable heterostructures known in the industry.
本发明的一个方面还提供了一种通过极性控制实现增强型HEMT的方法。在一些实施例中,所述方法包括:An aspect of the present invention also provides a method for realizing an enhanced HEMT through polarity control. In some embodiments, the method includes:
在衬底上依次生长主要由作为沟道层的第一半导体层和作为势垒层的第二半导体层组成的异质结构,且使分布于栅电极正下方的第一半导体层的局部区域的组成材料及第二半导体层的局部区域的组成材料均具有设定极性,从而使得当在所述栅电极施加零偏压或者没有施加偏压时,于所述栅电极正下方的异质结构局部区域内无二维电子气的积累,而当在所述栅电极电压大于阈值电压时,能够于所述栅电极正下方的异质结构局部区域内形成二维电子气;A heterostructure mainly composed of a first semiconductor layer as a channel layer and a second semiconductor layer as a barrier layer is sequentially grown on the substrate, and the local area of the first semiconductor layer distributed directly under the gate electrode is made Both the constituent material and the constituent material of the partial region of the second semiconductor layer have a set polarity, so that when zero bias voltage or no bias voltage is applied to the gate electrode, the heterostructure directly below the gate electrode There is no accumulation of two-dimensional electron gas in the local area, and when the voltage of the gate electrode is greater than the threshold voltage, two-dimensional electron gas can be formed in the local area of the heterostructure directly below the gate electrode;
以及,制作源、漏、栅电极,并使所述源、漏电极能够通过形成于所述异质结构中的二维电子气电连接,且使所述栅电极分布于源、漏电极之间。And, making source, drain, and gate electrodes, and enabling the source and drain electrodes to be electrically connected through the two-dimensional electron gas formed in the heterostructure, and distributing the gate electrodes between the source and drain electrodes .
在一些实施例中,对于半导体材料极性的控制,可以通过但不限于在衬底上首先生长一层纳米级的种子层(厚度约几纳米到几百纳米,材料可以选择但不限于选择氮化镓,氮化铝等半导体材料,可以有效的改变生长材料的生长极性即可),然后通过图形化的方式刻蚀部分区域的种子层,实现带有种子层区域和未有种子层区域生长材料过程中极性的转变。In some embodiments, for the control of the polarity of the semiconductor material, it is possible to grow a nanometer-scale seed layer (thickness is about several nanometers to hundreds of nanometers) on the substrate, but not limited to, the material can be selected but not limited to nitrogen Gallium nitride, aluminum nitride and other semiconductor materials can effectively change the growth polarity of the growth material), and then etch the seed layer in some areas by patterning to realize the area with the seed layer and the area without the seed layer Polarity transition during growth of material.
在一些实施例中,所述方法具体可以包括:In some embodiments, the method may specifically include:
在衬底上设置种子层,并对种子层进行图形化处理,且使图形化种子层所在区域或从种子层中露出的衬底所在区域与栅电极的分布区域对应,A seed layer is provided on the substrate, and the seed layer is patterned, and the area where the patterned seed layer is located or the area where the substrate is exposed from the seed layer is located corresponds to the distribution area of the gate electrode,
在图形化种子层及从图形化种子层中露出的衬底表面上依次生长第一半导体层和第二半导体层,其中,生长在种子层上的半导体材料与直接生长在衬底表面的半导体材料极性相反。The first semiconductor layer and the second semiconductor layer are grown sequentially on the patterned seed layer and the substrate surface exposed from the patterned seed layer, wherein the semiconductor material grown on the seed layer and the semiconductor material directly grown on the substrate surface opposite polarity.
在一些较为具体的实施案例中,所述种子层的组成材料为氮性材料,且生长于图形化种子层表面的材料为氮性材料,且栅电极在衬底上的正投影覆盖图形化种子层。In some more specific implementation cases, the constituent material of the seed layer is a nitrogenous material, and the material grown on the surface of the patterned seed layer is a nitrogenous material, and the orthographic projection of the gate electrode on the substrate covers the patterned seed layer.
其中,所述种子层的材质可以选择但不限于选择氮化镓,氮化铝等半导体材料。Wherein, the material of the seed layer can be selected but not limited to gallium nitride, aluminum nitride and other semiconductor materials.
在一些实施例中,所述种子层的生长方式可以选择但不限于使用金属有机化学气相沉积(MOCVD)、分子束外延(MBE)或磁控溅射等。In some embodiments, the growth method of the seed layer can be selected but not limited to metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or magnetron sputtering.
在一些实施例中,所述异质结构与栅电极之间设置栅介质层。所述栅介质层的材质可以选择但不限于使用Al2O3、氮化硅、SiO2等半导体介质。In some embodiments, a gate dielectric layer is disposed between the heterostructure and the gate electrode. The material of the gate dielectric layer can be selected but not limited to Al 2 O 3 , silicon nitride, SiO 2 and other semiconductor media.
本发明通过在半导体材料生长过程中对材料极性进行控制,即可有效实现增强型HEMT器件,不会引入等离子体等对材料的损伤,因而可保障器件性能,且具有工艺简单,重复性高,成本低廉,易于进行大规模生产等特点。By controlling the polarity of the material during the growth process of the semiconductor material, the invention can effectively realize the enhanced HEMT device, without introducing damage to the material such as plasma, thus ensuring the performance of the device, and has the advantages of simple process and high repeatability , low cost, easy to carry out large-scale production and so on.
以下结合附图等对本发明的技术方案作进一步的解释说明。The technical solution of the present invention will be further explained below in conjunction with the drawings and the like.
参阅图1,对于普通HEMT器件(以AlGaN/GaN器件为例,如下均简称“器件”),一般而言,当在栅电极8施加零偏压或者没有施加偏压时,漏电极6和源电极5都与二维电子气7相连接,所以器件的漏电极6和源电极5是导通的,器件处于开启状态,一般称这种器件为耗尽型HEMT器件,也可以称作常开型HEMT器件。在器件关断过程中,栅电极必须施加一定的负偏压,并且所加偏压V<Vth,将栅下二维电子耗尽,在实际的应用过程中,存在功耗高和安全性方面的问题。Referring to FIG. 1, for a common HEMT device (taking AlGaN/GaN devices as an example, hereinafter referred to as "device"), generally speaking, when zero bias voltage or no bias voltage is applied to the gate electrode 8, the drain electrode 6 and the source The electrodes 5 are all connected to the two-dimensional electron gas 7, so the drain electrode 6 and the source electrode 5 of the device are conductive, and the device is in an open state. Generally, this device is called a depletion HEMT device, and it can also be called normally open. type HEMT devices. In the process of turning off the device, a certain negative bias must be applied to the gate electrode, and the applied bias voltage V<Vth will deplete the two-dimensional electrons under the gate. In the actual application process, there are high power consumption and safety aspects. The problem.
参阅图2,对于普通增强型HEMT器件而言,当在栅电极8施加零偏压或者没有施加偏压时,由于栅电极8下面的二维电子气被耗尽,所以源电极5和漏电极6处于断开状态,一般称这种器件为增强型HEMT器件,也可以称作常关型HEMT器件。为了使器件处于开启状态,必须使栅电极的下端积累电子,实现源电极5和漏电极6之间的连接,当栅电极8加偏压达到Vg>Vth时,Vth为器件的阈值电压,对于增强型HEMT器件一般Vth为正值,器件开启。Referring to Fig. 2, for a common enhancement mode HEMT device, when zero bias voltage or no bias voltage is applied to the gate electrode 8, since the two-dimensional electron gas under the gate electrode 8 is depleted, the source electrode 5 and the drain electrode 6 is in an off state, and this device is generally called an enhanced HEMT device, and it can also be called a normally-off HEMT device. In order to make the device in the open state, electrons must be accumulated at the lower end of the gate electrode to realize the connection between the source electrode 5 and the drain electrode 6. When the gate electrode 8 is biased to Vg>Vth, Vth is the threshold voltage of the device. For The enhanced HEMT device generally has a positive value of Vth and the device is turned on.
参阅图3是本发明一典型实施方案中采用极性控制方法所实现的增强型HEMT的结构示意图。Referring to FIG. 3 , it is a schematic structural diagram of an enhanced HEMT realized by using a polarity control method in a typical embodiment of the present invention.
而一种实现增强型HEMT的方法可以包括:首先,在衬底1上生长一层用来改变材料极性的种子层9,生长方式可以选择但不限于使用金属有机化学气相沉积(MOCVD)、分子束外延(MBE)或磁控溅射等。然后通过图形化的方法,将栅下的种子层刻蚀干净,进行材料的外延生长,在外延过程中,生长在种子层9上的材料和直接生长在衬底上的材料10的极性相反,所以可以实现在栅电极区域,无法形成二维电子气的积累,在栅电极区域以外,由于势垒层4和沟道层的自发极化和压电极化,会形成高浓度的二维电子气。当在栅电极8施加零偏压或者没有施加偏压时,漏电极6和源电极5都与二维电子气7相连接,但在器件的栅电极下方没有二维电子气的积累,所以器件的漏电极6和源电极5是断开的,器件处于关闭状态,当栅压大于阈值电压时,栅电极的下端积累电子,实现源电极5和漏电极6之间的连接,器件导通,所以器件为常关型GaN HEMT器件。A method for realizing an enhanced HEMT may include: first, growing a seed layer 9 on the substrate 1 to change the polarity of the material. The growth method can be selected but not limited to metal organic chemical vapor deposition (MOCVD), Molecular beam epitaxy (MBE) or magnetron sputtering, etc. Then, by patterning, the seed layer under the gate is etched clean, and the epitaxial growth of the material is carried out. During the epitaxial process, the polarity of the material grown on the seed layer 9 is opposite to that of the material 10 directly grown on the substrate. , so it can be realized that in the gate electrode region, the accumulation of two-dimensional electron gas cannot be formed, and outside the gate electrode region, due to the spontaneous polarization and piezoelectric polarization of the barrier layer 4 and the channel layer, a high concentration of two-dimensional electron gas will be formed electronic gas. When zero bias or no bias is applied to the gate electrode 8, both the drain electrode 6 and the source electrode 5 are connected to the two-dimensional electron gas 7, but there is no accumulation of two-dimensional electron gas under the gate electrode of the device, so the device The drain electrode 6 and the source electrode 5 are disconnected, and the device is in an off state. When the gate voltage is greater than the threshold voltage, the lower end of the gate electrode accumulates electrons to realize the connection between the source electrode 5 and the drain electrode 6, and the device is turned on. Therefore, the device is a normally-off GaN HEMT device.
参阅图4是本发明一典型实施方案中采用极性控制的方法实现增强型MISHEMT的示意图;首先,在衬底1上,生长一层用来改变材料极性的种子层9,生长方式可以选择但不限于使用金属有机化学气相沉积(MOCVD)、分子束外延(MBE)或磁控溅射等。然后通过图形化方法,将栅下的种子层刻蚀干净,进行材料的外延生长。其中,图形化方法可以利用业界知悉的任何合适方式,例如光刻、湿法或干法刻蚀等方式实现。进而,在外延生长过程中,生长在种子层9上的半导体材料和直接生长在衬底上的半导体材料10的极性相反,所以可以实现在栅电极区域,无法形成二维电子气的积累,在栅电极区域以外,由于势垒层4和沟道层的自发极化和压电极化,会形成高浓度的二维电子气。为减小栅漏电和增加栅摆幅,在势垒层4和栅电极8之间插入一层栅介质11,栅介质的材质可以选择但不限于二氧化硅、氮化硅和氧化铝等半导体。Referring to Fig. 4 is the schematic diagram that adopts the method for controlling polarity to realize enhanced MISHEMT in a typical embodiment of the present invention; At first, on substrate 1, grow one deck to be used for changing the seed layer 9 of material polarity, growth mode can be selected But not limited to using Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE) or Magnetron Sputtering, etc. Then, the seed layer under the gate is etched clean by a patterning method, and epitaxial growth of the material is performed. Wherein, the patterning method can be implemented by any suitable method known in the industry, such as photolithography, wet or dry etching, and the like. Furthermore, during the epitaxial growth process, the polarity of the semiconductor material grown on the seed layer 9 is opposite to that of the semiconductor material 10 directly grown on the substrate, so it can be realized that the accumulation of two-dimensional electron gas cannot be formed in the gate electrode region, Outside the gate electrode region, due to the spontaneous polarization and piezoelectric polarization of the barrier layer 4 and the channel layer, a high-concentration two-dimensional electron gas is formed. In order to reduce the gate leakage and increase the gate swing, a layer of gate dielectric 11 is inserted between the barrier layer 4 and the gate electrode 8. The material of the gate dielectric can be selected but not limited to semiconductors such as silicon dioxide, silicon nitride and aluminum oxide. .
参阅图5是本发明一典型实施方案采用极性控制实现增强型HEMT的能带示意图;由能带示意图可以得到,不同极性GaN材料的能带弯曲时相反的,对于镓面材料而言,如果势垒层是GaN,那么在异质结构界面处由于能带无法形成量子阱限制二维电子气,所以没有电子的积累。因而可以通过极化的不同实现增强型HEMT器件。Referring to Fig. 5, a typical embodiment of the present invention adopts the polarity control to realize the energy band schematic diagram of the enhanced HEMT; it can be obtained from the energy band schematic diagram that the energy band bending of GaN materials with different polarities is opposite, and for gallium surface materials, If the barrier layer is GaN, then there is no electron accumulation at the interface of the heterostructure due to the inability to form a quantum well to confine the two-dimensional electron gas at the interface of the heterostructure. Therefore, the enhanced HEMT device can be realized by different polarization.
实施例请参考图3,首先在衬底1上生长种子层9,其材质可以选择但不限于选择氮化镓,氮化铝等半导体材料,生长方式可以选择但不限于使用金属有机化学气相沉积(MOCVD)、分子束外延(MBE)或磁控溅射等。生长的种子层为氮性材料,对于前述样品进行图形化,在带有种子层的上方生长的材料为氮性材料,并且氮性材料在栅电极的覆盖之下。在栅电极以外为镓性半导体材料,通过外延技术,依次在衬底1上生长沟道层2,空间层3和势垒层4,在这里只表示出HEMT器件的基本结构和外延结构,在实际的外延和器件制作过程中,还会涉及缓冲层、高阻层和盖帽层等结构,而形成这些结构的方法均可以采用业界已知的合适方式。以及,在器件的制作过程中,可首先进行台面隔离,隔离方式可以选择但不限于使用离子注入隔离和台面刻蚀隔离(如使用氯等离子体),然后通过设计的掩膜版和光刻技术在样品表面形成源、漏电极的图形化,然后再沉积金属,一般选择沉积钛/铝/镍/金(Ti/Al/Ni/Au 20nm/130nm/50nm/150nm)等多层金属,金属沉积后将源、漏电极外的金属剥离干净,进行快速退火(890℃30秒),退火后源电极5和漏电极6与二维电子气7相连接。然后通过光刻的方法形成栅金属的图形,沉积栅金属(一般选择Ni/Au 50nm/150nm)和剥离工艺,形成栅电极,栅电极完全覆盖氮性氮化镓材料。在一些较为优选的实施方案之中,为了提高器件的性能,还可以采取一些钝化方式,这些都是通过业界已知的合适方式实现的。Please refer to FIG. 3 for the embodiment. First, a seed layer 9 is grown on the substrate 1. Its material can be selected but not limited to semiconductor materials such as gallium nitride and aluminum nitride. The growth method can be selected but not limited to metal organic chemical vapor deposition. (MOCVD), molecular beam epitaxy (MBE) or magnetron sputtering, etc. The grown seed layer is a nitrogen material. For the aforementioned sample, the material grown above the seed layer is a nitrogen material, and the nitrogen material is covered by the gate electrode. Outside the gate electrode is a gallium semiconductor material. Through epitaxial technology, a channel layer 2, a space layer 3 and a barrier layer 4 are grown on the substrate 1 in sequence. Only the basic structure and epitaxial structure of the HEMT device are shown here. In the actual process of epitaxy and device fabrication, structures such as buffer layer, high-resistance layer, and capping layer are also involved, and methods for forming these structures can be adopted in suitable methods known in the industry. And, in the manufacturing process of the device, the mesa isolation can be carried out first, and the isolation method can be selected but not limited to ion implantation isolation and mesa etching isolation (such as using chlorine plasma), and then through the designed mask and photolithography technology Pattern the source and drain electrodes on the surface of the sample, and then deposit metal, generally choose to deposit multi-layer metals such as titanium/aluminum/nickel/gold (Ti/Al/Ni/Au 20nm/130nm/50nm/150nm), metal deposition Afterwards, the metal outside the source and drain electrodes is peeled off, and rapid annealing (890° C. for 30 seconds) is performed. After annealing, the source electrode 5 and the drain electrode 6 are connected to the two-dimensional electron gas 7 . Then form the pattern of the gate metal by photolithography, deposit the gate metal (generally choose Ni/Au 50nm/150nm) and lift-off process to form the gate electrode, and the gate electrode completely covers the gallium nitride material. In some preferred embodiments, in order to improve the performance of the device, some passivation methods may also be adopted, which are realized through suitable methods known in the industry.
又及,为减小栅漏电和增加栅摆幅,本发明也适合制作MISHEMT器件,其可通过在势垒层4和栅电极8之间插入至少一层栅介质11而实现。其中,栅介质可以选择但不限于二氧化硅、氮化硅和氧化铝等半导体材料。Furthermore, in order to reduce gate leakage and increase gate swing, the present invention is also suitable for manufacturing MISHEMT devices, which can be realized by inserting at least one layer of gate dielectric 11 between the barrier layer 4 and the gate electrode 8 . Wherein, the gate dielectric can be selected from but not limited to semiconductor materials such as silicon dioxide, silicon nitride and aluminum oxide.
该HEMT的工作原理如下:参阅图2,阈值电压Vth为正值,当栅电压Vg<Vth时,由于栅下为氮性半导体材料,由于极化电场的转变,在异质结构处无法形成二维电子气,所以源电极5和漏电极6处于断开,所以器件处于断开状态。当栅电压Vg>Vth时,栅下区域会积累电子,积累的电子形成新的导通沟道,使源电极5和漏电极6导通,器件处于开启状态。The working principle of the HEMT is as follows: Referring to Figure 2, the threshold voltage Vth is a positive value. When the gate voltage Vg<Vth, due to the nitrogen semiconductor material under the gate and the transformation of the polarization electric field, no dual The electron gas is maintained, so the source electrode 5 and the drain electrode 6 are disconnected, so the device is in an off state. When the gate voltage Vg>Vth, the region under the gate will accumulate electrons, and the accumulated electrons will form a new conduction channel, making the source electrode 5 and the drain electrode 6 conduct, and the device is in the on state.
应当理解,上述实施例仅为说明本发明的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施,并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰,都应涵盖在本发明的保护范围之内。It should be understood that the above-mentioned embodiments are only to illustrate the technical concept and features of the present invention, the purpose of which is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and not to limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention shall fall within the protection scope of the present invention.
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