CN106206309A - Secondary epitaxy p-type nitride realizes method and enhancement mode HEMT of enhancement mode HEMT - Google Patents

Abstract

The invention discloses a kind of secondary epitaxy p-type nitride and realize method and enhancement mode HEMT of enhancement mode HEMT.The method includes: provides heterojunction structure, and makes source, drain electrode on described heterojunction structure, makes source, drain electrode form Ohmic contact with heterojunction structure surface and also all be connected with the two-dimensional electron gas in heterojunction structure；The subregion that heterojunction structure is positioned at the barrier layer immediately below gate electrode (such as AlGaN layer) and n type semiconductor layer (such as i GaN layer) performs etching, and is formed and penetrates the groove in n type semiconductor layer；By this groove growing P-type quasiconductor in n type semiconductor layer, this P-type semiconductor can be formed with n type semiconductor layer when gate electrode connecting to neutral biases PN junction and when gate electrode connects forward voltage transoid and make source, drain electrode conducting；And, between source, drain electrode, make gate electrode.The present invention effectively achieves enhancement mode HEMT, and technique is simple, and repeatability is high, with low cost, it is easy to carry out large-scale production.

Description

Method for Realizing Enhanced HEMT by Secondary Epitaxial P-type Nitride and Enhanced HEMT

technical field

The invention relates to an enhanced HEMT (high electron mobility transistor) device, in particular to a method for realizing an enhanced HEMT by secondary epitaxy of a P-type nitride semiconductor and a corresponding enhanced HEMT, belonging to the field of microelectronic technology.

Background technique

HEMT devices are made by making full use of the two-dimensional electron gas formed by the heterojunction structure of semiconductors. Compared with the III-VI group (such as AlGaAs/GaAs HEMT), the III-nitride semiconductor can form a high concentration of dioxane on the heterostructure (such as AlGaN/GaN) due to the piezoelectric polarization and spontaneous polarization effects. Dimensional electron gas. Therefore, in HEMT devices made of group III nitrides, the barrier layer generally does not need to be doped. Group III nitrides have the characteristics of large band gap, high saturated electron drift velocity, high critical breakdown electric field and strong radiation resistance, which can meet the requirements of higher power and higher power devices in the next generation of power electronic systems. Requirements for high frequency, smaller volume and higher temperature work.

When the existing III-nitride semiconductor HEMT devices are used as high-frequency devices or high-voltage high-power switching devices, especially when used as power switching devices, the enhancement mode HEMT device is helpful to improve the safety of the system compared with the depletion mode HEMT device performance, reduce device loss and simplify circuit design. At present, the main methods for realizing enhanced HEMT include thin barrier layer, concave gate structure, P-type capping layer and F treatment and other technologies. But these technologies all have their own shortcomings. For example, the world's first enhancement mode HEMT device is realized by using a thinner barrier layer. This method does not use an etching process, so the damage caused is small, but due to the thinner barrier layer, the saturation of the device The current is small. F plasma treatment can also realize enhanced HEMT devices, and does not require etching, but F plasma will also etch the barrier layer during the implantation process, resulting in a decrease in device performance. The P-type cap layer technology does not produce the influence of ion etching on the channel electrons, so it has a high saturation current. However, the generally used P-type semiconductors (such as P-AlGaN, P-GaN, P-InGaN, etc.) In the process of dry etching (such as Cl ₂ plasma etching), the barrier layer AlGaN has a small etching selectivity ratio to the P-type semiconductor, so it is difficult to control the complete etching of the P-type semiconductor, and the etching stops at the same time. On the surface of the barrier layer AlGaN.

Contents of the invention

An important purpose of the present invention is to propose a method for realizing enhanced HEMT by secondary epitaxy of P-type nitride, so as to overcome the deficiencies in the prior art.

Another important purpose of the present invention is to provide an enhanced HEMT with an improved structure.

In order to realize the above-mentioned purpose of the invention, the present invention has adopted following technical scheme:

An enhanced HEMT includes a heterostructure mainly composed of an N-type semiconductor layer and a barrier layer, and source, drain, and gate electrodes. The source and drain electrodes form ohmic contacts with the surface of the heterostructure, and are also connected to the heterostructure. The two-dimensional electron gas connection in the material structure, the gate electrode is arranged between the source and drain electrodes, wherein a P-type semiconductor is distributed in a local area of the N-type semiconductor layer directly below the gate electrode, the The P-type semiconductor is completely covered by the gate electrode, and when the gate electrode is connected to zero bias, the P-type semiconductor and the N-type semiconductor layer form a PN junction, and when the gate electrode is connected to a forward voltage, the P-type semiconductor is inverted Make the source and drain electrodes conduction.

In a more specific embodiment, the heterostructure is mainly composed of intrinsic GaN layer (i-GaN layer) and _{AlxGa (1-x)} N layer, 0<x≤1, and located in the P-type GaN is distributed in a local area of the intrinsic GaN layer under the gate electrode, and the P-type GaN forms a PN junction with the intrinsic GaN layer.

In a more preferred embodiment, a gate dielectric layer is distributed between the gate electrode, the barrier layer and the P-type semiconductor.

In one embodiment, the gate electrode is located between the source electrode and the drain electrode and close to the side of the source electrode.

In one embodiment, the source electrode and the drain electrode are respectively connected to the low potential and the high potential of the power supply.

In one embodiment, a space layer is distributed between the N-type semiconductor layer and the barrier layer.

In the present invention, the P-type semiconductor is completely covered by the gate electrode, which means that the P-type semiconductor is all distributed in the orthographic projection of the gate electrode.

A method for secondary epitaxial P-type nitride to realize an enhanced HEMT, comprising:

Provide a heterostructure mainly composed of an N-type semiconductor layer and a barrier layer, and fabricate source and drain electrodes on the heterostructure, so that the source and drain electrodes form an ohmic contact with the surface of the heterostructure, and make the source and drain electrodes The poles are connected to the two-dimensional electron gas in the heterostructure;

Etching the barrier layer directly below the gate electrode and a partial region of the N-type semiconductor layer of the heterostructure to form a groove penetrating from the surface of the barrier layer into the N-type semiconductor layer;

The P-type semiconductor is epitaxially grown in the N-type semiconductor layer through the groove, and the P-type semiconductor can form a PN junction with the N-type semiconductor layer when the gate electrode is connected to zero bias, and can be connected to the forward direction of the gate electrode. When the voltage is reversed, the source and drain electrodes are turned on;

And, a gate electrode is formed between the source and drain electrodes.

In a more specific implementation, the heterostructure is mainly composed of intrinsic GaN layer and _{AlxGa (1-x)} N layer, 0<x≤1, and the intrinsic P-type GaN is distributed in a local area of the GaN layer, and the P-type GaN forms a PN junction with the intrinsic GaN layer.

In a more specific implementation, the method for implementing the enhanced HEMT by secondary epitaxial P-type nitride includes:

making a mask on the surface of the heterostructure, and patterning the mask;

The barrier layer under the gate and part of the intrinsic GaN layer are etched by a dry etching process, and the etching depth is above 30nm.

And, secondary epitaxial growth of P-type GaN with a thickness of 30nm-70nm in the etched intrinsic GaN layer region, the doping concentration of the P-type GaN is 10E18cm ^-3 to 10E19cm ^-3 , and the doping ions include Mg ²⁺ , but not limited to.

Further, a mask needs to be made during the secondary epitaxy of P-type gallium nitride. Self-alignment can be achieved through the mask used in etching, and SiN or SiO ₂ can be used as a mask. When growing GaN, gallium nitride cannot form a thin film on SiN or SiO ₂ semiconductors, so the process can be simplified and the lift-off process after the second epitaxy can be avoided.

In a more preferred implementation, the method for implementing the enhanced HEMT by secondary epitaxial P-type nitride further includes: growing a gate dielectric layer on the surface of the barrier layer, the groove wall and the surface of the P-type semiconductor, Then make a gate electrode on the gate dielectric layer.

In the present invention, the dry etching process used may be optional but not limited to plasma etching process and the like.

In the present invention, for the P-type semiconductor, its doping concentration depends on the actual application requirements of the device.

In the present invention, the secondary epitaxy of the P-type semiconductor can be selected but not limited to using semiconductor epitaxy equipment such as MBE (molecular beam epitaxy) or MOCVD (metal organic chemical vapor deposition).

In the present invention, the material of the aforementioned gate dielectric layer can be selected but not limited to common semiconductors such as SiN, SiO ₂ and Al ₂ O ₃ .

Compared with the prior art, the advantages of the present invention include: through secondary epitaxy of P-type semiconductors, using P-type semiconductors (such as P-type gallium nitride) and N-type semiconductor layers (such as intrinsic gallium nitride) to form opposite PN Junction, to realize that under zero bias, the device is in an off state, and the gate electrode can make the P-type semiconductor reverse to realize the conduction of the source and drain electrodes, thereby converting the depletion-type HEMT device into an enhancement-type HEMT device, effectively Enhanced HEMT (such as GaN HEMT) is realized, and the manufacturing process of the device is also characterized by simplicity, good repeatability, good controllability, low cost, and easy mass production.

Description of drawings

Fig. 1 is a partial structural schematic diagram of a common depletion mode HEMT device;

Fig. 2 is a schematic diagram of the structure of an enhanced HEMT realized by using a P-type semiconductor in a typical embodiment of the present invention;

Fig. 3a-Fig. 3b is the energy band diagram and basic principle diagram of realizing enhanced HEMT in a typical embodiment of the present invention;

Description of reference numerals: substrate 1, gallium nitride layer 2, aluminum nitride layer 3, barrier layer 4, P-type semiconductor layer 5, gate dielectric layer 6, gate electrode 7, two-dimensional electron gas 8, source electrode 9 , a drain electrode 10 , an intrinsic GaN energy band portion 11 , a P-type GaN energy band portion 12 , a Fermi level 13 , and a PN junction 14 .

detailed description

Referring to FIG. 1, for a common HEMT device (taking AlGaN/GaN devices as an example, hereinafter referred to as "device"), in general, when zero bias is applied to the gate electrode 7 or no bias is applied, the drain electrode 9 and the source The electrodes 10 are all connected to the two-dimensional electron gas 8, so the drain electrode 9 and the source electrode 10 of the device are turned on, and the device is in an open state. Generally, this device is called a depletion HEMT device, and it can also be called normally open. type HEMT devices. In the process of turning off the device, a certain negative bias must be applied to the gate electrode, and the applied bias voltage V<Vth will deplete the two-dimensional electrons under the gate. In the actual application process, there are high power consumption and safety aspects. The problem.

Referring to Fig. 2, for an ordinary enhancement mode HEMT device, when zero bias voltage or no bias voltage is applied to the gate electrode 7, since the P-type semiconductor 5 under the gate electrode 7 forms an opposite PN junction with the intrinsic semiconductor 2 , so the source electrode 9 and the drain electrode 10 are in a disconnected state, and this kind of device is generally called an enhanced HEMT device, and it can also be called a normally-off HEMT device. In order to make the device in the open state, electrons must be accumulated at the lower end of the gate electrode to realize the connection between the source electrode 9 and the drain electrode 10. When the gate electrode 11 is biased to Vg>Vth, Vth is the threshold voltage of the device. For The enhanced HEMT device generally has a positive Vth value, and when the electrons gathered by the P-type semiconductor under the gate make the P-type semiconductor 5 invert, electrons can be accumulated under the gate, thereby making the device in an on state. In the actual circuit application process of this device, the device is turned off only when the gate 7 is applied with 0 bias. Compared with the depletion device, the power consumption of the device is reduced, and the safety of the system is higher.

In the present invention, an opposite PN junction structure is formed by secondary epitaxy of P-type gallium nitride. When zero bias voltage or no bias voltage is applied to the gate electrode, the source and drain electrodes are in the disconnected state. When the gate electrode 11 is biased to reach When Vg>Vth, Vth is the threshold voltage of the device. When the electrons accumulated by the P-type semiconductor under the gate make the P-type semiconductor 5 invert, electrons can be accumulated under the gate, so that the device is in an open state, and the enhanced HEMT device is realized. Purpose.

Referring to Fig. 2, in a typical embodiment of the present invention, in order to realize enhanced HEMT device, at first make source electrode 9 and drain electrode 10, source, drain electrode form good ohmic contact with heterostructure surface, and with two-dimensional electron Gas 8 connection. Then deposit the mask required for etching on the surface of the sample, optional but not limited to SiN, _SiO2 , etc., and then pattern the sample through a semiconductor process (such as laser direct writing, photolithography, etc.), and expose the part to be etched On the outside, the AlGaN barrier layer 4 and part of the gallium nitride 2 are etched by an etching process, and then the P-type nitride semiconductor 5 is grown by secondary epitaxy. The growth method can be selected but not limited to MBE or MOCVD to grow. Then grow a layer of gate dielectric 6 on the surface of the sample, the gate dielectric can be selected but not limited to semiconductor thin films such as SiO ₂ , SiN or Al ₂ O ₃ . Finally, the gate metal is deposited to form an enhanced MISHEMT device.

3a-3b are energy band diagrams and basic principle diagrams of an enhanced HEMT in a typical implementation case of the present invention; secondary epitaxial P-type gallium nitride 5 and intrinsic gallium nitride 2 form a PN junction structure 14, When a voltage is applied to the source and drain electrodes, there is always a PN junction in a reverse bias state, so the device is turned off. When a forward bias voltage is applied to the gate electrode, the energy band 12 part of the barrier of the device begins to drop, and the device is turned on.

Please refer to FIG. 2 for the embodiment. First, the epitaxial HEMT structure is formed on the substrate 1, and the source electrode 9 and the drain electrode 10 are made. The electrodes form a good ohmic contact with the semiconductor AlGaN. Generally, titanium/aluminum/nickel/gold (Ti/Al /Ni/Au20nm/130nm/50nm/150nm) and other multi-layer metals, after metal deposition, the metal outside the source and drain electrodes is peeled off, and then rapid annealing (890 degrees Celsius for 30 seconds), after annealing, the source electrode 9 and drain electrode 10 and Two-dimensional electron gas 8-phase connection. Then deposit the mask required for etching on the surface of the sample, optional but not limited to SiN, _SiO2 , etc., the equipment used can be PECVD, ICPCVD, etc., the thickness of the deposition is 100nm (thickness can be adjusted according to the actual situation), and then through the semiconductor process (such as laser direct writing, photolithography, etc.) patterning the sample, exposing the part to be etched, and then etching the AlGaN barrier layer 4 and part of the gallium nitride 2 through the etching process, during the etching process ICP-RIE etching equipment can be selected for AlGaN semiconductor etching. Chlorine-based plasma, such as chlorine gas or boron trichloride, can be used for etching AlGaN semiconductors. The etching depth can be 50nm, and then the P-type can be grown by secondary epitaxy. The growth method of the nitride semiconductor 5 can be selected but not limited to growth by using MBE or MOCVD. Its thickness is about 30nm-70nm, and the doping concentration is between 10E18cm ^-3 and 10E19cm ^-3 . The specific doping concentration depends on the specific design requirements of the device. The P-type semiconductor and the intrinsic gallium nitride semiconductor form a PN junction structure. When the device is in the working state of zero gate bias, the source and drain electrodes are disconnected. Then grow a layer of gate dielectric 6 on the surface of the sample, the gate dielectric can be selected but not limited to semiconductor thin films such as SiO ₂ , SiN or Al ₂ O ₃ . Finally, the gate metal (Ni/Au50nm/150nm) is deposited to form an enhanced MISHEMT device. In order to improve the performance of the device, some passivation methods are required. These methods are known in the industry, so they will not be listed here.

The working principle of the HEMT is as follows: Referring to Figures 3a-3b, in the enhanced HEMT device, the threshold voltage Vth is positive, and when the gate voltage Vg<Vth, the P-type semiconductor under the gate and the intrinsic semiconductor form a PN junction structure , so the source electrode 9 and the drain electrode 10 are disconnected, so the device is in an off state. When the gate voltage Vg>Vth, it means that the area under the gate will accumulate electrons, and the accumulated electrons will form a new conduction channel, making the source electrode 9 and the drain electrode 10 conduct, and the device is in the on state.

The above-mentioned embodiments are only to illustrate the technical conception and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and not to limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention shall fall within the protection scope of the present invention.

Claims (10)

1. An enhanced HEMT, comprising a heterostructure and source, drain, and gate electrodes mainly composed of an N-type semiconductor layer and a barrier layer, the source and drain electrodes form an ohmic contact with the surface of the heterostructure, and simultaneously It is connected to the two-dimensional electron gas in the heterostructure, the gate electrode is arranged between the source and drain electrodes, and it is characterized in that P-type Semiconductor, the P-type semiconductor is completely covered by the gate electrode, and when the gate electrode is connected to zero bias, the P-type semiconductor and the N-type semiconductor layer form a PN junction, and when the gate electrode is connected to a forward voltage, the P-type Type semiconductor inversion makes the source and drain electrodes conduction. 2. The enhanced HEMT according to claim 1, characterized in that the heterostructure is mainly composed of an intrinsic GaN layer and an _{AlxGa (1-x)} N layer, 0<x≤1, and in the P-type GaN is distributed in a local area of the intrinsic GaN layer under the gate electrode, and the P-type GaN forms a PN junction with the intrinsic GaN layer. 3. The enhancement mode HEMT according to claim 1 or 2, characterized in that a gate dielectric layer is distributed between the gate electrode, the barrier layer and the P-type semiconductor. 4 . The enhancement mode HEMT according to claim 1 , wherein the gate electrode is located between the source electrode and the drain electrode, close to the side of the source electrode. 5. The enhanced HEMT according to claim 1, characterized in that the source electrode and the drain electrode are respectively connected to the low potential and the high potential of the power supply. 6. The enhanced HEMT according to claim 1, characterized in that a space layer is distributed between the N-type semiconductor layer and the barrier layer. 7. A method for secondary epitaxial P-type nitride to realize enhanced HEMT, characterized in that it comprises: Provide a heterostructure mainly composed of an N-type semiconductor layer and a barrier layer, and fabricate source and drain electrodes on the heterostructure, so that the source and drain electrodes form an ohmic contact with the surface of the heterostructure, and make the source and drain electrodes The poles are connected to the two-dimensional electron gas in the heterostructure; Etching the barrier layer directly below the gate electrode and a partial region of the N-type semiconductor layer of the heterostructure to form a groove penetrating from the surface of the barrier layer into the N-type semiconductor layer; The P-type semiconductor is epitaxially grown in the N-type semiconductor layer through the groove, and the P-type semiconductor can form a PN junction with the N-type semiconductor layer when the gate electrode is connected to zero bias, and can be connected to the forward direction of the gate electrode. When the voltage is reversed, the source and drain electrodes are turned on; And, a gate electrode is formed between the source and drain electrodes. 8. The method for realizing enhanced HEMT according to the described secondary epitaxial P-type nitride of claim 7, is characterized in that described heterostructure is mainly made up of intrinsic GaN layer and Al _x Ga _(1-x) N layer, 0< x≤1, and P-type GaN is distributed in a local area of the intrinsic GaN layer under the gate electrode, and the P-type GaN and the intrinsic GaN layer form a PN junction. 9. The method for realizing an enhanced HEMT by secondary epitaxial P-type nitride according to claim 8, characterized in that it comprises: making a mask on the surface of the heterostructure, and patterning the mask; The barrier layer under the gate and part of the intrinsic GaN layer are etched by a dry etching process, and the etching depth is above 30nm. And, secondary epitaxial growth of P-type GaN with a thickness of 30nm-70nm in the etched intrinsic GaN layer region, the doping concentration of the P-type GaN is 10E18cm ^-3 to 10E19cm ^-3 , and the doping ions include Mg ²⁺ . 10. According to any one of claims 7-9, the method for realizing an enhanced HEMT by secondary epitaxial P-type nitride is characterized in that it also includes: A gate dielectric layer is grown on the surface, and then a gate electrode is formed on the gate dielectric layer.