CN111653618B - Built-in PN junction silicon-based high-voltage enhanced gallium nitride transistor and manufacturing method thereof - Google Patents

Abstract

The invention relates to a built-in PN junction silicon-based high-voltage enhanced gallium nitride transistor and a manufacturing process thereof. The breakdown voltage of the EJ-high electron mobility transistor device can be improved by adjusting the electric field distribution through a built-in PN junction structure. The built-in PN junction is used for improving the electric field distribution inside the device between the grid electrode and the drain electrode, so that higher breakdown voltage is realized. The structural parameter optimized EJ-high electron mobility transistor achieves 2050V breakdown voltage performance at a gate-drain distance of 15 μm due to improved internal electric field distribution in the device between the gate and drain. The optimized transistor with the EJ-high electron mobility transistor structure has an on resistance of 15.37 omega mm and a basic quality factor of 2.734GWcm < -2 > of the power semiconductor device. Compared with a transistor without a built-in PN junction, the breakdown voltage of the novel device EJ-high electron mobility transistor is increased by 32.54%, the basic quality factor of the power semiconductor device is increased by 71.3%, and the on-resistance of the novel device EJ-high electron mobility transistor and the power semiconductor device are not greatly different.

Description

Built-in PN junction silicon-based high-voltage enhancement gallium nitride transistor and manufacturing method

technical field

The invention belongs to the field of transistors, and in particular relates to a built-in PN junction silicon-based high-voltage enhanced gallium nitride transistor and a manufacturing method.

Background technique

GaN-based electronics have emerged as one of the most promising candidates for power applications. Due to the strong polarized charges in the AlGaN/GaN heterojunction, a high-density two-dimensional electron gas is formed at the interface between GaN and AlGaN. Therefore, AlGaN/GaN high electron mobility transistors are usually used as depletion-mode devices, and in the past decade, many research efforts on GaN-based electronic devices have focused on depletion-mode AlN Gallium/Gallium Nitride High Electron Mobility Transistors. GaN-enhanced devices are emerging due to many limitations in circuit applications. Compared with depletion-mode AlGaN/GaN high electron mobility transistors, enhancement-mode GaN-based electronic devices have advantages in circuit applications. In circuits such as microwave power amplifiers and low noise amplifiers, negative voltage sources may not be used, which can greatly reduce the complexity and cost of the circuit, and have good circuit compatibility.

To increase the breakdown voltage of GaN-based devices, it is necessary to improve the electric field distribution between the gate and drain. Substrate electrodes have been used to realize high withstand voltage low surface electric field gallium nitride high electron mobility transistors. However, it can only be used for thin GaN buffer layers, and has certain limitations for GaN devices with high breakdown voltage and a certain thickness.

Contents of the invention

In view of the above defects, the present invention provides a built-in PN junction silicon-based high-voltage enhanced gallium nitride transistor with a built-in PN junction silicon-based high-voltage enhanced gallium nitride transistor, which is characterized in that it includes a silicon substrate, a transition layer, a buffer layer, The barrier layer, the built-in N-type layer and the embedded junction formed by the P-type layer form a PN junction in the barrier layer and the buffer layer, and a part of the two-dimensional electron gas is replaced by a highly doped N-type layer, while the P-type layer is embedded in the In the N-type layer; from bottom to top, there are silicon substrate, transition layer, buffer layer, and barrier layer; the barrier layer is an aluminum gallium nitride barrier layer, and two layers are formed on the aluminum gallium nitride barrier layer. Silicon oxide is used as an etching mask, and then the aluminum gallium nitride barrier layer and the gallium nitride buffer layer are etched, and the N-type layer and the P-type layer are re-grown by the crystal growth technology of molecular beam epitaxy, and the dioxide oxide is deposited on the top of the P-type layer. Silicon mask, forming N-type layer, as a passivation layer formed by plasma enhanced chemical vapor deposition, etching silicon nitride and gate groove by inductively coupled plasma, by depositing silicon nitride, as gate dielectric, forming The pure resistance of the source and drain electrodes. This built-in PN junction improves the internal electric field distribution of the device between the gate and drain, thereby increasing the breakdown voltage.

The present invention proposes a new structure of a high electron mobility transistor with a built-in PN junction to improve the breakdown voltage of an analog device. The structure is simulated using the Sentaurus TCAD tool, and the proposed new structure EJ-high electron mobility transistor provides The breakdown voltage is higher than that of the traditional FPC-high electron mobility transistor with an optimized field plate, and the quality factor is higher.

Brief steps of the manufacturing process, the steps of each figure can be summarized as follows:

(a) growing a transition layer on a silicon substrate, and then sequentially growing a buffer layer and an aluminum gallium nitride barrier layer on the transition layer by metal-organic chemical vapor deposition;

(b) forming silicon dioxide as an etch mask by using plasma enhanced chemical vapor deposition;

(c) etching the aluminum gallium nitride barrier layer and the gallium nitride buffer layer by transformer coupled plasma reactive ion etching with boron trichloride and chlorine gas mixture;

(d) A method of combining ultraviolet ozone cleaning and wet etching of hydrogen fluoride and hydrochloric acid to reduce the impurity concentration on the etched surface, and re-grow the N-type layer and the P-type layer through the crystal growth technology of molecular beam epitaxy;

(e) depositing a silicon dioxide mask on top of the P-type layer using plasma-enhanced chemical vapor deposition and forming an N-type layer by silicon ion implantation;

(f) After implantation, the silicon dioxide mask was removed using hydrofluoric acid, followed by a post-implantation anneal to activate the implanted silicon, and an in-situ remote plasma pretreatment technique was used to remove the native oxide on the sample surface, and the surface Minimal damage and deposition of silicon nitride as a passivation layer via plasma enhanced chemical vapor deposition;

(g) dry etching by low power inductively coupled plasma, in particular silicon nitride and gate grooves by inductively coupled plasma;

(h) depositing silicon nitride as a gate dielectric by using plasma enhanced chemical vapor deposition;

(i) A gate electrode is formed, and a pure resistance of a source electrode and a drain electrode is formed.

It should be noted that metal-organic chemical vapor deposition uses organic compounds of group III and group II elements and hydrides of group V and group VI elements as crystal growth source materials, and conducts vapor phase epitaxy on the substrate by thermal decomposition reaction. Thin-layer single crystal materials of various III-V main group, II-VI subgroup compound semiconductors and their multiple solid solutions are grown.

Beneficial effect:

The present invention proposes a silicon-based gallium nitride high electron mobility transistor structure with a built-in PN junction, EJ-high electron mobility transistor, and provides its optimization characteristics through a device simulation tool, and analyzes the device electric field improved by the structure distributed. The optimized EJ-high electron mobility transistor device has Ron of 15.37Ωmm, VTH of 1.7V, LGN=13μm, quality factor BFOM of 2.734GW cm-2, VBK of 2050V, and RON of 15.37Ωmm. Compared with FPC-high electron mobility transistors with optimized field plates (VBK is 1546.6V, Ron is 14.98Ωmm), the basic quality factor of power semiconductor devices is increased by 71.3%, and the breakdown voltage is almost increased by 32.54%, while RON is not much different .

Description of drawings

Figure 1 (a) FPC-high electron mobility transistor (b) EJ-high electron mobility transistor structure diagram;

Fig. 2 Manufacturing process of EJ-high electron mobility transistor;

Fig. 3 Experimental and simulated (a) IDS-VDS performance and (b) breakdown characteristics of EJ-high electron mobility transistor transistors;

Fig. 4 Comparison of channel electric field distribution of C-high electron mobility transistor, FPC-high electron mobility transistor and EJ-high electron mobility transistor;

Fig. 5 Comparison of the drain-source breakdown voltage of C-HEM transistor, FPC-HEM transistor and EJ-HEM transistor when the gate is turned off;

Figure 6 Comparison of lateral two-dimensional electron gas distribution of FPC-high electron mobility transistor and EJ-high electron mobility transistor;

Figure 7 Comparison of constant current characteristic curves of FPC-high electron mobility transistor and EJ-high electron mobility transistor;

Figure 8 Comparison of gate-source transfer characteristic curves of FPC-high electron mobility transistor and EJ-high electron mobility transistor;

Figure 9 EJ-high electron mobility transistor VBK and RON change curve after changing NN+;

Fig. 10 EJ-high electron mobility transistor changes the change curve of VBK and RON after LGN is changed;

Fig.11 Variation trend of VBK and RON with WN in J-high electron mobility transistor structure;

Fig.12 The trend of VBK and RON after changing with HP in the EJ-high electron mobility transistor structure;

Fig.13 The trend of VBK and RON changing with NP in the EJ-high electron mobility transistor structure;

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be described in detail below. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other implementations obtained by persons of ordinary skill in the art without making creative efforts fall within the protection scope of the present invention.

The content of the present invention will be further described in detail below in conjunction with the accompanying drawings and examples, but the scope of the present invention is not limited in any way.

Figure 1(a) and (b) show the architecture of FPC-high electron mobility transistor and EJ-high electron mobility transistor. The parameters of the FPC-high electron mobility transistor without field plate are the same as those in the GaN sample. The epitaxial layer consists of a 2.4μm Al-containing transition layer, a 1.6μm GaN buffer layer and a 21nm AlGaN barrier layer. The mole fraction of AlGaN barrier in FPC-High Electron Mobility Transistor and EJ-High Electron Mobility Transistor is 0.25. The undoped GaN buffer layer is doped with 1×1015 cm-3 N-type concentration. Both structures adopt full recessed gate technology, and choose Si3N4 as the gate dielectric and passivation layer. The thickness of the gate dielectric is 17nm, and the thickness of the passivation layer is 100nm.

Table I summarizes the details of the key structural parameters of the FPC-high electron mobility transistor and the proposed EJ-high electron mobility transistor.

Fig. 2 shows the brief steps of the manufacturing process of the inventive structure, and the steps of each figure can be summarized as follows:

(a) A transition layer is grown on a silicon substrate, and then a buffer layer and an aluminum gallium nitride barrier layer are sequentially grown on the transition layer by metal-organic chemical vapor deposition from bottom to top.

(b) By using plasma-enhanced chemical vapor deposition, silicon dioxide is formed as an etching mask on the aluminum gallium nitride barrier layer, and the etching mask is provided with grooves, and the grooves are formed by the aluminum gallium nitride barrier layer. The upper surface of the layer is the bottom.

(c) The aluminum gallium nitride barrier layer and the gallium nitride buffer layer are etched by transformer coupled plasma reactive ion etching with boron trichloride and chlorine gas mixture.

(d) A method of combining ultraviolet ozone cleaning and wet etching of hydrogen fluoride and hydrochloric acid to reduce the impurity concentration on the etched surface, and re-grow the N-type layer and the P-type layer through the crystal growth technology of molecular beam epitaxy.

(e) A silicon dioxide mask is deposited on top of the P-type layer using plasma-enhanced chemical vapor deposition, and an N-type layer is formed by silicon ion implantation.

(f) After implantation, the silicon dioxide mask was removed using hydrofluoric acid, followed by a post-implantation anneal to activate the implanted silicon, and an in-situ remote plasma pretreatment technique was used to remove the native oxide on the sample surface, and the surface The damage is minimal and silicon nitride is deposited as a passivation layer by plasma enhanced chemical vapor deposition, which is the uppermost layer in Figure 2(f).

(g) Dry etching by low power inductively coupled plasma, specifically silicon nitride and gate recesses by inductively coupled plasma.

(h) Depositing silicon nitride as the gate dielectric by using plasma enhanced chemical vapor deposition.

(i) A gate electrode is formed, and a pure resistance of a source electrode and a drain electrode is formed.

It should be noted that metal-organic chemical vapor deposition uses organic compounds of group III and group II elements and hydrides of group V and group VI elements as crystal growth source materials, and conducts vapor phase epitaxy on the substrate by thermal decomposition reaction. Thin-layer single crystal materials of various III-V main group, II-VI subgroup compound semiconductors and their multiple solid solutions are grown.

Among them, metal-organic chemical vapor deposition uses organic compounds of group III and group II elements and hydrides of group V and group VI elements as crystal growth source materials, and conducts vapor phase epitaxy on the substrate in a thermal decomposition reaction method to grow various Thin-layer single crystal materials of III-V main group, II-VI subgroup compound semiconductors and their multiple solid solutions.

Table 1: Main structural parameters

The two structures were simulated by Synopsys Inc.'s Sentaurus TCAD software. In order to verify the reliability of our use of simulation tools to simulate the performance of the new structure of EJ-high electron mobility transistors, we first use the method of BENCHMARK TEST to make the simulation model, parameters and default parameters confirmed by experimental data. In order to correspond more precisely with the experimental and real quantities, we selected some widely used physical models, such as Recombination model, Shockley ReadHall (SRH) model, Auger model and Mobility model, DopingDep model and high saturation model. In addition, the polarization effects of AlGaN and GaN were calculated by the piezoelectric polarization (strain) model. Under the assumption that the charge carriers are in thermal equilibrium with the lattice, a hot electron model is used to account for the self-heating effect. The avalanche model is used to simulate device breakdown simulation.

Figure 3(a) compares the IDS-VDS characteristics of the experimental results and the simulation results of TCAD at VDS = 10V and VGS = 2, 4, 6, 8 and 10V. It can be seen from the figure that the IDS-VDS characteristics with different VGS are in good agreement with the experimental results, and the RON obtained by the TCAD simulation with Sentaurus is 14.98Ωmm, which is close to the experimental result of 16.1Ωmm.

Figure 3(b) shows the simulated and experimental IDS-VDS and breakdown characteristics of the EJ-high electron mobility transistor. The breakdown voltage of the simulated devices is close to the experimental results. Compared with the experimental results, the leakage current of the simulated device is almost consistent with the experimental test data. Because the field plate has a great influence on the breakdown voltage characteristics, we prefer to choose the EJ-high electron mobility transistor with optimized field plate for comparison.

The simulation results are compared with various scenarios as follows:

Figure 4 plots a comparison of device channel electric field distributions for three GaN high electron mobility transistors under breakdown. This figure shows that the high electric field is concentrated on the drain side of the gate electrode corner in a conventional GaN high electron mobility transistor, that is, a C-high electron mobility transistor. For C-high electron mobility transistors, the peak value of the electric field near the gate reaches 4×106V/cm, almost reaching the critical electric field of GaN material. Thus, the transistor breaks down before the two-dimensional electron gas is completely depleted. For FPC-high electron mobility transistors, with the introduction of the gate field plate and the drain field plate, the electric field near the gate decreases sharply, and the peak electric field appears at the position near the gate field plate. In addition, the peak electric field near the drain plate shifts to the left as the length of the drain plate increases. Compared with C-high electron mobility transistor, FPC-high electron mobility transistor can improve the electric field distribution between gate and drain. To further improve the electric field distribution between the gate and drain, we propose the EJ-high electron mobility transistor.

For GaN-on-Si high electron mobility transistors, the drain leakage current mainly consists of substrate-drain leakage current and source-drain leakage current. In simulations, the substrate is floated to avoid substrate-drain leakage current, while the floating substrate can achieve higher device voltage rating and provide better dynamic RON for high drain bias switching operation. On the other hand, the source-drain leakage current is mainly caused by the buffer leakage current. When the FPC-high electron mobility transistor introduces the built-in N-type layer and P-type layer, the N-type layer and the undoped GaN buffer layer form an N-/N+ junction, and the N-/N+ junction is in the GaN buffer The peak electric field is introduced into the layer, thereby improving the electric field distribution inside the device. The N-type layer and the P-type layer form a built-in PN junction, which improves the electric field distribution between the gate and the N-type layer. Due to the P-type layer below the drain plate, the peak electric field decreases sharply near the drain plate. In addition, the highly N-doped gallium nitride layer is in contact with the buffer layer, and it changes the buffer leakage current path, which makes it more difficult for the EJ-high electron mobility transistor to break down.

Figure 5 shows the off-state characteristics of C-high electron mobility transistor, FPC-high electron mobility transistor and EJ-high electron mobility transistor, and compares the simulated cut-off of VGS=0V for the three architectures with LGD=15μm State characteristic curve. The breakdown voltage is defined as the voltage at which the drain current is 10-6A/mm in the off state. The simulated breakdown voltage of C-high electron mobility transistor is 868.3V, the simulated breakdown voltage of FPC-high electron mobility transistor is 1546.6V, and the simulated breakdown voltage of EJ-HMT is 2050V. In terms of using field plates, the breakdown capability of C-high electron mobility transistors has undoubtedly been improved. And the built-in PN junction helps the FPC-high electron mobility transistor to further improve the breakdown characteristics. The simulated breakdown voltage of the FPC-high electron mobility transistor was increased by 32.54%.

The lateral electron density distribution in the 2D electron gas is shown in Fig. 6. In order to be consistent with the experimental results, a 4.8×1012cm-3 trap was set on the surface of the AlGaN/GaN heterojunction, and its two-dimensional electron gas density N was 1.25×1019cm-3. The doping concentration of the P-type layer is 1×1017cm-3, which is enough to deplete the extra charge generated by the N-type layer. The two-dimensional electron gas in the P-type layer region is replaced by the P-type layer. The P-type layer is embedded in the N-type layer, thereby cutting off the two-dimensional electron gas portion between the gate and the drain. The doping concentration of the N-type layer is 1×1019cm-3, which is close to the two-dimensional electron gas density (N two-dimensional electron gas). Although part of the 2D electron gas is replaced by the N-type layer and the P-type layer, the distance from the N-type layer to the P-type layer (LPN) of 0.01 μm is still suitable for achieving low channel resistance.

Fig. 7 compares the drain current curves of FPC-high electron mobility transistor and EJ-high electron mobility transistor at VDS=10V and VGS=2, 4, 6, 8 and 10V. We see that the current of the EJ-HEM transistor is almost the same as that of the FPC-HEM transistor. The output characteristics of GaN-based electronic devices mainly depend on the density of the two-dimensional electron gas and the channel current density. FPC-High Electron Mobility Transistor and EJ-High Electron Mobility Transistor have similar channel current densities. For EJ - High Electron Mobility Transistors, a highly doped N-type layer is used instead of part of the 2D electron gas region. The concentration of the N-type layer is close to the density of the two-dimensional electron gas, which leads to a similar on-current. The RON of EJ-HMT is 15.37Ωmm, which is slightly higher than 14.98Ωmm of FPC-high electron mobility transistor. FIG. 8 compares the transfer characteristic curves of FPC-high electron mobility transistor and EJ-high electron mobility transistor at VDS=1V. The threshold voltage of both structures is about 1.7 V, and the threshold voltage is defined as IDS = 0.01 mA/mm. It is well known that the threshold voltage of GaN high electron mobility transistor structures is mainly determined by the thickness of the gate dielectric and the space charge under the gate electrode. The proposed EJ-high electron mobility transistor structure does not have any effect on the thickness of the gate dielectric and the space charge under the gate electrode. Therefore, EJ-high electron mobility transistors do not change the structure transfer properties. The EJ-high electron mobility transistor structure uses a highly doped N-type layer to replace part of the two-dimensional electron gas, and the current density between the gate and drain is slightly reduced.

To obtain the best Baliga figure of merit (BFOM, defined as VBK2/RON) for EJ-high electron mobility transistors, we simulated RON with different N-type layer doping concentrations (NN+) and showed the corresponding VBK and RON. Figure 9 presents the results obtained. It can be seen that as the doping concentration of the N-type layer increases, the value of RON decreases. With the increase of N-type layer doping, the trend of VBK first increases and then decreases. When NN+ is set to 6×1018cm-3, RON reaches the maximum value. As the doping of the N-type layer increases, the RON value gradually decreases. When the doping of the N-type layer reaches 1×1019cm-3, the simulated device breakdown voltage reaches the maximum value of 2050V, and the BFOM tends to the maximum value, and rises to the value of 2.734GW cm-2. As a result, a peak of BFOM was generated at NN+=1×1019 cm-3. When NN+ is set to 1×1019cm-3, the distance from the gate to the N-type layer (LGN) can be optimized. Figure 10 plots the optimized EJ-high electron mobility transistors for each LGN and the corresponding VBK and RON for different LGNs. When the length of LGN is set to 4um, VBK keeps minimum 1500V. As LGN increases, VBK increases in a quasi-linear manner during the simulation. When the length of LGN is set to 13um, VBK reaches a maximum of 2050V. The trend of the corresponding calculated RON remains within a narrow range, while the trend of the optimized BFOM is consistent with that of the optimized VBK. When LGN=13um, our maximum BFOM is 2.734GWcm-2, and NN+=1.0×1019cm-3.

Figure 11 presents the optimization of each WN and the corresponding VBK and RON of the EJ-high electron mobility transistor. As WN increases, the breakdown voltage also increases. When WN=1.5μm, the breakdown voltage reaches the saturation value of 2050V. With the increase of WN, the N-type layer gathers more 2D electron gas, and the RON gradually increases. Figure 12 presents the optimized EJ-high electron mobility transistors for each HN and the corresponding VBK and RON. The breakdown voltage and RON of N-type devices decreased with the increase of HN.

Figure 12 presents the optimized EJ-high electron mobility transistors for each HP and the corresponding VBK and RON. With the increase of HP, the breakdown voltage first increases and then decreases. The greater the HP, the lower the HN, resulting in an increase in RON with increasing HP. When HP=31nm, the breakdown voltage reaches the maximum value of 2050V. Figure 13 presents the optimized EJ-high electron mobility transistors for each NP and the corresponding VBK and RON. With the increase of NP, the breakdown voltage increases slightly at first and then decreases. When increasing NP, RON keeps rising. When increasing the doping concentration of the P-type layer, more N-type layer will be depleted and the breakdown voltage fluctuation is kept within a small range of voltage margin.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (2)

1. Built-in PN junction silicon-based high-voltage enhancement-mode gallium nitride transistor, which is characterized in that it includes a silicon substrate, a transition layer, a buffer layer, and a barrier layer, and the embedded junction formed by the built-in N-type layer and P-type layer is in the barrier A PN junction is formed in the layer and the buffer layer, a part of the two-dimensional electron gas is replaced by a highly doped N-type layer, and the P-type layer is embedded in the N-type layer; from bottom to top are the silicon substrate, the transition layer, and the buffer layer , barrier layer; the barrier layer is an aluminum gallium nitride barrier layer, silicon dioxide is formed on the aluminum gallium nitride barrier layer as an etching mask, and then the aluminum gallium nitride barrier layer and the gallium nitride buffer layer are etched Layer, the N-type layer and P-type layer are regrown by molecular beam epitaxy crystal growth technology, and a silicon dioxide mask is deposited on top of the P-type layer to form an N-type layer as a passivation layer formed by plasma-enhanced chemical vapor deposition. Silicon nitride and gate grooves are etched by inductively coupled plasma, and silicon nitride is deposited as a gate dielectric to form a pure resistance of the source and drain electrodes, and the built-in PN junction formed is located at the gate and drain between. 2. A method for manufacturing a silicon-based high-voltage enhancement mode gallium nitride transistor with a built-in PN junction, characterized in that the manufacturing steps of a silicon-based high-voltage enhancement mode gallium nitride transistor with a built-in PN junction are as follows: (a) A transition layer is grown on a silicon substrate, and then a buffer layer and an aluminum gallium nitride barrier layer are sequentially grown on the transition layer by metal-organic chemical vapor deposition; (b) forming silicon dioxide as an etch mask by using plasma-enhanced chemical vapor deposition; (c) Etching the AlGaN barrier layer and the GaN buffer layer by transformer-coupled plasma reactive ion etching with a mixture of boron trichloride and chlorine; (d) A combination of ultraviolet ozone cleaning and wet etching of hydrogen fluoride and hydrochloric acid is used to reduce the concentration of impurities on the etched surface, and the N-type layer and P-type layer are re-grown by molecular beam epitaxy crystal growth technology; (e) A silicon dioxide mask is deposited on top of the P-type layer using plasma-enhanced chemical vapor deposition, and an N-type layer is formed by silicon ion implantation, with a built-in PN junction between the gate and drain; (f) After implantation, the silicon dioxide mask was removed using hydrofluoric acid, followed by a post-implantation anneal to activate the implanted silicon and remove the native oxide on the sample surface using an in-situ remote plasma pretreatment technique, and the surface Minimal damage and deposition of silicon nitride as a passivation layer via plasma enhanced chemical vapor deposition; (g) dry etching by low power inductively coupled plasma, specifically silicon nitride and gate grooves by inductively coupled plasma; (h) depositing silicon nitride as a gate dielectric by using plasma enhanced chemical vapor deposition; (i) Form the gate electrode, and form the pure resistance of the source and drain electrodes.