CN107706241A - A kind of normally-off GaNMOSFET structures at high quality MOS interfaces and preparation method thereof - Google Patents

Abstract

The invention relates to the technical field of semiconductor devices, in particular to a normally-off GaN MOSFET structure with a high-quality MOS interface and a preparation method thereof. The present invention utilizes a dense dielectric layer formed at the interface between the mask layer and GaN during the secondary epitaxial high-temperature growth process to effectively passivate the dangling bonds on the surface of the GaN material, and reduce the loss of Ga-O bonds in the subsequent process. further formed, thereby improving the performance of the device. The epitaxial layer includes a GaN epitaxial layer substrate grown by primary epitaxial growth, a non-doped GaN epitaxial layer and a heterojunction barrier layer grown by secondary epitaxial growth in selected regions. The groove gate is naturally formed when the material of the access region is grown by secondary epitaxial growth. The gate insulation dielectric layer covers the groove channel, the side wall and the surface of the secondary epitaxial layer, the source and drain regions are formed by etching the two ends of the insulation layer, and then the ohmic contact electrode is formed by metal evaporation. The invention utilizes the selective area epitaxy technique to prepare a trench gate MOS device with a high-quality interface, which obviously improves the stability of the threshold voltage of the device.

Description

A normally-off GaN MOSFET structure with high-quality MOS interface and its preparation method

technical field

The invention relates to the technical field of semiconductor devices, in particular to a normally-off GaN MOSFET structure with a high-quality MOS interface and a preparation method thereof.

Background technique

As a third-generation semiconductor material, GaN not only has the advantages of wide band gap, high thermal conductivity, and high critical breakdown field strength, but also has a high two-dimensional electron gas formed at its heterointerface. Concentration and larger saturation electron transfer velocity. Compared with Si materials, this type of material has greater advantages in making power electronic devices with high power and high switching speed, and has broad application prospects.

Due to the high concentration of 2DEG produced by the spontaneous polarization effect and piezoelectric polarization effect in the AlGaN/GaN heterojunction, this type of device has the characteristics of low on-resistance and high current density, and belongs to the normally-on device. To achieve normally off of this type of device, an additional negative gate voltage is required. However, in the field of power electronics and radio frequency amplification, normally-off devices have a wider range of applications. A circuit composed of normally-off devices can be powered by a single power supply, which simplifies the circuit and increases the reliability of the circuit.

At present, there are mainly two types of methods to realize the normally-off of GaN-based devices. One is the cascade method (cascode), but the high temperature resistance of this method is restricted by the Si device, and the device is more complex and the process cost is higher; the other is to control the heterojunction in the device process or epitaxial growth. 2DEG, so as to realize the normally off of the device, including thin AlGaN barrier layer method, groove etching method, etc. However, the thinned AlGaN barrier layer significantly increases the resistance of the access region, and the damage introduced by the groove etching method on the gate surface of the device and the access region will affect the stability and reliability of the device. There is obvious deterioration. In GaN-based MOS devices, the surface defect states near the channel, the interface states between the GaN interface and the gate dielectric layer, and the defect states inside the dielectric layer may generate a large number of traps, which will generate leakage current channels, resulting in The device cannot be completely turned off at zero gate bias. When these trap states are occupied by electrons, the Coulomb scattering generated by the charged traps will lead to a decrease in the electron mobility of the gate channel, thereby deteriorating the conduction performance of the device. When different switching biases are applied to the gate, electrons will be released or trapped by trap states, resulting in shifts in threshold voltage. Therefore, preparing a high-quality MOS gate interface is an important idea to solve the problem of device reliability.

In order to improve the gate interface quality of GaN devices with trench gate structures, many researchers have applied selective area epitaxy (HeZ, Li J, Wen Y, et al. Comparison of Two Types of Recessed-Gate Normally-OffAlGaN/GaN Heterostructure Field Effect Transistors[ J]. Japanese Journal of Applied Physics, 2012, 51(5):4103.). Our previous work found that compared with GaN MOSFETs prepared by conventional dry etching under the same conditions, the interface states of the selective-region epitaxial trench gate MOSFETs were greatly reduced, and the performance of the devices was greatly improved.

Contents of the invention

In order to overcome at least one defect described in the above prior art, the present invention provides a high-quality MOS interface normally-off GaN MOSFET structure and a preparation method thereof. The method has simple process and high stability. After applying this method to improve the interface quality of the device, the flat-band voltage hysteresis window of the C-V curve is obviously reduced.

The technical solution of the present invention is: the present invention adopts the selective area epitaxy method to prepare the above device, the selective growth access can naturally form the groove structure and the gate area can effectively avoid the etching process under the protection of the patterned _SiO2 mask. Damage to the GaN interface below the trench gate. In addition, using the high temperature in the secondary epitaxial growth process (in this embodiment, the growth temperature of the non-doped GaN layer is 1075°C, and the temperature of the heterojunction barrier layer is 1095°C), the interface between the mask layer and GaN can be formed A dense dielectric layer is formed, which effectively passivates the dangling bonds on the surface of the GaN material, and reduces the further formation of Ga-O bonds in the subsequent process. This will reduce the scattering rate at the interface and increase the mobility of the 2DEG.

A normally-off GaN MOSFET structure with a high-quality MOS interface, which includes epitaxially growing a layer of GaN epitaxial layer substrate on the substrate at one time, depositing a layer of mask material on the GaN epitaxial layer substrate and forming a patterned mask , use secondary epitaxy to grow non-doped GaN epitaxial layer and heterojunction barrier layer, remove the patterned mask and naturally form grooves, deposit a layer of gate insulating dielectric layer, the dielectric layer covers the groove channel, two On the side wall and the surface of the sub-epitaxial layer, a source electrode, a drain electrode and a gate electrode are formed by metal evaporation.

Further, the material of the substrate may be SiC, sapphire or Si, but not limited to this range.

The GaN epitaxial layer substrate includes a stress buffer layer and a GaN layer. The stress buffer layer can be any one or combination of AlN, AlGaN, and GaN, and its thickness is between 100 nm and 10 μm. The GaN layer can be C or Fe A high-resistance layer formed by doping or an unintentionally doped epitaxial layer with a thickness between 100 nm and 10 μm.

The mask material can be SiO2, SiNx, Al ₂ O ₃ , AlN, HfO ₂ , MgO, Sc ₂ O ₃ , and its thickness is between 1nm and 100nm.

The thickness of the non-doped GaN layer is between 10 nm and 500 nm, and the heterojunction barrier layer can be any one or a combination of materials in AlGaN, AlInN, AlInGaN, AlN, InGaN, but Not limited to this range, its thickness is between 5nm and 50nm, and a 1nm to 10nm thick AlN layer is grown between the non-doped GaN epitaxial layer and the heterojunction barrier layer.

The material of the gate insulating dielectric layer can be any one of SiO2, Al2O3, Sc2O3, SiNx, AlN, HfO2, MgO, Ga2O3, HfSiON, AlHfOx, or a stacked combination of multiple materials, with a thickness between 1nm to 100nm.

The source and drain materials can be metals or alloys capable of ohmic contact, such as Ti/Al/Ti/Au alloys, Ti/Al/Mo/Au alloys, Ti/Al/Ni/Au alloys, etc.; The material of the grid can be one of Ni/Au alloy, Pd/Au alloy and Pt/Al alloy.

A method for preparing a normally-off GaN MOSFET structure with a high-quality MOS interface, wherein: comprising the following steps:

S1, growing a GaN epitaxial layer substrate on the Si substrate;

S2, forming a SiO2 mask dielectric layer on the GaN epitaxial layer;

S3. Using photolithography technology, selectively retain the SiO2 mask dielectric layer above the gate region;

S4. Perform secondary epitaxy on both sides of the SiO2 mask dielectric layer, and selectively grow a non-doped GaN layer and a heterojunction barrier layer in a high-temperature environment, thereby forming the groove structure described above;

S5, removing the SiO2 mask dielectric layer above the gate region;

S6. Depositing a gate insulating dielectric layer on the exposed groove channel and the heterojunction;

S7, performing metal evaporation on the source and drain regions;

S8, forming patterns of source and drain electrodes through a lift-off process;

S9. Evaporating metal on the gate insulating dielectric layer in the grooved gate region;

S10 , forming a pattern of the gate electrode through a lift-off process.

The GaN epitaxial layer in S1, the non-doped GaN layer and the heterojunction barrier layer in S4 can be grown by molecular beam epitaxy or metal organic chemical vapor deposition; the S6 can be grown by inductively coupled plasma etching etching technology; the growth method of the SiO2 mask dielectric layer in S2 and the gate dielectric layer in S7 can be atomic layer deposition, magnetron sputtering, plasma enhanced chemical vapor deposition or physical vapor deposition, etc. .

In S8, after the evaporation of the source and drain is completed, rapid annealing needs to be performed in an environment filled with nitrogen, so as to form an ohmic contact with sufficiently low resistance; in S9, no annealing process is required.

Compared with the prior art, the beneficial effect is: the device prepared by this method has a flat-band voltage hysteresis window of 0.12V in the C-V curve of the MOS interface, while GaN on sapphire prepared by conventional dry etching under the same conditions The hysteresis window of the flat-band voltage of the MOS interface reached 0.85V (V=6V, f=100kHz). In comparison, the devices prepared by this method showed better threshold voltage stability. This phenomenon shows that selective area epitaxy Trench gate MOS diodes have better MOS interface quality.

Description of drawings

1-8 are process schematic diagrams of the device manufacturing method in Example 1 of the present invention.

Figure 9 is a comparison chart of the flat-band voltage hysteresis window in the C-V curve of the device prepared by the present invention and the GaN MOSFET prepared by dry etching under the same conditions.

detailed description

The accompanying drawings are for illustrative purposes only, and should not be construed as limitations on this patent; in order to better illustrate this embodiment, certain components in the accompanying drawings will be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art It is understandable that some well-known structures and descriptions thereof may be omitted in the drawings. The positional relationship described in the drawings is for illustrative purposes only, and should not be construed as a limitation on this patent.

Example 1

The device structure of this embodiment 1 consists of a substrate 1, a GaN layer substrate 2, an undoped GaN layer 3, a heterojunction barrier layer 4, a gate dielectric layer 5 covering the groove, a groove gate 8, A source 6 and a drain 7 located on both sides of the gate are formed, as shown in FIG. 8 .

The preparation scheme of the normally-off GaN MOSFET of the high-quality MOS interface is shown in Figures 1 to 8, and the steps are as follows:

S1. Using a metal organic chemical vapor deposition method, a stress buffer layer 11 and a GaN layer 12 are grown on the Si substrate, and the two form a GaN layer substrate 2, as shown in FIG. 1 ;

S2. On the GaN epitaxial layer, a layer of SiO2 mask dielectric layer 9 is grown by plasma-enhanced chemical vapor deposition, as shown in FIG. 2 ;

S3. Using photolithography technology, selectively retain the SiO2 mask dielectric layer 10 above the gate region, and remove the rest, as shown in FIG. 3 ;

S4. On the substrate with the SiO2 mask dielectric layer, the metal-organic chemical vapor deposition method is used to perform selective area epitaxy, and the non-doped GaN layer 3 and the heterojunction barrier layer 4 are grown in sequence, thereby forming grooves, As shown in Figure 4;

S5, remove the SiO2 mask dielectric layer 10 in the gate area in Figure 4 by wet method with acid solution, as shown in Figure 5;

S6. On the structure shown in FIG. 5 , grow a layer of high-k dielectric layer 5 as the dielectric layer of the gate by using atomic layer deposition (ALD), as shown in FIG. 6 ;

S7. Etching both ends of the gate insulating dielectric layer to form a source region and a drain region, as shown in FIG. 7 ;

S8. Evaporation of ohmic contact electrodes is carried out in the source region and the drain region. After the evaporation is completed, the source electrode 6 and the drain electrode 7 are formed by a lift-off process. The metal material used is a Ti/Al/Ni/Au stack, such as As shown in Figure 8;

S9. After the evaporation of the source and drain is completed, rapid annealing is required in an environment filled with nitrogen to form an ohmic contact with sufficiently low resistance;

S10. Perform metal vapor deposition on the gate insulating dielectric layer in the grooved gate area, the alloy material used is Ni/Au alloy, and then form the metal gate electrode 8 by lift-off process, as shown in FIG. 8 .

So far, the preparation process of a normally-off GaN MOSFET with a high-quality MOS interface has been completed.

Fig. 9 is a comparison chart of C-V curves between the device prepared by the present invention and the GaN MOSFET prepared by dry etching under the same process conditions. (a) is the C-V characteristic curve of the selected area epitaxial trench gate GaN MOS diode. (b) is the C-V characteristic curve of GaN MOS diode on dry-etched sapphire.

Apparently, the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, rather than limiting the implementation of the present invention. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. All modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the claims of the present invention.

Claims (10)

1. the normally-off GaN MOSFET structures at a kind of high quality MOS interfaces, it is characterised in that be included in substrate（1）It is last One layer of GaN epitaxial layer substrate of epitaxial growth（2）, in GaN epitaxial layer substrate（2）One layer of mask material of upper deposition（9）And form figure The mask of shape（10）, grow undoped GaN epitaxial layer using secondary epitaxy（3）, potential barrier of heterogenous junction layer（4）, remove graphical Mask（10）And self-assembling formation groove, deposit one layer of gate insulation dielectric layer（5）, the dielectric layer is covered in recess channel, secondary outer Prolong on the side wall and surface of layer, source electrode is formed by metal evaporation（6）And drain electrode（7）And grid（8）.

A kind of 2. normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 1, it is characterised in that： Described substrate（1）Material can be SiC, sapphire or Si, but not limited to this scope.

A kind of 3. normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 1, it is characterised in that： Described GaN epitaxial layer substrate（2）Including stress-buffer layer（11）, GaN layer（12）, stress-buffer layer can be AlN, AlGaN, GaN any or combination, for its thickness between 100 nm to 10 μm, GaN layer can be that C or Fe adulterates the high resistant to be formed Layer or the epitaxial layer of unintentional doping, its thickness is between 100 nm to 10 μm.

A kind of 4. normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 1, it is characterised in that： Described mask material（9）SiO2, SiNx, Al can be used₂O₃、AlN、HfO₂、MgO、Sc₂O₃, its thickness between 1nm extremely 100nm 。

A kind of 5. normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 1, it is characterised in that： Described undoped GaN layer（3）Thickness between 10 nm between 500nm, described potential barrier of heterogenous junction layer（4）Can be The combination of any one or more material in AlGaN, AlInN, AlInGaN, AlN, InGaN, but not limited to this scope, its thickness Between 5nm between 50nm, in undoped GaN epitaxial layer（3）With potential barrier of heterogenous junction layer（4）Between also grow one layer of 1nm extremely AlN layers thick 10nm.

A kind of 6. normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 1, it is characterised in that： Described gate insulator dielectric layer（5）Material can be SiO2, Al2O3, Sc2O3, SiNx, AlN, HfO2, MgO, Ga2O3, Any one material in HfSiON, AlHfOx, or the stacked combination of many of material, thickness is between 1nm between 100nm.

A kind of 7. normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 1, it is characterised in that： Described source electrode（6）, drain electrode（7）Material can be that by the metal or alloy of Ohmic contact, such as Ti/Al/Ti/Au is closed Gold, Ti/Al/Mo/Au alloys, Ti/Al/Ni/Au alloys etc.；The grid（8）Material can be Ni/Au alloys, Pd/Au close One kind among gold, Pt/Al alloys.

8. the preparation method of the normally-off GaN MOSFET structures at the high quality MOS interfaces described in claim 1, its feature exist In：Comprise the following steps：

S1, Si substrates grow GaN epitaxial layer substrate（2）；

S2, SiO2 mask medium layers are formed in GaN epitaxial layer（9）；

S3, using photoetching technique, the SiO2 mask medium layers above selective retention area of grid（10）；

S4, in the both sides of SiO2 mask medium layers carry out secondary epitaxy, the under the high temperature conditions undoped GaN layer of growth selection （3）And potential barrier of heterogenous junction layer（4）, so as to form groove structure described above；

S5, by above area of grid SiO2 mask medium layers remove；

S6, gate insulator dielectric layer is deposited on exposed recess channel and on hetero-junctions（5）；

S7, in source electrode and drain region carry out metal evaporation；

S8, pass through stripping technology, formation source electrode（6）And drain electrode（7）The figure of electrode；

The enterprising row metal evaporation of S9, the gate insulator dielectric layer in groove grids region；

S10, pass through stripping technology, formation gate electrode（8）Figure.

9. the preparation method of the normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 8, its feature It is：The undoped GaN layer in GaN epitaxial layer and S4, potential barrier of heterogenous junction layer in the S1 can use molecular beam epitaxy Method or Metalorganic Chemical Vapor Deposition growth；The S6 can use inductive coupling type plasma etching technology；The S2 In SiO2 mask medium layers and the gate dielectric layer in S7 growing method can use atomic layer deposition method, magnetron sputtering method, Plasma enhanced chemical vapor deposition method or physical vaporous deposition etc..

10. the preparation method of the normally-off GaN MOSFET structures at high quality MOS interfaces according to claim 8, it is special Sign is：In the S8, source electrode（6）And drain electrode（7）Evaporation complete after, it is necessary to be carried out in the environment full of nitrogen quick Annealing, so as to form the sufficiently low Ohmic contact of resistance；The S9 need not carry out annealing process.