CN114334874B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN114334874B CN114334874B CN202011056478.8A CN202011056478A CN114334874B CN 114334874 B CN114334874 B CN 114334874B CN 202011056478 A CN202011056478 A CN 202011056478A CN 114334874 B CN114334874 B CN 114334874B
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- 238000000034 method Methods 0.000 title claims abstract description 85
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000000463 material Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 19
- 238000000231 atomic layer deposition Methods 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 346
- 230000015572 biosynthetic process Effects 0.000 description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 10
- 239000001301 oxygen Substances 0.000 description 10
- 229910052760 oxygen Inorganic materials 0.000 description 10
- 239000007789 gas Substances 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 2
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 238000009413 insulation Methods 0.000 description 1
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Abstract
The invention provides a semiconductor device and a forming method thereof, wherein the semiconductor device comprises: a substrate; a conductive layer within the substrate; an oxide layer on a portion of the surface of the substrate; the high-resistance layer is positioned on the oxide layer; the dielectric layer is positioned on the substrate and the high-resistance layer; the first through hole is positioned in the dielectric layer, and the bottom of the first through hole exposes the top surface of the conductive layer; the second through hole is positioned in the dielectric layer, and the bottom of the second through hole exposes the top surface of the oxide layer; the connecting layer is positioned in the first through hole; the adhesion layer is positioned on the surface of the dielectric layer, the surface of the connecting layer and the side wall and the bottom of the second through hole; a metal layer located on the adhesion layer and filling the second through hole; the formed semiconductor device is ensured to have higher quality.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. The device is used as the most basic semiconductor device, is widely applied at present, the control capability of the traditional planar device on channel current is weakened, short channel effect is generated to cause leakage current, and the electrical property of the semiconductor device is finally affected.
In the manufacturing process of a semiconductor device, a contact hole is required to be formed in a source region, a drain region or a gate structure of a transistor, and the like, then a conductive material is filled in the contact hole to form a conductive layer, after the conductive layer is formed, a connection layer is formed on the conductive layer and the high-resistance layer by using a selective growth process, and the transistor is electrically connected with the outside by using the connection layer. However, the heights of the connection layers formed on the high-resistance layer and the conductive layer are different, so that various connection modes appear on the connection layers on the high-resistance layer, and the connection line on the high-resistance layer is greatly changed finally, so that different interface problems and yield problems appear between the metal layer and the connection layer in the process of forming the metal layer on the connection layer on the high-resistance layer, and the use of the semiconductor device is limited.
How to realize the use of a connection layer selectively grown on a conductive layer while improving the quality of a metal layer and a connection layer formed on the high-resistance layer, thereby improving the performance of the final semiconductor device formed, is an urgent problem to be solved at present.
Disclosure of Invention
The invention solves the problem of providing a semiconductor device and a forming method thereof, which ensure that the formed semiconductor device has higher quality.
In order to solve the above-described problems, the present invention provides a semiconductor device including: a substrate; a conductive layer within the substrate; an oxide layer on a portion of the surface of the substrate; the high-resistance layer is positioned on the oxide layer; the dielectric layer is positioned on the substrate and the high-resistance layer; the first through hole is positioned in the dielectric layer, and the bottom of the first through hole exposes the top surface of the conductive layer; the second through hole is positioned in the dielectric layer, and the bottom of the second through hole exposes the top surface of the oxide layer; the connecting layer is positioned in the first through hole; the adhesion layer is positioned on the surface of the dielectric layer, the surface of the connecting layer and the side wall and the bottom of the second through hole; and the metal layer is positioned on the adhesion layer and is filled with the second through hole.
Optionally, the thickness of the oxide layer isTo the point of
Optionally, the etching selectivity ratio of the oxide layer to the high-resistance layer is less than 1.
Optionally, the material of the oxide layer is silicon oxide or silicon nitride.
Correspondingly, the invention also provides a method for forming the semiconductor device, which comprises the following steps: providing a substrate, wherein an oxide layer and a high-resistance layer positioned on the oxide layer are formed on part of the surface of the substrate; forming a dielectric layer on the surface of the high-resistance layer and the surface of the substrate uncovered by the oxide layer and the high-resistance layer; and etching the dielectric layer to form a first through hole and a second through hole in the dielectric layer, wherein the bottom of the first through hole exposes the top surface of the conductive layer in the substrate, and the bottom of the second through hole exposes the top surface of the oxide layer.
Optionally, the oxide layer forming process is an atomic layer deposition process or a chemical vapor deposition process.
Optionally, the thickness of the oxide layer isTo the point of
Optionally, the etching selectivity ratio of the oxide layer to the high-resistance layer is less than 1.
Optionally, after forming the first through hole and the second through hole, a connection layer is formed in the first through hole.
Optionally, after forming the connection layer, forming an adhesion layer on the dielectric layer, on the connection layer, and on the sidewall and the bottom of the second through hole; and forming a metal layer on the adhesion layer, wherein the metal layer fills the second through hole.
Optionally, the material of the oxide layer is silicon oxide or silicon nitride.
Compared with the prior art, the technical scheme of the invention has the following advantages:
In the semiconductor device, the bottom of the first through hole exposes the top surface of the conductive layer, the bottom of the second through hole exposes the top surface of the oxide layer, the first through hole is internally provided with the connecting layer, the adhesive layer is positioned on the surface of the dielectric layer, the surface of the connecting layer and the side wall and the bottom of the second through hole, and the metal layer is positioned on the adhesive layer and fills the second through hole, so that the problem that the growth heights of the connecting layers are different is avoided in the second through hole due to the fact that the connecting layer does not exist in the second through hole, the problem that the interface between the connecting layer and the metal layer is uneven or defective is thoroughly eliminated in the second through hole, the quality of the metal layer formed in the second through hole is improved, the performance of the finally formed semiconductor device is improved, and the application range of the semiconductor device is enlarged.
According to the forming method, an oxide layer and a high-resistance layer positioned on the oxide layer are formed on part of the surface of a substrate, a dielectric layer is formed on the surface of the high-resistance layer and the surface of the substrate which is not covered by the oxide layer and the high-resistance layer, the dielectric layer is etched, a first through hole and a second through hole are formed in the dielectric layer, the bottom of the first through hole exposes the top surface of a conductive layer in the substrate, and the bottom of the second through hole exposes the top surface of the oxide layer; due to the presence of the oxide layer. In the subsequent process of forming the connecting layer in the first through hole, the connecting layer cannot be formed at the bottom of the second through hole, so that the problem of uneven growth height of the connecting layer does not exist in the second through hole, meanwhile, the problem of interface difference does not exist in the high-resistance layer, the metal layer is directly formed in the second through hole, the quality of the interface formed by the metal layer in the second through hole can be improved, the performance of a finally formed semiconductor device is improved, and the application range of the semiconductor device is expanded.
Drawings
Fig. 1 to 3 are schematic structural views of a semiconductor device forming process in one embodiment;
fig. 4 to 8 are schematic structural views of a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
In the formation of the semiconductor device, after the formation of the conductive layer, a connection layer is required to be formed on the conductive layer, and connection between the transistor and an external circuit is achieved by using the connection layer to form a connection with the upper metal layer 1 (M1). In the process of forming the connecting layer on the conductive layer, the connecting layer can be grown simultaneously on the high-resistance layer, however, the problem of uneven growth of the connecting layer on the high-resistance layer can occur in the process of growing the connecting layer or the problem that the high-resistance layer at the bottom can be carved through in the process of growing the connecting layer can occur, so that the subsequent process of forming the metal layer on the high-resistance layer can be caused, various different connecting modes can occur in the process of connecting wires due to the connection difference between the metal layer and the through holes, and finally, the difference of electrical properties is caused, the performance of a semiconductor device is influenced, and the application range of the semiconductor device is limited.
Referring first to fig. 1, a substrate 100 is provided, an etch stop layer 101 is formed on the substrate 100, a high-resistance layer 102 is formed on a part of the surface of the etch stop layer 101, a dielectric layer 103 is formed on the etch stop layer 101 and the high-resistance layer 102, the dielectric layer 103 and the etch stop layer 101 at the bottom of the dielectric layer 103 are etched, a first via 104 and a second via 105 are formed, the bottom of the first via 104 exposes the top surface of a conductive layer 106 in the substrate 100, and the bottom of the second via 105 exposes the top surface of the high-resistance layer 102.
Referring to fig. 2, fig. 2 includes fig. 2a and fig. 2b, a connection layer 107 is formed in the first via 104, and the connection layer 107 is formed in the second via 105 during the formation of the connection layer 107.
Referring to fig. 3, wherein fig. 3 includes fig. 3a and 3b, an adhesion layer 108 is formed, and a metal layer 109 is formed on the adhesion layer 108.
Fig. 3a is a structural view of the metal layer 109 formed on the basis of fig. 2a, and fig. 3b is a structural view of the metal layer 109 formed on the basis of fig. 2 b.
Referring to fig. 3a, the adhesion layer 108 is formed on the surface of the dielectric layer 103, the surface of the connection layer 107 in the second via 105, and the sidewall of the second via 105, and the metal layer 109 is formed on the adhesion layer 108.
Referring to fig. 3b, the adhesion layer 108 is formed on the sidewall of the etched high-resistance layer 102, the bottom of the second via 105 and the sidewall, and the metal layer 109 is formed on the adhesion layer 108.
The inventors found that during the process of forming the connection layer 107 in the second via 105, different growth conditions occur in different areas, and that two conditions may occur, one is that, as shown in fig. 2a, the connection layer 107 with uneven surface height is formed in the second via 105; secondly, as shown in fig. 2b, in the process of forming the connection layer 107, the connection layer 107 etches away the high-resistance layer 102 at the bottom, which results in inconsistent interface of the etched high-resistance layer 102, so that in the process of forming the metal layer 109, the formation quality of the metal layer 109 in the second through hole 105 is greatly different, and in this way, during performance test, great electrical difference is easy to occur, which affects the performance of the finally formed semiconductor device, and limits the use of the semiconductor device.
The inventor researches and finds that an oxide layer and a high-resistance layer positioned on the oxide layer are formed on part of the surface of the substrate, a dielectric layer is formed on the surface of the high-resistance layer and the surface of the substrate which is not covered by the oxide layer and the high-resistance layer, the dielectric layer is etched, a first through hole and a second through hole are formed in the dielectric layer, the bottom of the first through hole exposes the top surface of the conductive layer in the substrate, and the bottom of the second through hole exposes the top surface of the oxide layer; due to the presence of the oxide layer. In the subsequent process of forming the connecting layer in the first through hole, the connecting layer cannot be formed at the bottom of the second through hole, so that the problem of uneven growth height of the connecting layer does not exist in the second through hole, meanwhile, the problem of interface difference does not exist in the high-resistance layer, the metal layer is directly formed in the second through hole, the quality of the interface formed by the metal layer in the second through hole can be improved, the performance of a finally formed semiconductor device is improved, and the application range of the semiconductor device is expanded.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Referring first to fig. 4, a substrate 200 is provided, and an oxide layer 201 and a high-resistance layer 202 on the oxide layer 201 are formed on a portion of the surface of the substrate 200.
In this embodiment, the substrate 200 has a conductive layer 203 therein.
In this embodiment, the base 200 further includes a substrate, and the conductive layer 203 is located on the substrate and includes a memory device, a logic device, and the like on the substrate.
In this embodiment, the conductive layer 203 is a metal layer, and is formed above the source-drain doped layer, so as to electrically connect the source-drain doped layer with the outside.
In this embodiment, the material of the conductive layer 203 is cobalt (Co); in other embodiments, the material of the conductive layer 203 may also be a metal material such as copper, aluminum, etc.
In this embodiment, the step of forming the oxide layer 201 and the high-resistance layer 202 on the oxide layer 201 on a part of the surface of the substrate 200 includes: an initial oxide layer (not shown) is formed on the surface of the substrate 200, an initial high-resistance layer (not shown) is formed on the initial oxide layer, the initial oxide layer and the initial high-resistance layer above the conductive layer 203 are etched away, and an oxide layer 201 and a high-resistance layer 202 on the oxide layer 201 are formed on a part of the surface of the substrate 200.
In this embodiment, before the initial oxide layer is formed, an etching stop layer 204 is formed on the surface of the substrate 200, where the purpose of the etching stop layer 204 is to protect the conductive layer 203 and the top surface of the substrate 200 from being damaged during the process of etching to remove the initial oxide layer and the initial high-resistance layer above the conductive layer 203.
In this embodiment, the material of the etching stop layer 204 is tungsten nitride or aluminum nitride or silicon nitride.
In this embodiment, the material of the oxide layer 201 is silicon oxide.
In other embodiments, the material of the oxide layer 201 may also be silicon nitride.
In this embodiment, the forming process of the oxide layer 201 is an atomic layer deposition process or a chemical vapor deposition process.
When the material of the oxide layer 201 is silicon nitride, the process of forming the oxide layer 201 is an atomic layer deposition process.
When the atomic layer deposition process is used in the formation process of the oxide layer 201, specific process parameters include: SAM24 and oxygen are adopted as raw materials, wherein the flow rate of the oxygen is 0 to 10slm; the reaction temperature is 150-450 ℃.
When the chemical vapor deposition process is adopted in the process of forming the oxide layer 201, specific process parameters include: TEOS and oxygen are used as raw materials, wherein the flow rate of the oxygen is 500 sccm-1500 sccm, and the reaction temperature is 150-450 ℃.
In this embodiment, the purpose of forming the oxide layer 201 is to make use of the insulation property of the oxide layer 201 in the subsequent process of forming the connection layer, so that the connection layer cannot grow on the oxide layer 201 and the connection layer cannot etch the oxide layer 201 in the process of growing, thereby ensuring the surface property of the oxide layer 201.
In this embodiment, the oxide layer 201 has a thickness ofTo the point ofWhen the thickness of the oxide layer 201 is smaller thanWhen the thickness of the oxide layer 201 is too thin, the risk of etching through easily occurs; when the thickness of the oxide layer 201 is greater thanThe thickness of the oxide layer 201 formed at this time is too thick, so that the amount of the metal layer that can be formed in the second via hole is small, and then the risk of exposing the oxide layer 201 during planarization is liable to occur, which affects the performance of the semiconductor device formed.
In this embodiment, after the oxide layer 201 is formed, the high-resistance layer 202 is formed.
In this embodiment, the material of the high-resistance layer 202 is TiN.
In other embodiments, the material of the high-resistance layer 202 may be one or more of TiN, taN, tiO 2, WN, or WSi.
In this embodiment, the etching selectivity of the oxide layer 201 to the high-resistance layer 202 is less than 1.
In this embodiment, since the etching selectivity of the oxide layer 201 to the high-resistance layer 202 is less than 1, it is ensured that only the high-resistance layer 202 is etched in the subsequent process of etching the high-resistance layer 202, and the surface of the oxide layer 201 is not damaged.
In the present embodiment, a protective layer is not formed on the surface of the high-resistance layer 202; in other implementations, a protective layer may also be formed on the surface of the high-resistance layer 202, serving to protect the high-resistance layer 202.
Referring to fig. 5, a dielectric layer 205 is formed on the surface of the high-resistance layer 202 and the surface of the substrate 200 not covered by the oxide layer 201 and the high-resistance layer 202.
In this embodiment, the material of the dielectric layer 205 is silicon oxide.
In other embodiments, the material of the dielectric layer 205 may be silicon nitride, silicon nitride boride, silicon oxycarbide, or silicon oxynitride.
In this embodiment, the dielectric layer 205 is formed by chemical vapor deposition, and the process parameters of the chemical vapor deposition include oxygen, ammonia (NH 3) and N (SiH 3)3), wherein the flow rate of the oxygen is 20 sccm-10000 sccm, the flow rate of the ammonia (NH 3) is 20 sccm-10000 sccm, the flow rate of the N (SiH 3)3) is 20 sccm-10000 sccm, the chamber pressure is 0.01-10 torr, and the temperature is 30-90 ℃.
Referring to fig. 6, the dielectric layer 205 is etched, and a first via 206 and a second via 207 are formed in the dielectric layer 205, wherein the bottom of the first via 206 exposes the top surface of the conductive layer 203 in the substrate 200, and the bottom of the second via 207 exposes the top surface of the oxide layer 201.
In the present embodiment, the process of forming the first via 206 and the second via 207 is a dry etching process; in other embodiments, the first via 206 and the second via 207 may also be formed using a wet etching process.
In this embodiment, the parameters of the dry etching process include: the adopted gas comprises CF 4 and CH 3F,CF4 with the flow rate of 20 sccm-200 sccm, CH 3 F with the flow rate of 20 sccm-50 sccm, the source radio frequency power of 200W-500W and the chamber pressure of 1 torr-10 torr.
In the present embodiment, the reason why the dry etching process is adopted is that the etching rate in the longitudinal direction is greater than the etching rate in the lateral direction during the etching, so that the influence on the lateral cross section of the first via 206 and the second via 207 can be reduced during the formation of the first via 206 and the second via 207.
In this embodiment, the first via 206 is formed to provide a space for forming a connection layer on the surface of the conductive layer 203 later.
Referring to fig. 7, after the first via 206 and the second via 207 are formed, a connection layer 208 is formed in the first via 206.
In this embodiment, the connection layer 208 is made of a metal material, which plays a role in connection, and can realize electrical connection between the transistor and the outside when external power is subsequently connected.
In this embodiment, the material of the connection layer 208 is tungsten; in other embodiments, the material of the connection layer 208 may also be other metals, such as copper, aluminum, silver, and the like.
In this embodiment, the process of forming the connection layer 208 is a selective growth process; in other embodiments, the connection layer 208 may also be formed using a chemical vapor deposition process, an atomic layer deposition process, or the like.
In this embodiment, the reason why the selective growth process is used to form the connection layer 208 is that the selective growth process can enable the connection layer 208 to be formed to grow gradually upwards from the top surface of the conductive layer 203, on one hand, it is guaranteed that the connection layer 208 is formed to have good compactness, on the other hand, since the connection layer 208 is not formed in excess on the dielectric layer 205 because the connection layer is grown from the top of the conductive layer 203, so that the excess connection layer 208 is not removed in a chemical mechanical polishing manner, the process flow is reduced, damage to the conductive layer 203 in the chemical mechanical polishing process is reduced, and the quality of the finally formed semiconductor device is improved.
In this embodiment, due to the presence of the oxide layer 201 at the bottom of the second through hole 207, the connection layer 208 cannot be attached to the oxide layer 201 during the formation of the connection layer 208, and meanwhile, the oxide layer 201 is not damaged during the formation of the connection layer 208, so that the uniformity of the interface in the second through hole 207 is ensured, and the difference of the quality of the interface formed by the metal layer in the second through hole 207 is small after the metal layer is formed in the second through hole 207, so that the uniformity of the electrical property in the second through hole 207 is easily ensured during the performance test, the performance of the finally formed semiconductor device is ensured, and the application range of the semiconductor device is expanded.
Referring to fig. 8, after the connection layer 208 is formed, an adhesion layer 209 is formed on the dielectric layer 205, on the connection layer 208, and on the sidewalls and bottom of the second via 207; a metal layer 210 is formed on the adhesion layer 209, and the metal layer 210 fills the second via 207.
In this embodiment, the material of the adhesion layer 209 is titanium nitride (TiN); in other embodiments, the material of the adhesion layer 209 may also be TaN, etc.
In this embodiment, the surface of the connection layer 208 is planarized before the adhesion layer 209 is formed, until the plane of the connection layer 208 is flush with the surface of the dielectric layer 205.
In this embodiment, the adhesion layer 209 may be used as a transition layer, so as to provide a better formation interface for a subsequently formed metal layer, thereby improving the formation quality of the finally formed metal layer.
In this embodiment, the process of forming the adhesion layer 209 is an atomic layer deposition process; in other embodiments, the adhesion layer 209 may also be formed using chemical vapor deposition, physical vapor deposition processes, and the like.
In this embodiment, the reason why the adhesion layer 209 is formed by using an atomic layer deposition process is that the adhesion layer 209 formed by using an atomic layer deposition process has a good step coverage capability, so that uniformity and flatness of the adhesion layer 209 formed are good, and thus, differences in interface properties between materials formed in the second via 207 and the second via 207 are reduced, so that in the subsequent test process, differences in various properties do not occur, and uniformity of device performance in the second via 207 is improved, so that uniformity of performance of a finally formed semiconductor device is improved, and a use range of the semiconductor device is widened.
In this embodiment, the process of forming the metal layer 210 is a chemical vapor deposition process; in other embodiments, one or more combinations of selective growth processes, physical vapor deposition processes, atomic layer deposition processes, or chemical vapor deposition processes may also be employed.
In this embodiment, the material of the metal layer 210 includes tungsten.
In this embodiment, the process parameters for forming the metal layer 210 include: the reaction gas comprises WF 6 gas and H 2, wherein the gas flow rate of the WF 6 gas is 50-1000 sccm, and the gas flow rate of the H 2 gas is 500-20000 sccm; the reaction temperature is 100-400 ℃; the pressure of the chamber is 2-100 Torr.
After the metal layer 210 is formed, it is planarized so that the surface of the metal layer 210 is flush.
Correspondingly, the invention also provides a semiconductor device, which comprises: a substrate 200; a conductive layer 203 located within the substrate 200; an oxide layer 201 on a part of the surface of the substrate 200; a high-resistance layer 202 on the oxide layer 201; a dielectric layer 205 disposed on the substrate 200 and the high-resistance layer 202; a first via 206 located in the dielectric layer 205, the bottom of which exposes the top surface of the conductive layer 203; a second via 207 located in the dielectric layer 205, the bottom of which exposes the top surface of the oxide layer 201; a connection layer 208 located in the first via 206; an adhesion layer 209 on the surface of the dielectric layer 205, the surface of the connection layer 208, and the sidewalls and bottom of the second via 207; and a metal layer 210 disposed on the adhesion layer 209 and filling the second via 207.
In this embodiment, the bottom of the first via 206 exposes the top surface of the conductive layer 203, the bottom of the second via 207 exposes the top surface of the oxide layer 201, the first via 206 has a connection layer 208 therein, the adhesion layer 209 is located on the surface of the dielectric layer 205, the surface of the connection layer 208 and the side wall and bottom of the second via 207, and the metal layer 210 is located on the adhesion layer 209 and fills the second via 207, so that the problem that the growth heights of the connection layers are different is avoided in the second via 207 due to the absence of the connection layer in the second via 207, the problem that the interface between the connection layer 208 and the metal layer 210 is uneven or defective in the second via 207 is thoroughly eliminated, the quality of the metal layer 210 formed in the second via 207 is improved, thereby improving the performance of the finally formed semiconductor device and expanding the application range of the semiconductor device.
The thickness of the oxide layer 201 isTo the point of
In this embodiment, the oxide layer 201 has a thickness ofTo the point ofWhen the thickness of the oxide layer 201 is smaller thanWhen the thickness of the oxide layer 201 is formed too thin, the risk of the oxide layer 201 being etched through increases; when the thickness of the oxide layer 201 is greater thanThe oxide layer 201 is formed to have a thickness too thick, so that the amount of metal layer that can be formed in the second via hole is small, and the risk of exposing the high-resistance layer 202 during planarization is increased, which affects the performance of the semiconductor device.
And the etching selection ratio of the oxide layer to the high-resistance layer is smaller than 1.
In this embodiment, since the etching selectivity of the oxide layer 201 to the high-resistance layer 202 is less than 1, it is ensured that only the high-resistance layer 202 is etched in the subsequent process of etching the high-resistance layer 202, and the surface of the oxide layer 201 is not damaged.
In this embodiment, the material of the oxide layer is silicon oxide or silicon nitride.
In this embodiment, the forming process of the oxide layer 201 is an atomic layer deposition process or a chemical vapor deposition process.
When the atomic layer deposition process is used in the formation process of the oxide layer 201, specific process parameters include: SAM24 and oxygen are adopted as raw materials, wherein the flow rate of the oxygen is 0 to 10slm; the reaction temperature is 150-450 ℃.
When the chemical vapor deposition process is adopted in the process of forming the oxide layer 201, specific process parameters include: TEOS and oxygen are used as raw materials, wherein the flow rate of the oxygen is 500 sccm-1500 sccm, and the reaction temperature is 150-450 ℃.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (11)
1. A semiconductor device, comprising:
a substrate;
A conductive layer within the substrate;
an oxide layer on a portion of the surface of the substrate;
The high-resistance layer is positioned on the oxide layer;
The dielectric layer is positioned on the substrate and the high-resistance layer;
The first through hole is positioned in the dielectric layer, and the bottom of the first through hole exposes the top surface of the conductive layer;
The second through hole is positioned in the dielectric layer, and the bottom of the second through hole exposes the top surface of the oxide layer;
The connecting layer is positioned in the first through hole;
The adhesion layer is positioned on the surface of the dielectric layer, the surface of the connecting layer and the side wall and the bottom of the second through hole;
And the metal layer is positioned on the adhesion layer and is filled with the second through hole.
2. The semiconductor device according to claim 1, wherein the oxide layer has a thickness ofTo the point of
3. The semiconductor device according to claim 1, wherein an etching selectivity of the oxide layer to the high-resistance layer is less than 1.
4. The semiconductor device according to claim 1, wherein a material of the oxide layer is silicon oxide or silicon nitride.
5. A method of forming a semiconductor device, comprising:
Providing a substrate, wherein an oxide layer and a high-resistance layer positioned on the oxide layer are formed on part of the surface of the substrate;
Forming a dielectric layer on the surface of the high-resistance layer and the surface of the substrate uncovered by the oxide layer and the high-resistance layer;
and etching the dielectric layer to form a first through hole and a second through hole in the dielectric layer, wherein the bottom of the first through hole exposes the top surface of the conductive layer in the substrate, and the bottom of the second through hole exposes the top surface of the oxide layer.
6. The method of claim 5, wherein the oxide layer forming process is an atomic layer deposition process or a chemical vapor deposition process.
7. The method of forming a semiconductor device according to claim 5, wherein the oxide layer has a thickness ofTo the point of
8. The method of claim 5, wherein an etch selectivity of the oxide layer to the high resistance layer is less than 1.
9. The method of forming of claim 5, wherein after forming the first via and the second via, a connection layer is formed within the first via.
10. The method of forming of claim 9, wherein after forming the connection layer, an adhesion layer is formed on the dielectric layer, on the connection layer, and on sidewalls and bottoms of the second via holes; and forming a metal layer on the adhesion layer, wherein the metal layer fills the second through hole.
11. The method of claim 5, wherein the oxide layer is made of silicon oxide or silicon nitride.
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