CN104600059B - A kind of TSV pore structures and its processing method with IPD - Google Patents
A kind of TSV pore structures and its processing method with IPD Download PDFInfo
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- CN104600059B CN104600059B CN201510055003.XA CN201510055003A CN104600059B CN 104600059 B CN104600059 B CN 104600059B CN 201510055003 A CN201510055003 A CN 201510055003A CN 104600059 B CN104600059 B CN 104600059B
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Abstract
The invention provides a kind of TSV pore structures with IPD, using traditional TSV technological processes, by structure design, so that the simple structure in TSV holes, the TSV adapter plate structures of resistance, electric capacity, inductance are realized while ensureing that TSV holes are simply molded, pinboard performance is improved, it includes silicon wafer circle, it is characterised in that：Multiple TSV through hole are provided with the silicon wafer circle, there is insulating barrier together with silicon wafer periphery deposition in the TSV through hole, in the TSV through hole lateral insulator is provided with least one TSV through hole, TSV through hole is formed to separate up and down, electroplated metal layer in the TSV through hole, the metal level upper and lower side in the TSV through hole interlocks interconnection, the silicon wafer periphery is molded ring-type electroplated metal layer, the ring-type electroplated metal layer is interconnected with electroplated metal layer in the TSV through hole, invention also provides a kind of processing method of the TSV pore structures with IPD.
Description
Technical field
The present invention relates to micro-electronic manufacturing or the technical field of the method for the treatment of semiconductor or solid state device, and in particular to one
Plant TSV pore structures and its processing method with IPD.
Background technology
With the continuous progress of microelectric technique, the characteristic size of integrated circuit is constantly reduced, and interconnection density is improved constantly.
Requirement of the user to high-performance low power consumption simultaneously is improved constantly.In this case, come by further reducing the line width of interconnection line
Put forward high performance mode to be limited by physical characteristics of materials and apparatus and process, the resistance capacitance of two-dimentional interconnection line（RC）Postpone by
Gradually turn into the bottleneck that limitation semiconductor core piece performance is improved.Silicon perforation（Through Silicon Via, abbreviation TSV）Technique is led to
Cross with reference to forming metal upright post in wafer, and be equipped with metal salient point, it is possible to achieve between wafer (chip) or chip and substrate
Between directly three-dimensional interconnection, can so make up conventional semiconductor chip two dimension wiring limitation.This interconnection mode and biography
The Stack Technology such as bonding techniques of system are small compared to appearance and size after having the advantages that three-dimensional stacking density is big, encapsulating, so that
Greatly improve the speed of chip and reduce power consumption.What is be widely used at present is the 2.5D encapsulation based on TSV pinboards, different
The chip of type, the substrate of lower section is linked to by TSV pinboards, can so greatly improve interconnection density, and improving machinery can
By property and heat-sinking capability.TSV pinboards are passive transition plate, mainly provide interconnecting channel, but in some high frequencies, the core of high speed
During piece is integrated, interconnection delay and parasitics are serious, therefore by adding decoupling capacitor, inductance element, improve interconnection performance,
Existing decoupling capacitor, inductance element are generally added by way of interconnection, this addition manner integrated circuit structure and Qi Jia
Work technique is all complex.
The content of the invention
Regarding to the issue above, the invention provides a kind of TSV pore structures with IPD, using traditional TSV technique streams
Journey, by structure design so that the simple structure in TSV holes, realized while ensureing that TSV holes are simply molded resistance, electric capacity,
The TSV adapter plate structures of inductance, improve pinboard performance, invention also provides a kind of adding for TSV pore structures with IPD
Work method.
Its technical scheme of the invention is such：A kind of TSV pore structures with IPD, it includes silicon wafer circle, and it is special
Levy and be：Be provided with the silicon wafer circle in multiple TSV through hole, the TSV through hole has absolutely together with silicon wafer periphery deposition
Edge layer, is provided with lateral insulator at least one TSV through hole in the TSV through hole, form TSV through hole and separate up and down, described
Electroplated metal layer in TSV through hole, the metal level upper and lower side in the TSV through hole interlocks interconnection, the silicon wafer periphery
Shaping ring-type electroplated metal layer, the ring-type electroplated metal layer is interconnected with electroplated metal layer in the TSV through hole.
It is further characterized by：Electroplated metal layer is ring-type inductance shape metal level in the TSV through hole of connection.
A kind of processing method of the TSV pore structures with IPD, it is comprised the following steps：
（1）, multiple TSV deep holes are etched on silicon wafer circle；
（2）, depositing first insulator layer in a TSV deep holes and on silicon wafer circle；
（3）, on the first insulating barrier deposited seed layer, on the seed layer electroplated metal layer, and TSV depths of forming part the
The electroplated metal layer interconnection in hole；
（4）, at the silicon wafer circle back side, correspondence the first TSV deep holes etch the second deep hole,
（5）, in the 2nd TSV deep holes and on silicon wafer circle deposit the second insulating barrier；
（6）, the TSV deep holes of etched portions the 2nd horizontal first insulating barrier and second insulating barrier, form the
One TSV deep holes and the 2nd TSV deep holes are connected；
（7）, deposited seed layer, the electroplated metal layer in Seed Layer and the 2nd TSV deep holes over the second dielectric, and formed
The electroplated metal layer interconnection of the TSV deep holes of part the 2nd.
Itself further improvement is that：
Ring-type inductance shape metal level is molded in the TSV through hole that a TSV deep holes and the 2nd TSV deep holes are connected；Described
Silicon wafer periphery is molded ring-type electroplated metal layer, forms resistor-type metal level.
In said structure of the invention, due to being molded TSV holes, the plating of profiled insulation in TSV holes on silicon wafer circle
Metal level, forms capacitance structure, and electroplated metal layer is molded in TSV holes, forms induction structure, and ring-type is molded on silicon wafer circle
Electroplated metal layer, form electric resistance structure, the TSV of resistance, electric capacity, inductance is realized while ensureing that TSV holes are simply molded
Adapter plate structure, it is to avoid the assembling of follow-up passive element, reduce space and the cost of element occupancy, improves encapsulation overall
Interconnection performance.
Brief description of the drawings
Fig. 1 is TSV pore structures generalized section of the present invention；
Fig. 2 is the first TSV deep hole schematic diagrames of etching；
Fig. 3 is that the first insulating barrier schematic diagram is molded in a TSV deep holes；
Fig. 4 is deposited seed layer and electroplated metal layer schematic diagram on the first insulating barrier；
Fig. 5 is to etch the 2nd TSV deep hole schematic diagrames；
Fig. 6 is that the second insulating barrier schematic diagram is molded in the 2nd TSV deep holes；
Fig. 7 is partial etching the second insulating barrier schematic diagram；
Fig. 8 is deposited seed layer and electroplated metal layer schematic diagram over the second dielectric.
Specific embodiment
The invention will be further described with reference to the accompanying drawings：
See Fig. 1,
A kind of TSV structure with IPD, it includes silicon wafer circle 1, multiple TSV through hole 4 is provided with silicon wafer circle 1,
There is insulating barrier 2 together with the surface of silicon wafer circle 1 deposition in TSV through hole 4, be provided with least one TSV through hole 4a in TSV through hole 4
Lateral insulator 2a, forms TSV through hole 4a and separates up and down, electroplated metal layer 3 in TSV through hole 4, plating in the TSV through hole 4 of connection
Metal level 3 is ring-type inductance shape metal level, and the upper and lower side of metal level 3 in TSV through hole 4 interlocks interconnection, the surface forming of silicon wafer circle 1
Ring-type electroplated metal layer 5, ring-type electroplated metal layer 5 is interconnected with electroplated metal layer in TSV through hole 3, due on silicon wafer circle into
Type TSV holes, the electroplated metal layer of profiled insulation in TSV holes forms capacitance structure, and electroplated metal layer, shape are molded in TSV holes
Into induction structure, the electroplated metal layer of ring-type is molded on silicon wafer circle, forms electric resistance structure, be simply molded in guarantee TSV holes
While realize the TSV adapter plate structures of resistance, electric capacity, inductance, it is to avoid the assembling of follow-up passive element, reduce element
The space of occupancy and cost, improve the overall interconnection performance of encapsulation.
A kind of processing method of the TSV pore structures with IPD, it is comprised the following steps：
See Fig. 2,（1）, multiple TSV deep holes 4 are etched on silicon wafer circle 1 using dry method or wet method；
See Fig. 3,（2）, in TSV deep holes 4 and on silicon wafer circle 1 using thermal oxide, CVD deposition, spin coating, spraying etc.
Mode forms the first insulating barrier 2；
See Fig. 4,（3）, on the first insulating barrier 2 PVD deposition adhesion layer and Seed Layer（It is not drawn into figure）, on the seed layer
Electroplated metal layer 3, by photoetching and metal dry or wet etch technique, metal is electroplated in the surface forming ring-type of silicon wafer circle 1
Layer 5, forms resistor-type metal level, and the electroplated metal layer of the TSV deep holes 4 of forming part the is interconnected；
See Fig. 5,（4）, in the back side of silicon wafer circle 1 correspondence the first TSV deep holes 4 position, by double-sided overlay and wet method or
Dry etching forms the 2nd TSV deep hole 4-1,
See Fig. 6,（5）, CVD deposition in the 2nd TSV deep holes 4-1 and on silicon wafer circle 1, that spin coating or spraying form second is exhausted
Edge layer 2-1；
See Fig. 7,（6）, using photoetching and dry or wet technique, horizontal first of the TSV deep holes 4 of etched portions the 2nd
The insulating barrier 2-1 of insulating barrier 2 and second, forms a TSV deep holes 4 and is connected with the 2nd TSV deep holes 4-1；
See Fig. 8,（7）, over the second dielectric deposited seed layer, in Seed Layer and the 2nd TSV deep holes 4-1 electroplate metal
Layer 3, and the TSV deep holes of forming part the 2nd electroplated metal layer interconnection, a TSV deep holes 4 and the 2nd TSV deep holes 4-1 are by the
Electroplated metal layer 3 forms capacitance structure in the through hole that one insulating barrier 2 and the second insulating barrier 2-1 disconnect, in the He of a TSV deep holes 4
Shaping ring-type inductance shape metal level 3 in the through hole of the 2nd TSV deep holes 4-1 connections.
In the said structure and process of TSV pore structures and its processing method of the present invention with IPD,
（1）, three-dimensional circular induction structure formed by TSV holes and surface wiring；
（2）, by forming insulating barrier in the middle of TSV holes, two ends form metal, form capacitance structure；
（3）, surface formed electric resistance structure；
（4）, simultaneous with the TSV pore structures of normal function.
TSV holes pinboard is by the elements such as integrated resistor, electric capacity, inductance, the electrical property that further lifting is interconnected, so that real
Existing intelligent pinboard.
Claims (8)
1. a kind of TSV pore structures with IPD, it includes silicon wafer circle, it is characterised in that：It is provided with the silicon wafer circle
There is insulating barrier together with silicon wafer periphery deposition in multiple TSV through hole, the TSV through hole, at least one in the TSV through hole
Lateral insulator is provided with TSV through hole, TSV through hole is formed and is separated up and down, electroplated metal layer in the TSV through hole, the TSV
The metal level upper and lower side on through hole interlocks interconnection, and the silicon wafer periphery is molded ring-type electroplated metal layer, the ring-type
Electroplated metal layer is interconnected with electroplated metal layer in the TSV through hole.
2. a kind of TSV pore structures with IPD according to claim 1：Electroplated metal layer in the TSV through hole of connection
It is ring-type inductance shape metal level.
3. a kind of processing method of the TSV pore structures with IPD, it is characterised in that：It is comprised the following steps：
（1）, multiple TSV deep holes are etched on silicon wafer circle；
（2）, depositing first insulator layer in a TSV deep holes and on silicon wafer circle；
（3）, on the first insulating barrier deposited seed layer, on the seed layer electroplated metal layer, and forming part the TSV deep holes
Electroplated metal layer is interconnected；
（4）, at the silicon wafer circle back side, correspondence the first TSV deep holes etch the 2nd TSV deep holes,
（5）, in the 2nd TSV deep holes and on silicon wafer circle deposit the second insulating barrier；
（6）, the TSV deep holes of etched portions the 2nd horizontal first insulating barrier and second insulating barrier, formed a TSV
Deep hole and the 2nd TSV deep holes are connected；
（7）, deposited seed layer, the electroplated metal layer in Seed Layer and the 2nd TSV deep holes over the second dielectric, and forming part
The electroplated metal layer interconnection of the 2nd TSV deep holes.
4. the processing method of a kind of TSV pore structures with IPD according to claim 3, it is characterised in that：First
Shaping ring-type inductance shape metal level in TSV deep holes and the TSV through hole of the 2nd TSV deep holes connection.
5. the processing method of a kind of TSV pore structures with IPD according to claim 3 or 4, it is characterised in that：
The silicon wafer periphery is molded ring-type electroplated metal layer, forms resistor-type metal level.
6. the processing method of a kind of TSV pore structures with IPD according to claim 3, it is characterised in that：Using hot oxygen
Change, CVD deposition, spin coating, spraying method form the first insulating barrier.
7. the processing method of a kind of TSV pore structures with IPD according to claim 3, it is characterised in that：By photoetching
With metal dry or wet etch technique, ring-type electroplated metal layer is molded in silicon wafer periphery.
8. the processing method of a kind of TSV pore structures with IPD according to claim 3, it is characterised in that：By two-sided
Alignment and wet method or dry etching form the 2nd TSV deep holes.
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Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201826893A (en) * | 2017-01-11 | 2018-07-16 | 思鷺科技股份有限公司 | Package structure and manufacturing method of package structure |
| CN105529299B (en) * | 2015-09-14 | 2019-03-22 | 上海交通大学 | A method of plating filling silicon substrate TSV pinboard |
| CN105390480B (en) * | 2015-10-23 | 2017-11-28 | 西安理工大学 | Three-dimensional high level integrated capacitor based on silicon hole array and preparation method thereof |
| CN105470237B (en) * | 2015-12-09 | 2018-04-17 | 西安交通大学 | Based on the three-dimensional integrated interconnection structure of three-dimensional capacitive coupling for wearing silicon capacitance |
| CN105679701B (en) * | 2016-01-18 | 2019-01-11 | 上海交通大学 | A kind of method of high-efficiency electroplating filling silicon substrate TSV |
| CN105679734B (en) * | 2016-03-07 | 2018-05-25 | 中国科学院上海微系统与信息技术研究所 | Integrated passive components pinboard and preparation method thereof |
| CN106057757A (en) * | 2016-07-08 | 2016-10-26 | 桂林电子科技大学 | Silicon through hole structure and manufacturing method thereeof |
| CN106298732A (en) * | 2016-09-29 | 2017-01-04 | 中国电子科技集团公司第四十三研究所 | A kind of adapter plate structure for system in package |
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| CN113161289B (en) * | 2021-04-22 | 2023-05-12 | 浙江集迈科微电子有限公司 | Electroplating process of TSV metal column with high depth-to-width ratio |
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Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8421158B2 (en) * | 1998-12-21 | 2013-04-16 | Megica Corporation | Chip structure with a passive device and method for forming the same |
| TW511405B (en) * | 2000-12-27 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Device built-in module and manufacturing method thereof |
| KR100400234B1 (en) * | 2001-11-15 | 2003-10-01 | 삼성전자주식회사 | Passive devices and modules for transceiver |
| TWI301739B (en) * | 2004-12-03 | 2008-10-01 | Via Tech Inc | Structure and method for embedded passive component assembly |
| US7772081B2 (en) * | 2008-09-17 | 2010-08-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming high-frequency circuit structure and method thereof |
| US8344478B2 (en) * | 2009-10-23 | 2013-01-01 | Maxim Integrated Products, Inc. | Inductors having inductor axis parallel to substrate surface |
| US8891245B2 (en) * | 2011-09-30 | 2014-11-18 | Ibiden Co., Ltd. | Printed wiring board |
| CN103378057B (en) * | 2012-04-20 | 2016-06-29 | 南亚科技股份有限公司 | Semiconductor chip and method of forming same |
| TWI488286B (en) * | 2012-12-25 | 2015-06-11 | Univ Nat Chiao Tung | Semiconductor device integrating passive components |
| US20140252547A1 (en) * | 2013-03-08 | 2014-09-11 | Advanced Semiconductor Engineering, Inc. | Semiconductor device having integrated passive device and process for manufacturing the same |
| CN104241267B (en) * | 2013-06-18 | 2017-08-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of integrated circuit and its manufacture method |
| CN103700644B (en) * | 2013-12-23 | 2016-06-01 | 华进半导体封装先导技术研发中心有限公司 | Based on pinboard deep-channel capacitor and the manufacture method thereof of TSV technique |
| CN103956326B (en) * | 2014-04-29 | 2017-01-11 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing method for integrated passive interposer and corresponding integrated passive interposer |
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