CN103346122A - High depth-to-width ratio TSV seed layer manufacturing method - Google Patents
High depth-to-width ratio TSV seed layer manufacturing method Download PDFInfo
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- CN103346122A CN103346122A CN2013103058669A CN201310305866A CN103346122A CN 103346122 A CN103346122 A CN 103346122A CN 2013103058669 A CN2013103058669 A CN 2013103058669A CN 201310305866 A CN201310305866 A CN 201310305866A CN 103346122 A CN103346122 A CN 103346122A
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- tsv
- seed layer
- copper
- copper seed
- width ratio
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000005516 engineering process Methods 0.000 claims abstract description 35
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052802 copper Inorganic materials 0.000 claims abstract description 31
- 239000010949 copper Substances 0.000 claims abstract description 31
- 238000010992 reflux Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 6
- 239000004568 cement Substances 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 15
- 239000002184 metal Substances 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 7
- 238000009713 electroplating Methods 0.000 abstract description 5
- 238000004377 microelectronic Methods 0.000 abstract description 3
- 210000002381 plasma Anatomy 0.000 abstract 3
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000004062 sedimentation Methods 0.000 abstract 1
- 238000005240 physical vapour deposition Methods 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000009832 plasma treatment Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 241000237509 Patinopecten sp. Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 description 1
- SKKMWRVAJNPLFY-UHFFFAOYSA-N azanylidynevanadium Chemical compound [V]#N SKKMWRVAJNPLFY-UHFFFAOYSA-N 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 235000020637 scallop Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention relates to a high depth-to-width ratio TSV seed later manufacturing method in a microelectronic processing technology. The high depth-to-width ratio TSV seed later manufacturing method aims to solve the problems that a seed layer is discontinuous and even prone to breakage, and the effect of a following-up electroplating technology is affected due to the fact that the metal seed layer generated through a common PVD method is low in step coverage rate in a silicon through hole. According to the high depth-to-width ratio TSV seed layer manufacturing method, after seed layer sedimentation is completed through PVD, heating is conducted under vacuum or ultra-low pressure environment so as to increase the liquidity of a copper seed layer, and meanwhile, plasma bombardment is conducted in an auxiliary mode to promote the copper seed layer to flow towards the lower middle portion of a TSV. Due to the bombardment effect of plasmas, copper at the bottom of the TSV can splash backward to the weakest lateral wall on the middle lower portion of the TSV after being bombarded, and therefore the continuity, inside a TSV hole, of the copper seed layer is guaranteed. The continuity, inside the TSV, of the copper seed layer which undergoes backflow and plasma processing is improved, and therefore the operation of the following-up electroplating technology is facilitated, and the filling effect of the TSV is guaranteed.
Description
Technical field
The present invention relates to a kind of method of making or handling semiconductor or solid state device of microelectronics technology, be specifically related to the manufacture method of a kind of high-aspect-ratio TSV Seed Layer in the microelectronic processing technology.
Background technology
Along with the semiconductor chip characteristic size is followed Moore's Law and is constantly dwindled, the performance of semiconductor device improves constantly, but meanwhile, the interconnection performance is but on the contrary because dwindling of live width and continuous variation makes interconnection line become the bottleneck that restriction semiconductor core piece performance improves gradually.(Through Silicon Via TSV) effectively uses the third dimension of semiconductor chip, can remedy the only limitation of two dimension wiring of conventional semiconductors chip, is the important way that solves the semiconductor chip interconnect bottleneck for silicon perforation or silicon through hole.Its manufacturing process is by forming metal upright post in wafer, and is equipped with metal salient point, can realize between the wafer (chip) or direct three-dimensional interconnection between chip and substrate, can remedy the limitation of conventional semiconductors chip two dimension wiring like this.This interconnection mode is compared with the traditional technology of piling up such as routing interconnected (Wire bonding) technology to have three-dimensional and piles up advantages such as density is big, encapsulation back overall dimension is little, thereby improves the speed of chip greatly and reduce power consumption.Therefore, the TSV technology be widely regarded as after the weldering of bonding, carrier band and flip-chip the 4th generation encapsulation technology, undoubtedly will become the mainstream technology in high-density packages field gradually.
The TSV development technology is included on the wafer makes the vertical conducting hole by modes such as etching, laser drill, makes insulating barrier, barrier layer and seed layer deposition, filling metal, chemico-mechanical polishing, attenuate and wafer bonding step subsequently then in via.When filling metal by electroplating technology in TSV, generation technology that usually must advanced row metal Seed Layer is to prevent non-continuous event such as hole.What the use of the generation technology of this Seed Layer was more in the practice is to utilize physical vapor deposition (PVD) technology.But along with the depth-to-width ratio (Aspect Ratio) of silicon through hole is increasing, utilize the difficulty of physical vapor deposition (PVD) technology making Seed Layer increasing.Such as, when depth-to-width ratio〉during 5:1, continuity will variation in the silicon through hole for the Seed Layer that the PVD mode generates, even interrupting near the side-walls of TSV bottom, influences the electroplating technology effect.
At the problems referred to above, known technology has ionization PVD or ALD at present, and they have adopted the mode of nano-spray, therefore has the high shortcoming of cost.Similar techniques also has electric crosslinking technology, also be to adopt nanometer technology to form the surface activity conformal film at the inwall of TSV, but this technology also is not very ripe at present.It is a kind of under dielectric layer fluted (recessed region) situation that publication number is that the United States Patent (USP) of US20030139033A1 has disclosed, the technology that how utilizing during deposited copper on dielectric layer refluxes fills avoids occurring in the above-mentioned grooved area technology of hole, to improve the reliability of electrical interconnection.But the result of reflux technique is that copper is filled and led up whole grooved area in this technology, can not satisfy the needs of deposition Seed Layer.
Summary of the invention
At above-mentioned Seed Layer discontinuous problem in the silicon through hole, the invention provides a kind of manufacture method that adopts the Seed Layer that copper refluxes, plasma enhancing technology combines with PVD technology.
A kind of high-aspect-ratio TSV seed layer manufacturing method thereof particularly may further comprise the steps:
(1) carrying out TSV in wafer substrate makes and the insulating barrier deposit;
(2) utilize PVD technology cement copper Seed Layer in substrate surface and TSV hole;
(3) reflux course, namely under vacuum or hypobaric, be heated to 200-800 ℃ and make the mobile increase of copper seed layer, wafer frontside is placed up, copper seed layer is flowed downward by the TSV oral area, the copper seed layer of eliminating the side-walls of TSV bottom interrupts, and makes copper seed layer evenly distribute along TSV sidewall and bottom.
As the further improvement to said method, in above-mentioned reflux course, be aided with from top to bottom direction bombardment TSV hole of plasma.Plasma bombardment will help the copper backwash of substrate surface and TSV oral area and bottom, make Seed Layer more continuous at TSV sidewall and bottom.
As the preferred version of such scheme, the aperture of above-mentioned TSV is more than 5 microns, and depth-to-width ratio is not less than 6 scopes.
The atmospheric pressure value of above-mentioned hypobaric is 10
2Pa, reflux temperature is in the 200-800 scope.
Above-mentioned Seed Layer can also be selected the metal outside the copper under the hypobaric of certain limit, as tungsten, aluminium etc.
Utilizing PVD technology first deposit one deck barrier layer before the cement copper Seed Layer in substrate surface and TSV hole.
Compare with prior aries such as ionization PVD or ALD, the technical advantage that the technical program has is, owing to being refluxed, metal seed layer all belongs to ripe technology with plasma treatment under hypobaric, and the backflow of Seed Layer can also reduce on the TSV inwall because the influence that the scalloped surface (scallop) that etching forms distributes to Seed Layer under the conventional PVD technology, and technical scheme has easy realization, clear superiority that cost is low.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is for finishing the wafer substrate of TSV etching and insulating barrier deposit.
Fig. 2 is for carrying out the schematic diagram after the plated metal Seed Layer to wafer shown in Figure 1.
Fig. 3 is for refluxing and the schematic diagram of plasma treatment to institute's plated metal Seed Layer.
Fig. 4 is the schematic diagram of the copper seed layer of process backflow and plasma treatment.
Embodiment
Figure 1 shows that the wafer substrate of finishing TSV etching and insulating barrier depositing technics, wherein 1 is substrate, and 2 is the barrier layer, and this rete can be materials such as silicon dioxide, silicon nitride, silicon oxynitride, organic polymer.3 is the TSV hole.Can there be zero layer or multilayer to cover deep hole sidewall film layer structure 2 as required in the deep hole.
Utilize PVD technology deposited metal 4 in substrate 1 surface and TSV hole 3, as shown in Figure 2.The PVD metal level comprises barrier layer adhesion layer metal and Seed Layer, and the material of barrier layer adhesion layer can be titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, vanadium, vanadium nitride, niobium, niobium nitride etc., and seed layer materials is copper.
After utilizing PVD to finish cement copper, wafer placed under vacuum or the hypobaric add hot reflux, make under 200-800 ℃ of condition that copper seed layer is mobile to be increased, be aided with plasma bombardment 5 simultaneously, promote copper seed layer 4 to flow to the TSV middle and lower part, as shown in Figure 3.Owing to the bombardment effect of plasma, the copper of TSV bottom can be arrived the weakest TSV middle and lower part sidewall of Seed Layer by backwash after bombarding, thereby guarantees the continuity of copper seed layer 4 in the TSV hole simultaneously.
The continuity of copper seed layer 4 in TSV inside through backflow and plasma treatment improves, and as shown in Figure 4, therefore is conducive to the carrying out of follow-up electroplating technology, guarantees the filling effect of TSV.
Undoubtedly, seed layer manufacturing method thereof of the present invention is not limited to above-mentioned listed embodiment, and the Seed Layer metal can also be the metal beyond the copper as described, and backing material can be not limited to silicon, can also be materials such as silicon dioxide.The those of ordinary skill of this area all drops among protection scope of the present invention in the be evenly distributed method of purpose of the bottom of TSV and sidewall with the realization Seed Layer as long as the method be combined with plasma by refluxing in the TSV related process is handled Seed Layer.
Claims (6)
1. high-aspect-ratio TSV seed layer manufacturing method thereof is characterized in that may further comprise the steps:
Carrying out TSV in wafer substrate makes and the insulating barrier deposit;
Utilize PVD technology cement copper Seed Layer in substrate surface and TSV hole;
(3) reflux course, namely under vacuum or hypobaric, be heated to 200-800 ℃ and make the mobile increase of copper seed layer, wafer frontside is placed up, copper seed layer is flowed downward by the TSV oral area, the copper seed layer of eliminating the side-walls of TSV bottom interrupts, and makes copper seed layer evenly distribute along TSV sidewall and bottom.
2. TSV seed layer manufacturing method thereof according to claim 1 is characterized in that being aided with in the described reflux course from top to bottom direction bombardment TSV hole of plasma.
3. TSV seed layer manufacturing method thereof according to claim 1, the material that it is characterized in that described Seed Layer can also be tungsten, aluminium etc.
4. TSV seed layer manufacturing method thereof according to claim 1 and 2 is characterized in that the aperture of described TSV more than 5 microns, and depth-to-width ratio is not less than 6 scope.
5. TSV seed layer manufacturing method thereof according to claim 1 and 2 is characterized in that the atmospheric pressure value of described hypobaric is less than 10
2Pa, reflux temperature is 200-800 ℃ of scope.
6. TSV seed layer manufacturing method thereof according to claim 1 and 2 is characterized in that utilizing PVD technology first deposit one deck barrier layer before the cement copper Seed Layer in substrate surface and TSV hole.
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| CN2013103058669A CN103346122A (en) | 2013-07-22 | 2013-07-22 | High depth-to-width ratio TSV seed layer manufacturing method |
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| CN2013103058669A CN103346122A (en) | 2013-07-22 | 2013-07-22 | High depth-to-width ratio TSV seed layer manufacturing method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105112972A (en) * | 2015-08-27 | 2015-12-02 | 成都嘉石科技有限公司 | Method for manufacturing electroplating seed layer |
| CN109887879A (en) * | 2017-12-06 | 2019-06-14 | 北京北方华创微电子装备有限公司 | A kind of method and semiconductor processing equipment covering film in hole |
| CN114959606A (en) * | 2022-05-13 | 2022-08-30 | 赛莱克斯微系统科技（北京）有限公司 | Preparation method of silicon through hole seed layer and preparation method of chip |
| CN115863259A (en) * | 2023-02-07 | 2023-03-28 | 合肥晶合集成电路股份有限公司 | Metal interconnection structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070032004A1 (en) * | 2005-08-08 | 2007-02-08 | Applied Materials, Inc. | Copper barrier reflow process employing high speed optical annealing |
| CN101643891A (en) * | 2008-08-05 | 2010-02-10 | 吉和林 | Device and process method for filling aluminum into nano through holes by using PVD method |
| US20100068881A1 (en) * | 2008-09-18 | 2010-03-18 | Kang Joo-Ho | Method of forming metallization in a semiconductor device using selective plasma treatment |
| CN102034744A (en) * | 2009-10-05 | 2011-04-27 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing semiconductor device |
-
2013
- 2013-07-22 CN CN2013103058669A patent/CN103346122A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070032004A1 (en) * | 2005-08-08 | 2007-02-08 | Applied Materials, Inc. | Copper barrier reflow process employing high speed optical annealing |
| CN101643891A (en) * | 2008-08-05 | 2010-02-10 | 吉和林 | Device and process method for filling aluminum into nano through holes by using PVD method |
| US20100068881A1 (en) * | 2008-09-18 | 2010-03-18 | Kang Joo-Ho | Method of forming metallization in a semiconductor device using selective plasma treatment |
| CN102034744A (en) * | 2009-10-05 | 2011-04-27 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105112972A (en) * | 2015-08-27 | 2015-12-02 | 成都嘉石科技有限公司 | Method for manufacturing electroplating seed layer |
| CN109887879A (en) * | 2017-12-06 | 2019-06-14 | 北京北方华创微电子装备有限公司 | A kind of method and semiconductor processing equipment covering film in hole |
| CN109887879B (en) * | 2017-12-06 | 2021-12-17 | 北京北方华创微电子装备有限公司 | Method for covering film in hole and semiconductor processing equipment |
| CN114959606A (en) * | 2022-05-13 | 2022-08-30 | 赛莱克斯微系统科技（北京）有限公司 | Preparation method of silicon through hole seed layer and preparation method of chip |
| CN115863259A (en) * | 2023-02-07 | 2023-03-28 | 合肥晶合集成电路股份有限公司 | Metal interconnection structure and manufacturing method thereof |
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Application publication date: 20131009 |