CN102104009A - Manufacturing method of three-dimensional silicon-based capacitor - Google Patents
Manufacturing method of three-dimensional silicon-based capacitor Download PDFInfo
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- CN102104009A CN102104009A CN200910242766.XA CN200910242766A CN102104009A CN 102104009 A CN102104009 A CN 102104009A CN 200910242766 A CN200910242766 A CN 200910242766A CN 102104009 A CN102104009 A CN 102104009A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 65
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 65
- 239000010703 silicon Substances 0.000 title claims abstract description 65
- 239000003990 capacitor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000010949 copper Substances 0.000 claims abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052802 copper Inorganic materials 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 230000008569 process Effects 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 7
- 239000004568 cement Substances 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 238000003487 electrochemical reaction Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000000992 sputter etching Methods 0.000 claims description 4
- 238000000608 laser ablation Methods 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 239000000654 additive Substances 0.000 claims description 2
- 230000000996 additive effect Effects 0.000 claims description 2
- 238000001514 detection method Methods 0.000 claims description 2
- 239000000615 nonconductor Substances 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 26
- 238000005516 engineering process Methods 0.000 abstract description 18
- 238000012545 processing Methods 0.000 abstract description 4
- 238000004377 microelectronic Methods 0.000 abstract description 3
- 238000000708 deep reactive-ion etching Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 239000010931 gold Substances 0.000 abstract 1
- 239000002356 single layer Substances 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for manufacturing a high-density three-dimensional silicon-based stacked capacitor by utilizing semiconductor PN junction capacitance and through silicon via technology, which comprises the following steps: a single-layer silicon-based capacitor chip is etched by utilizing mature microelectronic processing technologies such as deep reactive ion etching, deposition, bonding and the like to form a through hole with a large depth-to-width ratio, copper is deposited to manufacture a gold salient point, and the same multi-layer silicon-based capacitors are aligned and bonded to form a multi-layer stacked three-dimensional silicon-based capacitor. The capacitor can replace the traditional chip capacitor to be applied to a high-frequency high-speed circuit, and is characterized by simple structure, large capacitance, adjustable capacitance value and compatibility with the existing microelectronic process.
Description
Technical field
The present invention relates to technical field of microelectronic devices, be particularly related to a kind of method of utilizing semiconductor PN junction capacitance and the three-dimensional silica-based stacked capacitor of silicon through hole (TSV through silicon vias) fabrication techniques, this capacitor is compared with the semiconductor junction capacitor of individual layer has the big characteristics of unit appearance value, in can be used for, occasions such as high frequency decoupling.
Background technology
Along with people to the requirement of electronic product development to directions such as miniaturization, multi-functional, environment-friendly types, people make great efforts to seek to do electronic system more little, integrated level is more and more higher, function is done more and more, and is more and more stronger.Many new technologies, new material and new design have been produced thus, for example the laminated chips encapsulation technology and with the closely-related system in package of the present invention technology such as (System-in-Package SiP, System-on-Package SoP) be exactly the typical case representative of these technology.The former is called for short the 3D encapsulation technology, is meant under the prerequisite that does not change package body sizes, stacks the encapsulation technology of two above chips in same packaging body in vertical direction, and it originates from the stacked package of flash memory (NOR/NAND) and SDRAM.And TSV realizes one of key technology in the 3D encapsulation.This with respect to traditional mutual contact mode, can realize the total silicon encapsulation owing to TSV, and is compatible mutually with semiconductor CMOS technology, but and equal proportion increase density of components, reduce the interconnect delay problem, realize that high speed is interconnected.And the integrated technology of electric capacity is the essential technology that realizes SOP.This integrated capacitance generally is connected between the power supply and ground in the supply network in the electronic system, utilizes the electric capacity frequency more little principle of high impedance more, the high-frequency noise in the electric power network is reduced, thereby the noise in the electric power network is played inhibitory action.The 3D technology can be used for the integrated IPD of passive device (Integration Passive Devices), the nude film of passive device as active chip, process such as is piled up by the etching punching, with device stack, realize the higher performance of device, be applied to field widely.
The silicon chip micro through-hole has its unique distinction: 1) the silicon chip through-hole aperture is much smaller than the printed circuit board through-hole aperture; 2) depth-to-width ratio of silicon chip through hole is much larger than the depth-to-width ratio of printed circuit board through-hole; 3) density of silicon chip through hole is much larger than the density of printed circuit board through-hole.Based on above characteristics, the processing of silicon chip micro through-hole is different from traditional processing method of through holes, so its development of studying M EMS and semiconductor technology plays an important role.
In the practical application, because intrinsic stray inductance and the resistance of capacitor, any capacitor all can not be accomplished the full frequency band decoupling from the low frequency to the high frequency.In general, capacitor appearance value is big more, and is just good more to low frequency decoupling effect, but volume is just big more, and stray inductance and resistance are also big more, just poor more to the decoupling effect of high frequency; Capacitor appearance value is more little, and volume is just more little, and stray inductance and resistance are just more little, therefore can be used for high frequency, but because the appearance value is little, low frequency decoupling weak effect.So generally be that capacitor with a plurality of different appearance values is together in parallel, Da Rong value capacitor is to the low frequency component decoupling, the low-capacitance capacitor is to the high fdrequency component decoupling.This solution is feasible to the electronic system space without limits the time, but just infeasible when there is strict restriction in the electronic system space.
Up to now, based on metal-insulator-metal (MIM) structure, its representative value of the capacitance density of imbedding electric capacity on especially silica-based is 0.7～0.9nF/mm2, and this capacitance density is that the ideal that low value is used is selected, for example radio frequency middle impedance coupling.But, be difficult to satisfy the requirement of 1～100nF capacitance because little this limitation of its capacitance density is difficult to such as the problems such as decoupling under the radio frequency.The appearance of channel-type electric capacity is exactly in order to increase effective capacitance area, a kind of capacitor that utilizes semiconductor PN junction capacitance to constitute as people such as Wan Lixi proposition, it proposes a kind of unique capacitive properties that the space charge region had that utilizes semiconductor P district, N regional boundary face place to form, carve on silica-based simultaneously poor, increase the effective area of electric capacity, to increase capacitance, still still have limitation for the requirement of capacitance in order to the intermediate frequency decoupling.
People such as Taiwan Maode Science Co., Ltd Li Yue river " form channel capacitor in the method and the channel capacitor of substrate " and Huabang Electronics Co., Ltd execute this one-tenth in " semiconductor device and the manufacture method thereof that comprise groove type capacitance " also the processing procedure to mim structure formula channel capacitance detailed description is also arranged.People such as the Leonard of Arkansas university even electric capacity has been prepared into the MIMIMI...M structure.
The present invention is incorporated into the three-dimensional stacked of passive device with the three-dimensional stacked notion of chip, utilize the key technology of 3D encapsulation, the miniature silicon through hole of etching on the PN junction multiple-grooved channel capacitance that with silicon is base material, and multiple-level stack is realized in parallel, realize reducing required operation and strengthening its high frequency performance in the big capacitance density on silica-based thereby reach, this process also meets the novel notion of total silicon encapsulation.For capacitance density under the 2.5GHz that designs and produce greater than 2nF/mm
2Channel capacitance, pile up ten layer capacitance density in theory and can reach 20nF/mm
2, make capacitor of the present invention can be used for the interior decoupling of medium-high frequency on a large scale.
Summary of the invention
(1) technical problem that will solve
The object of the present invention is to provide a kind of manufacture method of three-dimensional silica based capacitor, propose a kind of notion of integrated capacitance.To being that the electric capacity of material carries out multiple-level stack and interconnected with silicon, make the electric capacity of each interlayer become to be connected in parallel by the TSV technology, increase capacitance in the unit two-dimensional areas with this.
(2) technical scheme
For achieving the above object, the invention provides a kind of manufacture method of three-dimensional silica based capacitor, comprise the following steps:
At the silicon wafer to manufacture PN junction, form semiconductor junction electric capacity, utilize this junction capacitance to be stacked into three-dimensional capacitor for elementary cell;
Silicon chip is carried out attenuate;
On silicon chip back side deposit one deck barrier layer of attenuate, this barrier layer is simultaneously also as the stop layer of etching;
With the silicon chip counter-rotating, on silicon chip, form through hole with deep reaction ion etching or laser ablation;
The copy mask layer pattern forms one deck SiO in through-hole surfaces
2As physical protection layer and electrical insulator layer;
By electrochemical reaction cement copper in the through hole, it is complete that through hole is electrically connected;
Remove unnecessary copper with cmp polishing and etching, make to have an even surface;
With the silicon chip counter-rotating, wet etching is removed the barrier layer and is exposed through hole, and does polishing once more again;
The copper surface of being filled at the silicon through hole makes salient point, and the electric capacity chip that multilayer is identical aligning back bonding, realizes the connection between each layer through hole;
The silicon chip peace that bonding is good will be carried out the making that plastic packaging, cutting and trace routine are finished the whole capacitor device then on silicon substrate.
In the such scheme, the described step that silicon chip is carried out attenuate comprises: to certain thickness, its value depends on whether junction capacitance has vertical structure to wafer thinning, and if any vertical structure, thickness will surpass vertical structure; If there is not vertical structure, thickness is as far as possible little.
In the such scheme, described at through-hole surfaces formation one deck SiO
2Be to use PECVD or thermal oxidation process growth SiO in through-hole surfaces
2
In the such scheme, described by electrochemical reaction cement copper in the through hole, be to adopt to electroplate or additive method is filled through hole with copper.
In the such scheme, described copper surface of being filled at the silicon through hole makes salient point, is to carry out polishing on each layer silicon chip two sides, and makes salient point at lead to the hole site.
In the such scheme, the described silicon chip that bonding is good peace will be that the three-dimensional stacked silicon chip that will form is welded on the substrate in the flip chip bonding mode on silicon substrate, carry out plastic packaging, cutting and detection then, and then form complete capacitor.
(3) beneficial effect
The present invention has compared several advantages with common three-dimensional capacitance.At first, the present invention has broken away from the constraint that traditional MIMIM... multilayer " sandwich " structure forms electric capacity, stands in the angle of three-dimension packaging, and device is integrated.The second, directly utilize the knot electricity of PN junction to hold for elementary cell, making whole capacitor is that base material completes with silicon, relatively cheap, technical maturity.The 3rd, theory analysis, the condenser capacitance density that the present invention makes can reach 10nF to every square millimeter of 15nF, can replace surface mount electric capacity under high frequency, particularly obtains important application in the total silicon encapsulation field.
Description of drawings
Fig. 1 a is silicon base chip multiple-level stack result's a basic schematic diagram
Fig. 1 b after to be that the present invention is prepared finish multiple-level stack electric capacity in application section of structure, wherein:
101-is the chip nude film of matrix with silicon, is PN junction nude film electric capacity in the present invention;
102-is the silicon slide glass of base material with silicon dioxide;
103-is in order to the filling glue of protection laminated device;
104-silicon connecting through hole TSV;
The welded ball array that the silica-based version of 105-links to each other with PCB;
The golden Au salient point that each layer of 106-TSV is connected;
Fig. 2 a to Fig. 2 b is the section of structure that two kinds of different electrodes form electric capacity, is the nude film schematic diagram in order to the multiple-grooved channel capacitance of lamination
201-P type low-resistance silicon substrate;
The 202-dielectric layer;
203-photoresist material;
The n+ district that 204-forms by diffusing, doping;
The 205-Al electrode layer.
Fig. 3 a to Fig. 3 d be used for the present invention the vertical view of PN junction channel-type electric capacity nude film.Wherein:
The P type electrode of 301-electric capacity;
The N type electrode of 302-electric capacity;
303-passes through in the formed raceway groove of the method for method etching;
304-P type low-resistance silicon substrate;
TSV through hole among 304-the present invention.
The flow process profile that Fig. 4 a to Fig. 4 g finishes for the multiple-level stack capacitor.Wherein:
401-is the used electric capacity chip of invention unit silicon chip;
402-is for being used for the barrier layer that etching is protected and the support silicon chip is used among the present invention;
Be used as the oxide layer of physical protection and electrical insulation among 403-the present invention;
Metallic copper Cu through hole in order to be electrically connected among 404-the present invention;
Realize the golden Au salient point that each layer TSV is connected among 405-the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Fig. 4 a to Fig. 4 g is the schematic flow sheet of the multiple-level stack three-dimensional structure capacitor of making according to the present invention.
Step 1 is a basic structural unit of the present invention with as shown in Figure 2 silicon substrate electric capacity, 4 o'clock silicon chips of this basic capacitance structure unit of the selected one-tenth array distribution of the present invention.The making of this electric capacity is finished, and integral thickness is approximately 300 to 400 microns.After the electric capacity cleaning, need silicon chip back side substrate thinning is thinned to about 200 microns, be convenient to next step etching, need thermal oxidation or deposit one deck barrier layer 402 overleaf, shown in Fig. 4 a.
Step 2 shown in Fig. 4 b, is utilized deep reaction ion etching (DRIE) and laser ablation, forms the silicon through hole of high-aspect-ratio.With deep reaction ion etching is example, can adopt Bosch technology, and its plasma gas can be selected SF6, the mist of C2H4, and the protection of etching limit, limit forms diameter at last and is approximately 20 microns, and the degree of depth is 200 microns a silicon through hole.Through hole on each electric capacity the position and distribute shown in visible Fig. 3 d.
Step 3 shown in Fig. 4 c, forms a dielectric layer 403 on the surface of through hole, is used for the physical protection and the electrical insulation of required mask of processing procedure and device.This dielectric layer wherein, can for example be silicon oxide layer, its thickness can be approximately 2 microns, and the formation method for example is to carry out thermal oxidation program (thermal oxidation) or form in plasma enhanced chemical vapor deposition modes such as (PECVD) under the temperature of 850-950 Celsius.
Step 4 is shown in Fig. 4 d, by electrochemical reaction cement copper metal 404 in the through hole.Needing or not the local copy pattern of cement copper by mask earlier; protected; then at the heavy copper in whole capacitor surface; utilize the method for chemistry to form one deck Seed Layer on the surface; remove the protection figure then; electro-coppering can be electroplated the thick copper of last layer rapidly, up to filling up whole through hole on Seed Layer.
Step 5 shown in Fig. 4 e, by chemico-mechanical polishing or grinding and etching technics removal barrier layer, after the removal of finishing the barrier layer, also needs the copper metal of smooth upper and lower surface.
Step 6 shown in Fig. 4 f, is made au bump on the lower surface of copper metal throuth hole.
Step 7 shown in Fig. 4 g, behind two onesize electric capacity chips alignings, by metal bonding together, forms the path that the power-on and power-off gas phase is communicated with.
Step 8 can form lamination with polylith electric capacity chip bonding by that analogy.
Step 9 places the annealing furnace annealing with this device, and the corresponding junior unit of section formation, shown in Fig. 4 h.
In addition, change the position of capacitance electrode, then the position of silicon through hole also can change thereupon, and the present invention has designed the electric capacity of two kinds of diverse location deposits, as shown in Figure 2, the former is the center symmetric mode, the latter is the left-right symmetric mode, and Fig. 3 a to 3b has also provided the upward view of center symmetry electrode, and the position that forms the silicon through hole, Fig. 3 c to 3d has provided the upward view of left-right symmetric electrode, and the position that forms the silicon through hole.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the manufacture method of a three-dimensional silica based capacitor is characterized in that, comprises the following steps:
At the silicon wafer to manufacture PN junction, form semiconductor junction electric capacity, utilize this junction capacitance to be stacked into three-dimensional capacitor for elementary cell;
Silicon chip is carried out attenuate;
On silicon chip back side deposit one deck barrier layer of attenuate, this barrier layer is simultaneously also as the stop layer of etching;
With the silicon chip counter-rotating, on silicon chip, form through hole with deep reaction ion etching or laser ablation;
The copy mask layer pattern forms one deck SiO in through-hole surfaces
2As physical protection layer and electrical insulator layer;
By electrochemical reaction cement copper in the through hole, it is complete that through hole is electrically connected;
Remove unnecessary copper with cmp polishing and etching, make to have an even surface;
With the silicon chip counter-rotating, wet etching is removed the barrier layer and is exposed through hole, and does polishing once more again;
The copper surface of being filled at the silicon through hole makes salient point, and the electric capacity chip that multilayer is identical aligning back bonding, realizes the connection between each layer through hole;
The silicon chip peace that bonding is good will be carried out the making that plastic packaging, cutting and trace routine are finished the whole capacitor device then on silicon substrate.
2. according to the manufacture method of the described three-dimensional silica based capacitor of claim 1, it is characterized in that the described step that silicon chip is carried out attenuate comprises:
To certain thickness, its value depends on whether junction capacitance has vertical structure to wafer thinning, and if any vertical structure, thickness will surpass vertical structure; If there is not vertical structure, thickness is as far as possible little.
3. according to the manufacture method of the described three-dimensional silica based capacitor of claim 1, it is characterized in that, described at through-hole surfaces formation one deck SiO
2Be to use PECVD or thermal oxidation process growth SiO in through-hole surfaces
2
4. according to the manufacture method of the described three-dimensional silica based capacitor of claim 1, it is characterized in that, described by electrochemical reaction cement copper in the through hole, be to adopt to electroplate or additive method is filled through hole with copper.
5. according to the manufacture method of the described three-dimensional silica based capacitor of claim 1, it is characterized in that described copper surface of being filled at the silicon through hole makes salient point, is to carry out polishing on each layer silicon chip two sides, and makes salient point at lead to the hole site.
6. according to the manufacture method of the described three-dimensional silica based capacitor of claim 1, it is characterized in that, the described silicon chip that bonding is good peace will be on silicon substrate, be that the three-dimensional stacked silicon chip that will form is welded on the substrate in the flip chip bonding mode, carry out plastic packaging, cutting and detection then, and then form complete capacitor.
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| CN102339803A (en) * | 2010-07-15 | 2012-02-01 | 南亚科技股份有限公司 | Die package structure and related method of manufacturing the die package structure |
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| US9875959B2 (en) | 2016-06-09 | 2018-01-23 | International Business Machines Corporation | Forming a stacked capacitor |
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| WO2020037497A1 (en) * | 2018-08-21 | 2020-02-27 | 深圳市为通博科技有限责任公司 | Capacitor and processing method therefor |
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| WO2021135018A1 (en) * | 2019-12-31 | 2021-07-08 | 诺思(天津)微系统有限责任公司 | Semiconductor structure having stacking unit and manufacturing method therefore, and electronic device |
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- 2009-12-16 CN CN200910242766.XA patent/CN102104009B/en active Active
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339803A (en) * | 2010-07-15 | 2012-02-01 | 南亚科技股份有限公司 | Die package structure and related method of manufacturing the die package structure |
| CN102339803B (en) * | 2010-07-15 | 2013-09-25 | 南亚科技股份有限公司 | Die package structure manufacturing method |
| CN104685098A (en) * | 2012-09-28 | 2015-06-03 | 田中贵金属工业株式会社 | Method for treating substrate carrying catalyst particles for plating treatment |
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| CN106847557A (en) * | 2015-12-05 | 2017-06-13 | 佛山市欣源电子股份有限公司 | The metal grill hot pressing shaping process of capacitor core |
| CN106847557B (en) * | 2015-12-05 | 2023-11-07 | 佛山市欣源电子股份有限公司 | Metal grid hot-press shaping process of capacitor core |
| US9875959B2 (en) | 2016-06-09 | 2018-01-23 | International Business Machines Corporation | Forming a stacked capacitor |
| US10242943B2 (en) | 2016-06-09 | 2019-03-26 | International Business Machines Corporation | Forming a stacked capacitor |
| WO2020037497A1 (en) * | 2018-08-21 | 2020-02-27 | 深圳市为通博科技有限责任公司 | Capacitor and processing method therefor |
| US10910158B2 (en) | 2018-08-21 | 2021-02-02 | Shenzhen Weitongbo Technology Co., Ltd. | Capacitor and method for fabricating the same |
| CN109461737B (en) * | 2018-11-12 | 2020-09-29 | 长江存储科技有限责任公司 | Semiconductor device and manufacturing method thereof |
| CN109461737A (en) * | 2018-11-12 | 2019-03-12 | 长江存储科技有限责任公司 | A kind of semiconductor devices and its manufacturing method |
| WO2021135018A1 (en) * | 2019-12-31 | 2021-07-08 | 诺思(天津)微系统有限责任公司 | Semiconductor structure having stacking unit and manufacturing method therefore, and electronic device |
| CN112018096A (en) * | 2020-07-31 | 2020-12-01 | 复旦大学 | A three-dimensional integrated system of nanocapacitors for energy buffering and preparation method thereof |
| CN112018096B (en) * | 2020-07-31 | 2022-05-24 | 复旦大学 | A three-dimensional integrated system of nanocapacitors for energy buffering and preparation method thereof |
| TWI862432B (en) * | 2024-03-11 | 2024-11-11 | 華邦電子股份有限公司 | 3d capacitance structure and manufacture method of the same |
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