CN112018096A - A three-dimensional integrated system of nanocapacitors for energy buffering and preparation method thereof - Google Patents

Abstract

The invention discloses a nano-capacitor three-dimensional integrated system for energy buffering and a preparation method thereof. The three-dimensional integrated system of nanocapacitors for energy buffering includes multiple vertically stacked through-silicon via-nanocapacitor hybrid structures, which can greatly increase the capacitance density and storage capacity, so that while having higher power density, it can also have higher energy density.

Description

A three-dimensional integrated system of nanocapacitors for energy buffering and preparation method thereof

technical field

The invention belongs to the field of integrated circuit packaging, and in particular relates to a nano-capacitor three-dimensional integrated system for energy buffering and a preparation method thereof.

Background technique

At present, for portable electronic devices, batteries are still the main energy supply components. Although battery technology continues to evolve, there is still a trade-off between battery capacity and volume and weight. Accordingly, some alternative power supply components with large capacity, light weight and small volume have been researched and developed, such as micro fuel cells, plastic solar cells and energy harvesting systems. In all the cases mentioned above, an energy buffer system is generally required to maintain a continuous and stable energy output. For example, fuel cell systems are generally considered to have slower start-up times and lower kinetic energy. Therefore, a hybrid system in which the fuel cell provides the base power and the buffer system provides the starting power is the best solution. Furthermore, energy harvesting systems rely on energy sources that are not continuously available in the environment; therefore, energy buffering systems are required to maintain uninterrupted operation of the device. Further, energy buffering systems can provide peak loads, whereas energy generating systems cannot. In general, the energy buffer system is either a battery or a capacitor. An important disadvantage of the battery is its limited discharge efficiency. In contrast, capacitors can provide larger discharge currents. Other advantages of using capacitors as energy buffers include longer cycle life and higher power density. In addition to the advantages mentioned above, with proper material and structural design, capacitors are easier to downsize than batteries. Capacitive density and storage capacity can be greatly increased by introducing high aspect ratio structures, such as carbon nanotubes, silicon nanowires, silicon nanoholes, and silicon deep trenches, and depositing high dielectric constant materials in these high aspect ratio structures. Such capacitors prepared by using nanostructures can be called nanocapacitors. However, when the aspect ratio exceeds a certain value, the step coverage and integrity of the material on the surface of the high aspect ratio structure will be greatly weakened, and even the deposited material will have holes on site, which will affect the capacitance performance. In addition, in order to etch a structure with a very large aspect ratio, the precision requirements of the etching equipment are also very high. Further, when the lateral dimensions of these high aspect ratio structures, such as silicon nanopores, are very small, only metals, insulating materials and metals can be deposited directly on their surfaces to form nanocapacitive structures. Due to the high resistivity of silicon materials, the series resistance of nanocapacitors is large, which in turn reduces power density.

SUMMARY OF THE INVENTION

In order to solve the above problems, the present invention discloses a three-dimensional integrated system of nanocapacitors for energy buffering, comprising: a plurality of vertically stacked TSV-nanocapacitor hybrid structures, wherein the monolithic TSV-nanocapacitor hybrid structure includes: :

The through-silicon via structure passing through the silicon substrate is located on the left and right sides of the through-silicon via-nano capacitor hybrid structure, wherein the first insulating medium covers the sidewall of the through-silicon hole; the first copper diffusion barrier layer covers the first insulating medium the sidewall of the first copper seed layer; the first copper seed layer covers the sidewall of the first copper diffusion barrier layer; the first copper metal layer covers the sidewall of the first copper seed layer and completely fills the TSV;

A nanocapacitor structure, located between two through-silicon via structures, includes an array of silicon nanoholes penetrating a silicon substrate; an isolation medium covers the surface of the silicon nanoholes; the bottom metal electrode layer covers the surface of the isolation medium; the second insulating medium covers the bottom metal electrode layer surface, and an opening is formed in a part of the area close to the right TSV; the top metal electrode layer covers the surface of the second insulating medium and completely fills the silicon nanohole;

The top metal contact includes a third insulating medium to form a first trench structure and a fourth trench structure on the upper surfaces of the through silicon via structure on the left and right sides, and the bottoms of the first trench structure and the fourth trench structure expose the first trench structure. a copper diffusion barrier layer, a first copper seed layer and a first copper metal layer; a third insulating medium forms a second trench structure on the surface of the top metal electrode layer, and a third trench structure is formed on the surface of the bottom metal electrode layer, so The second trench structure is adjacent to the first trench structure, the third trench structure is adjacent to the fourth trench structure, and the third insulating medium in the middle region is connected to the bottom metal at the opening. The surfaces of the electrode layers are in contact; the second copper diffusion barrier layer covers the surfaces of the four trenches, and is broken and disconnected in the middle region; the second copper seed layer covers the surface of the second copper diffusion barrier layer; the second copper metal a layer covering the surface of the second copper seed layer;

The bottom metal contact includes a fourth insulating medium. A fifth trench structure and a sixth trench structure are formed on the lower surfaces of the through silicon via structure on the left and right sides, and the fifth trench structure and the top of the sixth trench structure are formed The first copper diffusion barrier layer, the first copper seed layer and the first copper metal layer are exposed; the third copper diffusion barrier layer covers the surfaces of the fifth trench structure and the sixth trench structure, and is not fractured in the middle region. connected; the third copper seed layer covers the surface of the third copper diffusion barrier layer; the third copper metal layer covers the surface of the third copper seed layer;

The third copper metal layer of the TSV-nano capacitor hybrid structure above and the second copper metal layer of the TSV-nano capacitor hybrid structure below are connected by copper-copper bonding through a high-temperature process, so that the upper and lower TSV- The nanocapacitor hybrid structure realizes three-dimensional interconnection; the top metal electrode layers of the upper and lower nanocapacitor structures are electrically connected through the left through-silicon via structure, and the bottom metal electrode layer is electrically connected through the right through-silicon via.

In the three-dimensional integrated system of nanocapacitors for energy buffering of the present invention, preferably, the diameter of the silicon nanoholes ranges from 0.5 to 1 μm, and the depth ranges from 10 to 20 μm.

In the three-dimensional integrated system of nanocapacitors for energy buffering of the present invention, preferably, the thickness of the isolation medium is in the range of 100-200 nm, the thickness of the bottom metal electrode layer is in the range of 50-150 nm, and the thickness of the second insulating medium is in the range of 10-50 nm. , the thickness of the top metal electrode layer ranges from 100 to 300 nm.

In the three-dimensional integrated system of nanocapacitors for energy buffering of the present invention, preferably, the isolation medium is at least one of SiO ₂ , Si ₃ N ₄ , SiON, SiCOH, and SiCOFH.

In the three-dimensional integrated system of nanocapacitors for energy buffering of the present invention, preferably, the bottom metal electrode layer and the top metal electrode layer are at least one of TaN, TiN, WN, MoN, Ni and Ru.

The invention also discloses a preparation method of a nano-capacitor three-dimensional integrated system for energy buffering, which comprises the following steps: making a single-chip through-silicon via-nano-capacitor hybrid structure; The copper is bonded to form a vertical stack connection; wherein, the steps of making a monolithic through-silicon via-nano-capacitor hybrid structure include:

Photolithography and etching are performed on the areas on both sides of the silicon substrate to form through-silicon vias; the first insulating medium, the first copper diffusion barrier layer, the first copper seed crystal layer and the first copper metal layer are sequentially formed, wherein the first The copper metal layer completely fills the TSV; the first copper metal layer, the first copper seed layer, the first copper diffusion barrier layer and the first insulating medium are removed on the top by a chemical mechanical polishing process;

A silicon nanohole array is etched between two adjacent TSVs; an isolation medium, a bottom metal electrode layer, a second insulating medium and a top metal electrode layer are sequentially formed on the surface of the silicon nanohole to obtain a nanocapacitor structure, wherein , the top metal electrode layer is completely filled with silicon nanopores;

The top metal electrode layer, the second insulating dielectric layer, the bottom metal electrode layer and the isolation medium on the tops of the TSVs on both sides are removed by photolithography and etching processes, thereby exposing the tops of the TSVs; photolithography and etching processes are used to remove Part of the top metal electrode layer and part of the second insulating dielectric layer on the right side of the nanocapacitor structure, thereby exposing part of the bottom metal electrode layer;

A third insulating medium is formed, and a trench structure is etched on the surface of the third insulating medium by photolithography and etching processes, wherein the third insulating medium forms a first trench structure on the upper surface of the through silicon via structure on the left and right sides and a fourth trench structure to expose the first copper diffusion barrier layer, the first copper seed layer and the first copper metal layer; the third insulating medium forms a second trench structure on the surface of the top metal electrode layer, and the bottom metal electrode A third trench structure is formed on the surface of the layer, and the second trench structure is adjacent to the first trench structure, and the third trench structure is adjacent to the fourth trench structure;

forming a second copper diffusion barrier layer and a second copper seed layer in sequence; removing the second copper seed layer and the second copper diffusion barrier layer on the surface of the third insulating medium above the nanocapacitor structure, so that the second copper seed layer and the second copper diffusion barrier layer is broken into two regions; the second copper metal layer is formed on the surface of the second copper seed layer; the third insulating medium with a certain thickness is continued to grow on the surface of the third insulating medium in the middle region, so that the middle the top of the third insulating medium of the region is flush with the top of the second copper metal layer;

Thinning the silicon substrate to expose the bottom of the TSV, and making the bottom of the silicon substrate flush with the bottom of the isolation medium of the nanocapacitor structure;

A fourth insulating medium is formed at the bottom of the above structure, and a trench structure is etched on the surface of the fourth insulating medium by photolithography and etching processes, wherein the fourth insulating medium is formed on the lower surfaces of the through silicon via structures on the left and right sides The fifth trench structure and the sixth trench structure expose the lower surfaces of the first copper diffusion barrier layer, the first copper seed crystal layer and the first copper metal layer; the third copper diffusion barrier layer and the first copper metal layer are sequentially formed on the surface of the trench structure. The third copper seed layer; the part of the third copper seed layer and the third copper diffusion barrier layer located on the surface of the fourth insulating medium under the nanocapacitor structure is removed, so that the third copper seed layer and the third copper diffusion barrier layer are broken into There are two areas on the left and right; a third copper metal layer is formed on the surface of the third copper seed layer by electroplating; The bottom is flush with the bottom of the third copper metal layer.

In the preparation method of the nano-capacitor three-dimensional integrated system for energy buffering of the present invention, preferably, copper-copper bonding is performed on the multi-chip TSV-nano-capacitor hybrid structure to form a vertical stack connection, which specifically includes: A plurality of through-silicon via-nano-capacitor hybrid structures are vertically stacked together and heated, so that the third copper metal layer of the TSV-nano-capacitor hybrid structure above and the third copper metal layer of the TSV-nano-capacitor hybrid structure below the through-silicon via-nano capacitor hybrid structure are stacked vertically. The two copper metal layers undergo copper-copper bonding under high temperature conditions and are connected together. The top metal electrode layers of the upper and lower nanocapacitor structures are electrically connected through the left TSV structure, and the bottom metal electrode layer is connected through the right TSV structure. electrical connection.

In the preparation method of the nanocapacitor three-dimensional integrated system for energy buffering of the present invention, preferably, the diameter of the silicon nanopore is in the range of 0.5-1 μm, and the depth is in the range of 10-20 μm.

In the preparation method of the nanocapacitor three-dimensional integrated system for energy buffering of the present invention, preferably, the thickness of the isolation medium is in the range of 100-200 nm, the thickness of the bottom metal electrode layer is in the range of 50-150 nm, and the thickness of the second insulating medium is in the range of 100-200 nm. The thickness of the top metal electrode layer ranges from 100 to 300 nm.

In the preparation method of the nanocapacitor three-dimensional integrated system for energy buffering of the present invention, preferably, the isolation medium is at least one of SiO ₂ , Si ₃ N ₄ , SiON, SiCOH, and SiCOFH.

Description of drawings

Figure 1 is a flow chart of a method for fabricating a nanocapacitor three-dimensional integrated system for energy buffering.

2 to 21 are schematic structural diagrams of each step of a method for preparing a three-dimensional integrated system of nanocapacitors for energy buffering

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the specific The embodiments are only used to explain the present invention, and are not intended to limit the present invention. The described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for convenience The invention is described and simplified without indicating or implying that the device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

Furthermore, numerous specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques and techniques, in order to provide a clearer understanding of the present invention. However, as can be understood by one skilled in the art, the present invention may be practiced without these specific details. Unless specifically indicated below, various parts of the device may be constructed of materials known to those skilled in the art, or materials developed in the future with similar functions may be employed.

The technical solutions of the present invention will be further described below with reference to accompanying drawings 1-21. Fig. 1 is a flow chart of a method for preparing a three-dimensional integrated system of nanocapacitors for energy buffering, and Figs. 2 to 21 show structural schematic diagrams of each step of the method for preparing a three-dimensional integrated system of nanocapacitors for energy buffering. As shown in Figure 1, the specific preparation steps are:

Step S1 : making through-silicon vias and performing first wiring in the through-silicon vias. Specifically, first, the photoresist is spin-coated and the positions of the TSVs are defined by the exposure and development process; then, the regions on both sides of the silicon substrate 200 are etched by the deep plasma etching (DRIE) process. Through silicon vias are formed by etching, and the resulting structure is shown in FIG. 2 . The diameter of the TSV is 5-10 μm, and the depth is 20-50 μm; the plasma for etching the silicon substrate 200 can be selected from at least one of CF ₄ and SF ₆ .

Next, a chemical vapor deposition process is used to deposit a layer of SiO ₂ film on the surface of the through silicon hole as the first insulating medium 201; then, a physical vapor deposition process is used to sequentially deposit a layer of TaN film and a layer of Co film on the surface of the first insulating medium 201 , respectively as the first copper diffusion barrier layer 202 and the first copper seed layer 203; further electroplating a first copper metal layer 204 on the surface of the first copper seed layer 203 by electroplating process, and the first copper metal layer 204 is completely The TSVs are filled and the resulting structure is shown in Figure 3.

Finally, a chemical mechanical polishing process is used to remove the top first copper metal layer 204 , the first copper seed layer 203 , the first copper diffusion barrier layer 202 and the first insulating medium 201 , and the resulting structure is shown in FIG. 4 . In this embodiment, a deep reactive ion etching process is used to obtain the TSV structure, but the present invention is not limited to this, and dry etching such as ion milling etching, plasma etching, reactive ion etching, deep At least one of reactive ion etching, laser ablation, or wet etching by using an etchant solution. In addition, in this embodiment, SiO ₂ is used as the first insulating medium, TaN is used as the first copper diffusion barrier layer, and Co thin film is used as the first copper seed layer, but the present invention is not limited to this, and SiO ₂ , Si can be selected ₃ At least one of N ₄ , SiON, SiCOH, and SiCOFH is used as the first insulating medium; at least one of TaN, TiN, ZrN, and MnSiO ₃ can be selected as the first copper diffusion barrier layer; Cu, Ru, Co, At least one of RuCo, CuRu, and CuCo serves as the first copper seed layer. The growth mode of the first insulating medium, the first copper diffusion barrier layer and the first copper seed layer can be selected from at least one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

Step S2: etching a silicon nanohole array between two adjacent through silicon vias and preparing a nanocapacitor. Specifically, first, a photoresist is spin-coated and a pattern of silicon nanoholes is defined through exposure and development processes. Then, a deep plasma etching (DRIE) process is used to etch the region of the silicon substrate 200 between the two TSV structures to form a silicon nanohole array, and the obtained structure is shown in FIG. 5 . The diameter of the silicon nanoholes ranges from 0.5 to 1 μm and the depth ranges from 10 to 20 μm; the plasma for etching the silicon substrate 200 can be selected from at least one of CF ₄ and SF ₆ .

Then, a chemical vapor deposition process is used to deposit a layer of SiO ₂ film on the surface of the silicon nanopore as the isolation medium 205; then, a physical vapor deposition process is used to sequentially deposit a layer of TiN film, a layer of Al ₂ O ₃ film and A layer of TiN film is used as the bottom metal electrode layer 206, the second insulating medium 207 and the top metal electrode layer 208 respectively, and the top metal electrode layer 208 is completely filled with silicon nanopores, and the resulting structure is shown in FIG. 6 . The thickness of the isolation medium 205 is in the range of 100-200 nm, the thickness of the bottom metal electrode layer 206 is in the range of 50-150 nm, the thickness of the second insulating medium 207 is in the range of 10-50 nm, and the thickness of the top metal electrode layer 208 is in the range of 100-150 nm. 300nm. In this embodiment, a deep reactive ion etching process is used to obtain the TSV structure, but the present invention is not limited to this, and dry etching such as ion milling etching, plasma etching, reactive ion etching, deep At least one of reactive ion etching, laser ablation, or wet etching by using an etchant solution. In addition, in this embodiment, SiO ₂ is used as the isolation medium, TiN is used as the bottom and top metal electrode layers, and the Al ₂ O ₃ film is used as the second insulating medium layer, but the invention is not limited to this, and SiO ₂ , Si can be selected ₃ At least one of N ₄ , SiON, SiCOH, and SiCOFH is used as the isolation medium; at least one of TaN, TiN, WN, MoN, Ni and Ru can be selected as the bottom and top metal electrode layers; Al ₂ O ₃ , ZrO can be selected _2. At least one of TiO ₂ , HfO ₂ , La ₂ O ₃ , HfZrO, HfAlO, and HfTiO as the second insulating medium layer. The growth mode of the isolation medium, the second insulating medium, the bottom metal electrode layer and the top metal electrode layer can be selected from at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and pulsed laser deposition.

Step S3: Perform a second wiring on the top so that the left and right TSV structures are electrically connected to the upper and lower electrodes of the nanocapacitor respectively. First, the top metal electrode layer 208, the second insulating dielectric layer 207, the bottom metal electrode layer 206 and the isolation dielectric 205 on the tops of the TSVs on both sides are removed by photolithography and etching processes, thereby exposing the top structure of the TSVs; then Part of the top metal electrode layer 208 and part of the second insulating dielectric layer 207 on the right side of the nanocapacitor structure are removed by photolithography and etching, thereby exposing part of the bottom metal electrode layer 206. The resulting structure is shown in FIG. 7 .

Then, a layer of SiO ₂ film 209 is deposited on top of the above structure as a third insulating medium by using a chemical vapor deposition process, and the obtained structure is shown in FIG. 8 .

A trench structure is further etched on the surface of the third insulating medium 209 by photolithography and etching processes, wherein the third insulating medium 209 forms first and fourth trench structures on the upper surfaces of the through silicon via structures on the left and right sides, and The bottoms of the first and fourth trench structures expose the first copper diffusion barrier layer 202 , the first copper seed layer 203 and the first copper metal layer 204 ; the third insulating medium 209 forms a second layer on the surface of the top metal electrode layer 208 For the trench structure, a third trench structure is formed on the surface of the bottom metal electrode layer 206, and the second trench structure is adjacent to the first trench structure, and the third trench structure is adjacent to the fourth trench structure. The resulting trench structure is shown in Figure 9 shown.

A layer of TaN film and a layer of Co film are successively deposited on the surface of the trench structure by chemical vapor deposition process as the second copper diffusion barrier layer 210 and the second copper seed layer 211 respectively. The resulting structure is shown in FIG. 10 .

Next, the second copper seed layer 211 and the second copper diffusion barrier layer 210 located on the surface of the third insulating medium 209 above the nanocapacitor structure are removed by photolithography and etching, so that the second copper seed layer 211 and the second copper seed layer 211 and the second copper diffusion barrier layer 210 are removed. The copper diffusion barrier layer 210 is broken into two regions on the left and right, and the resulting structure is shown in FIG. 11 .

Subsequently, a layer of Cu material is plated on the surface of the second copper seed layer 211 by an electroplating process as the second copper metal layer 212 , and the obtained structure is shown in FIG. 12 .

Finally, a SiO ₂ film of a certain thickness is continued to grow on the surface of the third insulating medium 209 in the middle area by a chemical vapor deposition process to ensure that the top of the third insulating medium 209 in the middle area is flush with the top of the second copper metal layer 212, and the resulting structure As shown in Figure 13. In this embodiment, SiO ₂ is used as the third insulating medium, TaN is used as the second copper diffusion barrier layer, and Co thin film is used as the second copper seed layer, but the invention is not limited to this, and SiO ₂ and Si ₃ N can be selected. _4. At least one of SiON, SiCOH, and SiCOFH is used as the _third insulating medium; at least one of TaN, TiN, ZrN, and MnSiO can be selected as the second copper diffusion barrier; Cu, Ru, Co, RuCo, At least one of CuRu and CuCo serves as the second copper seed layer. The growth mode of the third insulating medium, the second copper diffusion barrier layer and the second copper seed layer can be selected from at least one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

Step S4 : thinning the silicon wafer to expose the bottom of the TSV structure, and performing a third wiring to lead out the bottom metal contact of the TSV. First, the silicon substrate 200 is thinned by mechanical grinding and chemical mechanical polishing, so as to expose the bottom structure of the TSV, and the bottom of the silicon substrate 200 is flush with the bottom of the isolation medium 205 of the nanocapacitor. The obtained structure is shown in the figure 14 shown.

Then, a chemical vapor deposition process is used to deposit a layer of SiO ₂ film on the bottom of the above structure as the fourth insulating medium 213 , and the obtained structure is shown in FIG. 15 .

Further, a trench structure is etched on the surface of the fourth insulating medium 213 by using photolithography and etching processes, wherein the fourth insulating medium 213 forms fifth and sixth trench structures on the lower surfaces of the through silicon via structures on the left and right sides , and the fifth and sixth trench structures expose the lower surfaces of the first copper diffusion barrier layer 202 , the first copper seed layer 203 and the first copper metal layer 204 , and the resulting trench structures are shown in FIG. 16 .

Further, a layer of TaN thin film and a layer of Co thin film are sequentially deposited on the surface of the trench structure by chemical vapor deposition process as the third copper diffusion barrier layer 214 and the third copper seed layer 215 respectively. The resulting structure is shown in FIG. 17 .

Immediately after, photolithography and etching processes are used to remove part of the third copper seed layer 215 and the third copper diffusion barrier layer 214 located on the surface of the fourth insulating medium 213 under the nanocapacitor structure, so that the third copper seed layer 215 and the third copper diffusion barrier layer 214 are removed. The third copper diffusion barrier layer 214 is broken into left and right regions, and the resulting structure is shown in FIG. 18 .

Subsequently, a layer of Cu material is plated on the surface of the third copper seed layer 215 by an electroplating process as the third copper metal layer 216 , and the obtained structure is shown in FIG. 19 .

Finally, a SiO ₂ film of a certain thickness is continued to grow on the surface of the fourth insulating medium 213 in the middle area by a chemical vapor deposition process to ensure that the bottom of the fourth insulating medium 213 in the middle area is flush with the bottom of the third copper metal layer 216, and the resulting structure As shown in Figure 20. In this embodiment, SiO ₂ is used as the fourth insulating medium, TaN is used as the third copper diffusion barrier layer, and Co thin film is used as the third copper seed layer, but the invention is not limited to this, and SiO ₂ and Si ₃ N can be selected. _4. At least one of SiON, SiCOH, and SiCOFH is used as the fourth insulating medium; at least one of TaN, TiN, ZrN, and MnSiO can be selected as the _third copper diffusion barrier; Cu, Ru, Co, RuCo, At least one of CuRu and CuCo serves as the third copper seed layer. The growth mode of the fourth insulating medium, the third copper diffusion barrier layer and the third copper seed layer can be selected from at least one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition. .

Step S5 : copper-copper bonding is performed on two identical TSV-nanocapacitor structures to form a vertical stack connection. First, two monolithic through-silicon via-nanocapacitor hybrid structures formed by the above steps S1-S4 are vertically stacked together; then, they are placed in a tube furnace for heating at a temperature range of 300-400°C. The third copper metal layer 216 of the upper TSV-nanocapacitor hybrid structure and the second copper metal layer 212 of the lower TSV-nanocapacitor hybrid structure undergo copper-copper bonding under high temperature conditions and are connected together , the resulting structure is shown in Figure 21. The top metal electrode layers of the upper and lower nanocapacitors are electrically connected through the left through-silicon vias, and the bottom metal electrode layers are electrically connected through the right through-silicon vias; that is to say, the upper and lower nanocapacitors are connected in parallel. In this embodiment, two nanocapacitor structures are connected in vertical parallel through TSVs, but the present invention is not limited to this, and more nanocapacitor structures can also be vertically connected in parallel through TSVs in the above manner.

FIG. 21 is a schematic diagram of a three-dimensional integrated system of nanocapacitors for energy buffering according to the present invention. As shown in FIG. 21 , the nanocapacitor three-dimensional integrated system includes: two vertically stacked TSV-nanocapacitor hybrid structures 100 . Wherein, the monolithic TSV-nanocapacitor hybrid structure 100 includes:

The TSV structures penetrating the silicon substrate 200 are located on the left and right sides of the TSV-nanocapacitor hybrid structure, respectively. The first insulating medium 201 covers the sidewall of the TSV; the first copper diffusion barrier layer 202 covers the sidewall of the first insulating medium 201 ; the first copper seed layer 203 covers the sidewall of the first copper diffusion barrier layer 202 ; The first copper metal layer 204 covers the sidewall of the first copper seed layer 203 and completely fills the TSV.

The nanocapacitor structure is located between the two through-silicon via structures 101 . The basic skeleton of the nanocapacitor structure 102 is an array of silicon nanoholes penetrating the silicon substrate 200; the isolation medium 205 covers the surface of the silicon nanohole; the bottom metal electrode layer 206 covers the surface of the isolation medium 205; the second insulating medium 207 covers the bottom metal electrode The surface of the layer 206; the top metal electrode layer 208 covers the surface of the second insulating medium 207 and completely fills the silicon nanoholes. In addition, the bottom metal electrode layer 206 is exposed and not covered by the second insulating medium 207 in a partial area close to the right TSV.

Top metal contacts. The third insulating medium 209 forms first and fourth trench structures on the upper surfaces of the left and right TSV structures, and the bottoms of the first and fourth trench structures expose the first copper diffusion barrier layer 202, the first The copper seed layer 203 and the first copper metal layer 204; the third insulating medium 209 forms a second trench structure on the surface of the top metal electrode layer 208, and forms a third trench structure on the surface of the bottom metal electrode layer 206, and the second trench The trench structure is adjacent to the first trench structure, and the third trench structure is adjacent to the fourth trench structure. The second copper diffusion barrier layer 210 covers the surfaces of the four trenches, and is broken and disconnected in the middle region; the second copper seed layer 211 covers the surface of the second copper diffusion barrier layer 210; the second copper metal layer 212 covers the second The surface of the copper seed layer 211 . The left TSV structure and the top metal electrode layer 208 of the nanocapacitor are electrically connected through the first and second trench structures; the right TSV structure and the bottom metal electrode layer 206 of the nanocapacitor pass through the third and fourth trenches The slot structure enables electrical communication.

Bottom metal contact. The fourth insulating medium 213 forms fifth and sixth trench structures on the lower surfaces of the left and right TSV structures, and the tops of the fifth and sixth trench structures expose the first copper diffusion barrier layer 202, the first The copper seed layer 203 and the first copper metal layer 204 . The third copper diffusion barrier layer 214 covers the surfaces of the fifth and sixth trenches, and is broken and disconnected in the middle region; the third copper seed layer 215 covers the surface of the third copper diffusion barrier layer 214; the third copper metal layer 216 Cover the surface of the third copper seed layer 215 .

The second copper metal layer 212 and the third copper metal layer 216 are connected by copper-copper bonding through a high-temperature process, so that the two upper and lower TSV-nanocapacitor hybrid structures 100 realize three-dimensional interconnection. In addition, the top metal electrode layers of the upper and lower nanocapacitors are electrically connected through the left through-silicon vias, and the bottom metal electrode layers are electrically connected through the right through-silicon vias; that is to say, the upper and lower nanocapacitors are connected in parallel.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be included within the protection scope of the present invention.

Claims (10)

1. a nano-capacitor three-dimensional integrated system for energy buffering, is characterized in that, Including: multiple vertically stacked TSV-nanocapacitor hybrid structures, Among them, the monolithic TSV-nanocapacitor hybrid structure includes: The TSV structure penetrating the silicon substrate (200) is located on the left and right sides of the TSV-nano capacitor hybrid structure, wherein the first insulating medium (201) covers the sidewalls of the TSV; the first copper diffusion barrier A layer (202) covers the sidewall of the first insulating medium (201); a first copper seed layer (203) covers the sidewall of the first copper diffusion barrier layer (202); a first copper metal layer (204) ) covers the sidewalls of the first copper seed layer (203) and completely fills the TSVs; A nanocapacitor structure, located between two TSV structures, includes a silicon nanohole array penetrating the silicon substrate (200); an isolation medium (205) covers the surface of the silicon nanoholes; and a bottom metal electrode layer (206) covers the entire surface of the silicon nanoholes. the surface of the isolation medium (205); the second insulating medium (207) covers the surface of the bottom metal electrode layer (206), and forms an opening in a part of the region close to the through silicon via on the right side; the top metal electrode layer (208) Covering the surface of the second insulating medium (207) and completely filling the silicon nanopore; The top metal contact includes a first trench structure and a fourth trench structure formed by a third insulating medium (209) on the upper surfaces of the TSV structures on the left and right sides, the first trench structure and the fourth trench The bottom of the trench structure exposes the first copper diffusion barrier layer (202), the first copper seed layer (203) and the first copper metal layer (204); the third insulating medium (209) is in the a second trench structure formed on the surface of the top metal electrode layer (208), a third trench structure formed on the surface of the bottom metal electrode layer (206), the second trench structure adjacent to the first trench structure , the third trench structure is adjacent to the fourth trench structure, and the third insulating medium (209) in the middle region is in contact with the surface of the bottom metal electrode layer (206) at the opening; the second A copper diffusion barrier layer (210) covers the surfaces of the four trenches, and is broken and disconnected in the middle region; a second copper seed layer (211) covers the surface of the second copper diffusion barrier layer (210); a second copper A metal layer (212) covers the surface of the second copper seed layer (211); The bottom metal contact includes a fifth trench structure and a sixth trench structure formed by a fourth insulating medium (213) on the lower surfaces of the TSV structures on the left and right sides, the fifth trench structure and the sixth trench The top of the trench structure exposes the first copper diffusion barrier layer (202), the first copper seed layer (203) and the first copper metal layer (204); the third copper diffusion barrier layer (214) covers The surfaces of the fifth trench structure and the sixth trench structure are broken and disconnected in the middle region; the third copper seed layer (215) covers the surface of the third copper diffusion barrier layer (214); the third A copper metal layer (216) covers the surface of the third copper seed layer (215); The third copper metal layer (216) of the TSV-nanocapacitor hybrid structure above and the second copper metal layer (212) of the TSV-nanocapacitor hybrid structure below realize copper-copper through a high temperature process are bonded and connected, so that the upper and lower through-silicon via-nano-capacitor hybrid structures realize three-dimensional interconnection; the top metal electrode layers (208) of the upper and lower nano-capacitor structures are electrically connected through the left through-silicon via structure, and the bottom metal electrode layer (208) 206) Electrically connected through the right TSV. 2. the nano-capacitor three-dimensional integrated system for energy buffering according to claim 1, The diameter of the silicon nanopores ranges from 0.5 to 1 μm, and the depth ranges from 10 to 20 μm. 3. The nanocapacitor three-dimensional integrated system for energy buffering according to claim 1, The thickness of the isolation medium (205) is in the range of 100-200 nm, the thickness of the bottom metal electrode layer (206) is in the range of 50-150 nm, and the thickness of the second insulating medium (207) is in the range of 10-50 nm. The thickness of the top metal electrode layer (208) ranges from 100 to 300 nm. 4. The nanocapacitor three-dimensional integrated system for energy buffering according to claim 1, The isolation medium (205) is at least one of SiO ₂ , Si ₃ N ₄ , SiON, SiCOH, and SiCOFH. 5. The nanocapacitor three-dimensional integrated system for energy buffering according to claim 1, The bottom metal electrode layer (206) and the top metal electrode layer (208) are at least one of TaN, TiN, WN, MoN, Ni, and Ru. 6. a preparation method of a nano-capacitor three-dimensional integrated system for energy buffering, characterized in that, Include the following steps: Fabrication of monolithic TSV-nanocapacitor hybrid structure; Copper-copper bonding of multiple through-silicon via-nanocapacitor hybrid structures to form vertical stack connections; Wherein, the steps of fabricating the monolithic TSV-nano capacitor hybrid structure include: Photolithography and etching are performed on regions on both sides of the silicon substrate (200) to form through silicon vias; a first insulating medium (201), a first copper diffusion barrier layer (202), and a first copper seed crystal layer (203) are sequentially formed ) and a first copper metal layer (204); wherein, the first copper metal layer (204) completely fills the through silicon vias; the first copper metal layer (204), the first copper metal layer (204) and the first copper metal layer (204) on the top are removed by chemical mechanical polishing process. a copper seed layer (203), the first copper diffusion barrier layer (202), and the first insulating medium (201); A silicon nanohole array is etched between two adjacent TSVs; an isolation medium (205), a bottom metal electrode layer (206), a second insulating medium (207) and a top metal are sequentially formed on the surface of the silicon nanoholes an electrode layer (208) to obtain a nanocapacitive structure, wherein the top metal electrode layer (208) is completely filled with silicon nanopores; The top metal electrode layer (208), the second insulating dielectric layer (207), the bottom metal electrode layer (206) and the isolation dielectric on the tops of the TSVs on both sides are removed by photolithography and etching processes (205), thereby exposing the top of the TSV; using photolithography and etching processes to remove part of the top metal electrode layer (208) and part of the second insulating dielectric layer (207) on the right side of the nanocapacitor structure, thereby exposing part of the bottom metal electrode layer (206); A third insulating medium (209) is formed, and a trench structure is etched on the surface of the third insulating medium (209) using photolithography and etching processes, wherein the third insulating medium (209) is on the left and right sides A first trench structure and a fourth trench structure are formed on the upper surface of the TSV structure, so that the first copper diffusion barrier layer (202), the first copper seed layer (203) and the first copper The metal layer (204) is exposed; the third insulating medium (209) forms a second trench structure on the surface of the top metal electrode layer (208), and forms a third trench on the surface of the bottom metal electrode layer (206) structure, and the second trench structure is adjacent to the first trench structure, and the third trench structure is adjacent to the fourth trench structure; forming a second copper diffusion barrier layer (210) and a second copper seed layer (211) in sequence; removing the second copper seed layer (211) on the surface of the third insulating medium (209) above the nanocapacitor structure ) and the second copper diffusion barrier layer (210), so that the second copper seed layer (211) and the second copper diffusion barrier layer (210) are broken into left and right regions; The second copper metal layer (212) is formed on the surface of the copper seed layer (211); the third insulating medium of a certain thickness is continuously grown on the surface of the third insulating medium (209) in the middle region, so that the third insulating medium in the middle region is The top of the third insulating medium (209) is flush with the top of the second copper metal layer (212); Thinning the silicon substrate (200) to expose the bottom of the TSV, and making the bottom of the silicon substrate (200) flush with the bottom of the isolation medium (205) of the nanocapacitor structure; A fourth insulating medium (213) is formed at the bottom of the above structure, and a trench structure is etched on the surface of the fourth insulating medium (213) by using photolithography and etching processes, wherein the fourth insulating medium (213) A fifth trench structure and a sixth trench structure are formed on the lower surfaces of the TSV structures on the left and right sides, so that the first copper diffusion barrier layer (202), the first copper seed layer (203) and the The lower surface of the first copper metal layer (204) is exposed; a third copper diffusion barrier layer (214) and a third copper seed layer (215) are sequentially formed on the surface of the trench structure; the fourth insulating layer located under the nanocapacitor structure is removed part of the third copper seed layer (215) and the third copper diffusion barrier layer (214) on the surface of the dielectric (213), so that the third copper seed layer (215) and the third copper are diffused The barrier layer (214) is broken into left and right regions; a third copper metal layer (216) is formed on the surface of the third copper seed layer (215) by an electroplating process; the fourth insulating medium (213) in the middle region ) surface continues to grow the fourth insulating medium (213) with a certain thickness, so that the bottom of the fourth insulating medium (213) in the middle region is flush with the bottom of the third copper metal layer (216). 7. the preparation method of the nano-capacitor three-dimensional integrated system for energy buffering according to claim 6, is characterized in that, The steps of copper-copper bonding of multiple through-silicon via-nanocapacitor hybrid structures to form a vertical stack connection, specifically including: A plurality of TSV-nano capacitor hybrid structures are vertically stacked together and heated, so that the third copper metal layer (216) of the upper TSV-nano capacitor hybrid structure is connected to the lower TSV-nano capacitor. The second copper metal layer (212) of the capacitive hybrid structure undergoes copper-copper bonding under high temperature conditions and is connected together, The top metal electrode layers (208) of the upper and lower nanocapacitor structures are electrically connected through the left TSV structure, and the bottom metal electrode layer (206) is electrically connected through the right TSV structure. 8. the preparation method of the nano-capacitor three-dimensional integrated system for energy buffering according to claim 6, is characterized in that, The diameter of the silicon nanopores ranges from 0.5 to 1 μm, and the depth ranges from 10 to 20 μm. 9. The preparation method of the nanocapacitor three-dimensional integrated system for energy buffering according to claim 6, wherein, The thickness of the isolation medium (205) is in the range of 100-200 nm, the thickness of the bottom metal electrode layer (206) is in the range of 50-150 nm, and the thickness of the second insulating medium (207) is in the range of 10-50 nm. The thickness of the top metal electrode layer (208) ranges from 100 to 300 nm. 10. The preparation method of the nanocapacitor three-dimensional integrated system for energy buffering according to claim 6, wherein, The isolation medium (205) is at least one of SiO ₂ , Si ₃ N ₄ , SiON, SiCOH, and SiCOFH.

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