CN105185719B - A kind of hybrid bonded method of bayonet type - Google Patents
A kind of hybrid bonded method of bayonet type Download PDFInfo
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- CN105185719B CN105185719B CN201510354733.XA CN201510354733A CN105185719B CN 105185719 B CN105185719 B CN 105185719B CN 201510354733 A CN201510354733 A CN 201510354733A CN 105185719 B CN105185719 B CN 105185719B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/0805—Shape
- H01L2224/08057—Shape in side view
- H01L2224/08058—Shape in side view being non uniform along the bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/802—Applying energy for connecting
- H01L2224/80201—Compression bonding
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Abstract
The present invention relates to a kind of hybrid bonded method of bayonet type.Comprise the following steps：Multiple metal depressions are formed on the insulating layer of upper substrate；Multiple metal protuberances are formed on the insulating layer of lower substrate；The rising height of the metal protuberance is more than the concave cup depth of the metal；The substrate up and down is cleaned, forms hydrophilic active surface；Upper and lower substrate is aligned, apply pressure, multiple metal protuberances on lower substrate are made to penetrate respectively on the upper substrate in corresponding multiple metal depressions, while the insulating layer of the insulating layer of the upper substrate and the lower substrate is also bonded together, and forms firm pre- bonding structure；Annealing.The present invention uses hybrid bonded method; the requirement of interface flat degree will be converted into metal protuberance and concave control; greatly reduce hybrid bonded technology difficulty; using contemporary integrated circuits manufacturing process can scale manufacture meet the wafer of hybrid bonded requirement; production cost is significantly reduced, improves production efficiency.
Description
Technical field
The present invention relates to a kind of hybrid bonded method, more particularly to a kind of hybrid bonded method of bayonet type.
Background technology
With development of requirement of the people to electronic product to directions such as miniaturization, multi-functional, environment-friendly types, people make great efforts to seek
Ask and more do electronic system smaller, integrated level is higher and higher, and function the more is done the more more, more and more by force.Thereby produce many new skills
Art, new material and new design, such as the technology such as three-dimensional stacked encapsulation are exactly the Typical Representative of these technologies.Ultra-large integrated
Circuit development is increasingly close in the case of physics limit, all advantageous three dimensional integrated circuits in terms of physical size and cost
It is extension Moore's Law and solves the problems, such as the effective way of Advanced Packaging.Three-dimensional stacked encapsulating structure can be directly by multiple bare chips
Or substrate is stacked up by way of bonding, realize the metal interconnection structure on three-dimensional, greatly reduce interconnection away from
From, transmission speed is improved, it is integrated in three-dimensional structure so as to fulfill a system or some function.And wafer bond techniques
One of key technology that exactly three-dimensional circuit integrates, especially hybrid bonded technology can be realized while two panels wafer bonding
The interconnected of thousands of chips, can greatly improve chip performance and cost-effective.
The difficulty of hybrid bonded technology is the interconnected for realizing metal and maintains the high yield of this interconnection.But
Common hybrid bonded processing procedure para-linkage interface is just high, it is desirable to which the high low head of micro interface is less than 1 to 3 nanometers, traditional work
Skill is difficult to produce so flat interface, can not also be accomplished scale production even if the interface that reaches requirement is produced.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of hybrid bonded method of bayonet type, solve prior art key
Close interface flat and require technical problem that is high, being difficult to large-scale production.
The technical solution that the present invention solves above-mentioned technical problem is as follows：A kind of hybrid bonded method of bayonet type, including it is following
Step：
Step 1, there is provided the first wafer and the second wafer, first wafer has the upper substrate of bonding to be mixed, described
Second wafer has the lower substrate of bonding to be mixed, the upper substrate bottom of first wafer and the lower substrate of second wafer
Top is each formed with insulating layer.
Step 2, forms multiple metal depressions on first wafer on the insulating layer of substrate；
Step 3, forms multiple metal protuberances, the lower insulated substrate under second wafer on the insulating layer of substrate
The position of multiple metal protuberances is corresponded with the concave position of multiple metals on the upper insulated substrate layer on layer；The metal
The rising height of projection is all higher than the concave cup depth of corresponding metal；
Step 4, cleans first wafer and the second wafer, removes on the upper substrate and the lower substrate
The pollutant of attachment；
Step 5, the substrate up and down of be surface-treated two wafers is aligned, and applies pressure by bonding apparatus, under making
Multiple metal protuberances on substrate penetrate on the upper substrate in corresponding multiple metal depressions respectively, while the upper substrate
The insulating layer of insulating layer and the lower substrate is also bonded together, and forms firm pre- bonding structure；
Step 6, the first wafer for forming pre- bonding structure and the second wafer are annealed.
Based on the above technical solutions, the present invention can also be improved as follows.
Further, hydrophily is formed on the insulating layer of the lower substrate after the insulating layer of upper substrate after cleaning and cleaning to live
Property surface.
Further, the concave width of the metal is more than the width of the metal protuberance.
Further, the concave width dimensions of the metal are 30nm~50um；The width dimensions of the metal protuberance are
10nm~45um.
Further, the concave cup depth of the metal is 3nm~450nm.
Further, the rising height of the metal protuberance is 10nm~500nm.
Further, the insulating layer on substrate up and down be silicon dioxide insulating layer, silicon nitride dielectric layer, silicon oxynitride it is exhausted
Edge layer, carborundum insulating layer or carbon mix up silicon oxide dielectric layer.
Further, the metal depression and the metal protuberance have copper, aluminium, tin, gold or indium plating filling to be formed.
Further, in the step 5, pressure applied is 1~50,000 newton.
Further, in the step 6, annealing region is 200~450 DEG C, when annealing time is small more than 0.15.
The beneficial effects of the invention are as follows：The present invention uses hybrid bonded method, during hybrid bonded, the gold of projection
Belonging to can be deep into through the interface of bonding in the metal depression of another side wafer, and the requirement of interface flat degree will be converted into
To metal protuberance and concave control, hybrid bonded technology difficulty is greatly reduced, using contemporary integrated circuits manufacturing process
Can scale manufacture meet the wafer of hybrid bonded requirement, significantly reduce production cost, improve production efficiency.
Brief description of the drawings
Fig. 1 is the flow chart of the hybrid bonded method of the present invention；
Fig. 2 a to Fig. 2 c are that two substrate of the embodiment of the present invention completes the hybrid bonded corresponding structure diagram of technical process.
Embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the present invention.
As shown in Figure 1, be the flow diagram of a kind of hybrid bonded method of bayonet type in the embodiment of the present invention, including it is following
Step：
Step 1, there is provided the first wafer and the second wafer, first wafer has the upper substrate of bonding to be mixed, described
Second wafer has the lower substrate of bonding to be mixed, the upper substrate bottom of first wafer and the lower substrate of second wafer
Top is each formed with silicon dioxide insulating layer.In other embodiments, insulating layer can also be silicon nitride dielectric layer, silicon oxynitride
Insulating layer, carborundum insulating layer or carbon mix up any one of silicon oxide dielectric layer.
Step 2, forms multiple metal depressions 01 on first wafer, such as schemes on the silicon dioxide insulating layer of substrate
Shown in 2a；In the present embodiment, metal depression has metallic copper plating filling to be formed, in other embodiments, can also be aluminium,
The metal platings such as tin, gold or indium fill to be formed；The concave cup depth of metal is 100nm, in other embodiments, described
The concave cup depth of metal can be between 3nm~450nm arbitrary value, such as 10nm, 80nm, 120nm, 200nm, 320nm,
400nm etc..
Step 3, forms multiple metal protuberances 02 under second wafer on the silicon dioxide insulating layer of substrate, described
The position of multiple metals depressions 01 is one by one on the position of multiple metal protuberances and the upper insulated substrate layer on lower insulated substrate layer
It is corresponding；And the rising height of the metal protuberance 02 is all higher than the concave cup depth of metal corresponding thereto, such as Fig. 2 b institutes
Show；In the present embodiment, the rising height of the metal protuberance 02 is 120nm, in other embodiments, the metal protuberance 02
Arbitrary value of the rising height between 10nm~500nm, such as 20nm, 50nm, 150nm, 200nm, 350nm, 480nm etc..And
Preferably, the width of metal depression 01 is more than the width of the metal protuberance 02, in the present embodiment, the metal depression 01
Width be 300nm, the width of the metal protuberance 02 is 200nm, with facilitate the metal protuberance 02 preferably insertion described in
Among metal depression 01, in other embodiments, the arbitrary value of the width dimensions of metal depression 01 between 30nm~50um；
Arbitrary value of the width dimensions of the metal protuberance 02 between 10nm~45um, for example the width of metal depression 01 is 30um, institute
The width for stating metal protuberance 02 is 20um.
Step 4, cleans first wafer and the second wafer, removes on the upper substrate and the lower substrate
The pollutant of attachment, and hydrophilic active surface is formed on the insulating layer of the insulating layer of substrate and the lower substrate on described.
Step 5, the substrate up and down of be surface-treated two wafers is aligned, and applies 30,000 newton by bonding apparatus
Pressure, multiple metal protuberances 02 on lower substrate is penetrated respectively on the upper substrate in corresponding multiple metals depression 01,
The insulating layer of the upper substrate and the insulating layer of the lower substrate are also bonded together at the same time, form firm pre- bonding structure,
As shown in Figure 2 c；In other embodiments, pressure applied scope the newton of 1,000 newton~50,000 arbitrary value, such as 20
Thousand newton, 35,000 newton etc., make the insulating layer of the upper substrate and the insulating layer of the lower substrate be bonded together.
Step 6, the wafer after pre- bonding is annealed.In the present embodiment, annealing temperature is 300 DEG C, and annealing half is small
When, the thermal expansion that annealing temperature reaches metallic copper can produce extruding so as to fulfill the fusion of the crystal grain of interracial contact and copper.At other
In embodiment, the annealing temperature used is the arbitrary value between 200~450 DEG C, such as 380 DEG C, 420 DEG C etc., and annealing time is more than
0.15 it is small when.
The present invention uses hybrid bonded method, and during hybrid bonded, the metal of projection can pass through the interface of bonding
It is deep into the metal depression of another side wafer, the requirement of interface flat degree will be converted into metal protuberance and concave
Control, greatly reduces hybrid bonded technology difficulty, can scale manufacture symbol using contemporary integrated circuits manufacturing process
The wafer of hybrid bonded requirement is closed, significantly reduces production cost, improves production efficiency.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent replacement, improvement and so on, should all be included in the protection scope of the present invention.
Claims (7)
1. a kind of hybrid bonded method of bayonet type, comprises the following steps：
Step 1, there is provided the first wafer and the second wafer, upper substrate of first wafer with bonding to be mixed, described second
Wafer has the lower substrate of bonding to be mixed, the upper substrate bottom of first wafer and the lower substrate top of second wafer
It is each formed with insulating layer；
Step 2, forms multiple metal depressions on first wafer on the insulating layer of substrate；
Step 3, forms multiple metal protuberances under second wafer on the insulating layer of substrate, on the lower insulated substrate layer
The position of multiple metal protuberances is corresponded with the concave position of multiple metals on the upper insulated substrate layer；The metal protuberance
Rising height be all higher than the concave cup depth of corresponding metal, the concave cup depth of metal for 3nm~
450nm, the rising height of the metal protuberance is 10nm~500nm；
Step 4, cleans first wafer and the second wafer, removes and adheres on the upper substrate and the lower substrate
Pollutant；
Step 5, the substrate up and down of be surface-treated two wafers is aligned, and is applied pressure by bonding apparatus, is made lower substrate
On multiple metal protuberances penetrate respectively on the upper substrate in corresponding multiple metals depression, while the insulation of the upper substrate
The insulating layer of layer and the lower substrate is also bonded together, and forms firm pre- bonding structure；
Step 6, the first wafer for forming pre- bonding structure and the second wafer are annealed；
The metal depression and the metal protuberance are formed by the plating filling of copper, aluminium, tin, gold or indium.
2. hybrid bonded method according to claim 1, it is characterised in that：The insulating layer of upper substrate after cleaning and clear
Hydrophilic active surface is formed on the insulating layer of lower substrate after washing.
3. hybrid bonded method according to claim 1, it is characterised in that：The concave width of metal is more than the gold
Belong to the width of projection.
4. hybrid bonded method according to claim 3, it is characterised in that：The concave width dimensions of metal are 30nm
~50um；The width dimensions of the metal protuberance are 10nm~45um.
5. according to any hybrid bonded method of Claims 1 to 4, it is characterised in that：The insulation on substrate up and down
Layer mixes up silica medium for silicon dioxide insulating layer, silicon nitride dielectric layer, oxide-nitride layer, carborundum insulating layer or carbon
Layer.
6. hybrid bonded method according to claim 5, it is characterised in that：In the step 5, pressure applied 1
~50 thousand newton.
7. hybrid bonded method according to claim 5, it is characterised in that：In the step 6, annealing region is
200~450 DEG C, when annealing time is small more than 0.15.
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| CN201510354733.XA CN105185719B (en) | 2015-06-24 | 2015-06-24 | A kind of hybrid bonded method of bayonet type |
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| CN201510354733.XA CN105185719B (en) | 2015-06-24 | 2015-06-24 | A kind of hybrid bonded method of bayonet type |
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| CN105575953B (en) * | 2015-12-31 | 2018-06-29 | 上海华虹宏力半导体制造有限公司 | Connecting component of sports apparatus and forming method thereof and sports apparatus |
| US10340249B1 (en) | 2018-06-25 | 2019-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
| CN110429038A (en) * | 2019-08-09 | 2019-11-08 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof |
| CN110896025A (en) * | 2019-10-28 | 2020-03-20 | 芯盟科技有限公司 | Wafer bonding method and wafer after bonding |
| US12119315B2 (en) | 2021-07-09 | 2024-10-15 | Changxin Memory Technologies, Inc. | Chip bonding method and semiconductor chip structure |
| CN113690217A (en) * | 2021-09-16 | 2021-11-23 | 苏州通富超威半导体有限公司 | Semiconductor assembly |
| CN116525475B (en) * | 2023-07-05 | 2024-04-02 | 湖北芯研投资合伙企业(有限合伙) | Wafer-level hybrid bonding method based on pre-positioning self-compensating alignment |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |