CN104966693A - Three-dimensional integrated power system of embedded composite heat dissipating structure and preparation method thereof - Google Patents

Abstract

The invention discloses a three-dimensional integrated power system and a preparation method of an embedded composite heat dissipation structure. (2) The upper part is the low-voltage device and sensor device layer (3). The preparation method includes: step 1, making the low-voltage device and sensor device layer (3); step 2, making the high-voltage and high-power device layer and embedding the heat dissipation channel Hole making; step 3, stacking the high-voltage and high-power device layer (2) chip layer; step 4, after stacking the high-voltage and high-power device layer (2) on the heat sink (1), the low-voltage device and sensor device layer (3) Stacked on the high-voltage and high-power device layer (2) to form a three-dimensional integrated power system with an embedded composite heat dissipation structure, etc., the invention solves the heat dissipation problem of the three-dimensional integrated power system, so it has the advantages of high integration and larger power capacity .

Description

A three-dimensional integrated power system with an embedded composite heat dissipation structure and its preparation method

technical field

The invention belongs to the heat dissipation technology of a three-dimensional integrated power system, in particular to a three-dimensional integrated power system with an embedded composite heat dissipation structure and a preparation method.

Background technique

With the continuous improvement of power electronics technology's requirements for power system integration, intelligence, and reliability, for a very highly integrated power system on a chip (Power System on a Chip, referred to as PSoC), that is, the sensor device and the control circuit , signal processing circuit, interface circuit, power device, etc. are integrated on the same chip, so that it has the intelligent function of precisely adjusting the output according to the load requirements and self-protecting according to overheating, overvoltage, overcurrent, etc. Its superiority is self-evident And metaphor. The key to realizing a single-chip intelligent power integration system is the intelligent power integration technology based on high and low voltage compatibility, high and low voltage interconnection, and high and low voltage isolation processes. At present, for silicon-based smart power devices, the mature BCD (Bipolar, CMOS, DMOS) process has basically solved the problem of high and low voltage process compatibility, but the high and low voltage isolation structure in the BCD process limits the high power capacity of the power system. and development on high power density. Moreover, the integration technology of power systems based on new semiconductor materials (such as SiC, GaN, etc.) is difficult and the process cost is high. Since G. Moore, the founder of Intel, published Moore's Law in 1965, the scale of integrated circuits has basically followed this law. It is predicted that by 2016, 22nm integrated circuits will be mass-produced, and the feature size of transistors will be close to the nanoscale. It can be seen from physical knowledge that quantum effects will play a role at such a size level, and the current problems related to quantum effects have not been solved; and after the size of the integration process is reduced to the deep submicron level, the performance of the integrated circuit is dominated by the device. The dominant position has changed to the dominance of interconnect lines; with the advent of the multimedia network era, people's pursuit of large-capacity, multi-functional, high-performance electronic products, a series of problems such as signal delay and power consumption caused by traditional integration technology are increasingly protrude. Three-dimensional integration technology is recognized as the development direction of future integration technology, and it is a strong guarantee that Moore's Law will continue to be effective. Three-dimensional integration is a system-level architecture method, which uses stacking transistors or chips or modules in the vertical direction, so that more devices can be integrated on a chip per unit area, and the biggest advantage of 3D integration is that it can achieve highly heterogeneous multiple Functional system, that is, devices with different functions, different materials or different processes can be fabricated on different chip layers and then stacked to form a performance-optimized system. However, since the three-dimensional chip has a higher device density per unit area than the traditional two-dimensional chip, and has a higher interconnection density, the multi-layer stack of active devices makes the power consumption density rise rapidly; The low thermal conductivity of the dielectric layer becomes the bottleneck of the internal heat dissipation channel of the three-dimensional chip. Moreover, the power loss of high-power transistors under high-voltage and high-current working conditions in the power system is more prominent. The power consumption of power transistors will be converted into heat to heat up the tube core and increase the junction temperature. If the heat cannot be promptly and effectively dissipated If it is released, it will affect the performance of the device, thereby reducing the reliability of the system and even damaging the device.

Contents of the invention

The technical problem to be solved by the present invention is to provide a three-dimensional integrated power system and a preparation method of an embedded composite heat dissipation structure to solve the problem that the existing three-dimensional chip has a higher device density per unit area than the traditional two-dimensional chip, and has Higher interconnection density, multi-layer stacking of active devices makes the power consumption density rise rapidly; and because the thermal conductivity of the dielectric layer between the stacked layers is very low, it becomes the bottleneck of the internal heat dissipation channel of the three-dimensional chip. The power loss of high-power transistors under high-voltage and high-current working conditions is more prominent. The power consumption of power transistors will be converted into heat to heat up the tube core and increase the junction temperature. If the heat cannot be released in a timely and effective manner, it will It affects the working performance of the device, thereby reducing the reliability of the system work, and even damaging the device.

Technical scheme of the present invention:

A three-dimensional integrated power system with an embedded composite heat dissipation structure, which includes a heat sink, a high-voltage high-power device layer above the heat sink, and a low-voltage device and sensor device layer above the high-voltage high-power device layer.

The high-voltage high-power device layer and the low-voltage device and sensor device layer all include one or more than one chip layer, and each chip layer of the high-voltage high-power device layer and the low-voltage device and sensor device layer is connected by a through-silicon via. .

The periphery of each power unit on each chip layer of the high-voltage and high-power device layer is evenly provided with heat dissipation through holes, and metal materials are poured into the heat dissipation through holes as filling materials. .

The size and shape of the heat dissipation vias and power units corresponding to each chip layer of the high-voltage and high-power device layer are consistent.

The preparation method of the three-dimensional integrated power system of the embedded composite heat dissipation structure comprises the following steps:

Step 1. Integrate the low-voltage devices and sensor devices in the control circuit, protection circuit and detection circuit in the power system on one or more chip layers, and overlap the chip layers to form a low-voltage device and sensor device layer;

Step 2. Integrate the high-voltage and high-power devices in the power system on one or more chip layers, and reserve drilling positions around the power unit of each chip layer;

Step 3. Use plasma etching method to drill through holes at the reserved drilling positions on the periphery of each power unit, use low temperature chemical vapor deposition method to form an insulating dielectric layer in the through holes, and then use sputtering process to form in the through holes The barrier layer, and finally the metal core of the through hole is completely filled by electroplating to form an embedded heat dissipation through hole;

Step 4. Polish the upper and lower surfaces of the high-voltage, high-power chip layer embedded in the heat dissipation vias with a chemical and physical polishing process, and expose and smooth the upper and lower metal connection surfaces embedded in the heat dissipation vias. Finally, use low-temperature bonding technology to Each high-voltage and high-power chip layer is stacked in the vertical direction to form a high-voltage and high-power device layer;

Step 5. After stacking the high-voltage and high-power device layers on the heat sink, stack the low-voltage device and sensor device layers on the high-voltage and high-power device layer to form a three-dimensional integrated power system with an embedded composite heat dissipation structure.

Beneficial effects of the present invention:

The technical solution of the present invention does not need to consider the problem of process compatibility between the low-voltage device and the high-voltage power device in the power system. The low-voltage device and the high-voltage power device are separated and integrated on different chip layers, so that the integration degree of the system is higher and the power capacity is higher. Large; by embedding heat dissipation through holes inside the chip layer of the high-voltage device, the heat converted by the power consumption of the high-voltage device can be quickly diffused to the heat sink, realizing rapid heat dissipation, and improving the stability and reliability of the system; the present invention solves the problem of existing Technology Since the three-dimensional chip has a higher device density per unit area than the traditional two-dimensional chip, and has a higher interconnection density, the multi-layer stack of active devices makes the power consumption density rise rapidly; The low thermal conductivity of the dielectric layer has become the bottleneck of the heat dissipation channel inside the three-dimensional chip. The power loss of the high-power transistor under the high-voltage and high-current working conditions in the power system is more prominent, and the power consumption of the power transistor will be converted into heat to make the die If the heat cannot be released in a timely and effective manner, it will affect the performance of the device, thereby reducing the reliability of the system, and even damage the device.

Description of drawings:

Fig. 1 is a structural representation of the present invention;

Fig. 2 is a schematic cross-sectional view of the layer structure of the high-voltage high-power device of the present invention;

Fig. 3 is a schematic top view of the high-voltage high-power device layer of the present invention.

Detailed ways:

A three-dimensional integrated power system with an embedded composite heat dissipation structure (see Figure 1), which includes a heat sink 1, a high-voltage high-power device layer 2 above the heat sink 1, and a low-voltage device and sensor device above the high-voltage high-power device layer 2 Layer 3.

The high-voltage high-power device layer 2 and the low-voltage device and sensor device layer 3 all include one or more than one chip layer, and each chip layer of the high-voltage high-power device layer 2 and the low-voltage device and sensor device layer 3 is penetrated TSV connection. The present invention no longer considers the problem of high-voltage and low-voltage compatibility in the conventional silicon-based BCD process, but the high-voltage power devices, low-voltage devices and sensor devices in the power system are separately manufactured on different chip layers, and then completed by penetrating silicon vias The connection between layers shortens the interconnection wiring and optimizes the system performance.

The periphery of each power unit 5 on each chip layer of the high-voltage and high-power device layer 2 is evenly provided with heat dissipation vias 4, since the area occupied by the high-voltage and high-current device in the planar chip will be as high as 2/3 of the entire chip area, in order to To improve the integration degree and power capacity of the chip, the present invention distributes high-voltage and high-current devices on multiple chip layers, and embeds heat dissipation through holes in each chip layer where the power device is located to reduce the thermal resistance of the heat diffusion path, so that the power device The heat generated by dissipating power spreads more quickly to the bottom of the 3D chip.

Metal materials are poured into the heat dissipation vias 4 as filling materials, and the metal materials are metal materials with high thermal conductivity. The heat dissipation vias are inserted into each chip layer of the high-voltage and high-power device layer, and the filling materials of the heat dissipation vias are selected from high thermal conductivity. metal to reduce the thermal resistance of the heat dissipation channel.

In the power system, the power transistor formed by parallel connection of a large number of power device cells 7 can be divided into many power units, and the number of cells contained in each power unit may be different, depending on the temperature field of the chip layer. The power unit at the lower position contains more cells, and the power unit at the higher temperature position has fewer cells; then a plurality of heat dissipation through holes are evenly inserted around the periphery of each power unit, and the periphery of each power unit The number of heat dissipation vias is determined by the maximum power dissipation of the power unit. In short, try to ensure that the temperature on the chip layer of the power device embedded with the composite heat dissipation technology is basically the same. In order to facilitate stacking, the size and shape of the power unit and the heat dissipation via at the corresponding position of each chip in the power device layer are the same. The top view of the power device layer structure after embedding the composite heat dissipation technology is shown in Figure 3.

The preparation method of the three-dimensional integrated power system of the embedded composite heat dissipation structure comprises the following steps:

Step 1. Integrate the low-voltage devices and sensor devices in the control circuit, protection circuit and detection circuit in the power system on one or more chip layers, and overlap the chip layers to form a low-voltage device and sensor device layer 3;

Step 2. Integrate the high-voltage and high-power devices in the power system on one or more chip layers, and reserve drilling positions around the power unit of each chip layer;

Step 3. Use plasma etching method to drill through holes at the reserved drilling positions on the periphery of each power unit, use low temperature chemical vapor deposition method to generate insulating dielectric layer 6 in the through holes, and then use sputtering process to form the through holes in the through holes. Form a barrier layer, and finally fill the through-hole metal core completely by electroplating to form an embedded heat dissipation through-hole;

Step 4. Polish the upper and lower surfaces of the high-voltage and high-power chip layer forming the embedded heat dissipation vias with a chemical and physical polishing process, expose and smooth the upper and lower metal connection surfaces of the heat dissipation vias, and finally adopt low-temperature bonding technology Stack each chip layer of high voltage and high power in the vertical direction to form a high voltage and high power device layer 2;

Step 5. After stacking the high-voltage and high-power device layer 2 on the heat sink 1, stack the low-voltage device and sensor device layer 3 on the high-voltage and high-power device layer 2 to form a three-dimensional integrated power system with an embedded composite heat dissipation structure.

The number of heat dissipation vias, the ratio of width to depth, and the thermal conductivity of the internal filling metal determine the thermal resistance of the heat dissipation channel. Since the heat dissipation via holes are formed in the blank space of the chip layer, the process of manufacturing the heat dissipation via holes adopts a low-temperature process. The distance between the heat dissipation via and the power unit is determined by the thermal stress caused by the mismatch of the thermal expansion coefficients of the materials in the heat dissipation via.

Claims (5)

1. A three-dimensional integrated power system with an embedded composite heat dissipation structure, which includes a heat sink (1), characterized in that: above the heat sink (1) is a high-voltage high-power device layer (2), and a high-voltage high-power device layer ( 2) The upper part is the low-voltage device and sensor device layer (3). 2. A three-dimensional integrated power system with an embedded composite heat dissipation structure according to claim 1, characterized in that: the high-voltage high-power device layer (2) and the low-voltage device and sensor device layer (3) each include a Or more than one chip layer, each chip layer of the high-voltage high-power device layer (2) and the low-voltage device and sensor device layer (3) is connected through a through-silicon hole. 3. A three-dimensional integrated power system with an embedded composite heat dissipation structure according to claim 1, characterized in that: the periphery of each power unit on each chip layer of the high-voltage and high-power device layer (2) is uniformly arranged The heat dissipation through hole (4), the heat dissipation through hole (4) is poured with a metal material as a filling material. 4. A three-dimensional integrated power system with an embedded composite heat dissipation structure according to claim 1, characterized in that: the heat dissipation vias (4) at the corresponding positions of each chip layer of the high-voltage and high-power device layer (2), The size and shape of the power unit (5) are consistent. 5. The preparation method of the three-dimensional integrated power system of the embedded composite cooling structure as claimed in claim 1-4, it may further comprise the steps: Step 1. Integrate the low-voltage devices and sensor devices in the control circuit, protection circuit and detection circuit in the power system on one or more chip layers, and overlap the chip layers to form a low-voltage device and sensor device layer (3); Step 2. Integrate the high-voltage and high-power devices in the power system on one or more chip layers, and reserve drilling positions around the power unit of each chip layer; Step 3. Use plasma etching method to drill through holes at the reserved drilling positions on the periphery of each power unit, use low temperature chemical vapor deposition method to form an insulating dielectric layer in the through holes, and then use sputtering process to form in the through holes The barrier layer, and finally the metal core of the through hole is completely filled by electroplating to form an embedded heat dissipation through hole; Step 4. Polish the upper and lower surfaces of the high-voltage, high-power chip layer embedded in the heat dissipation vias with a chemical and physical polishing process, and expose and smooth the upper and lower metal connection surfaces embedded in the heat dissipation vias. Finally, use low-temperature bonding technology to Each high-voltage and high-power chip layer is stacked vertically to form a high-voltage and high-power device layer (2); Step 5. After stacking the high-voltage and high-power device layer (2) on the heat sink (1), stack the low-voltage device and sensor device layer (3) on the high-voltage and high-power device layer (2) to form an embedded composite heat dissipation Structured 3D integrated power systems.