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CN111554646B - Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method - Google Patents

Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method Download PDF

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Publication number
CN111554646B
CN111554646B CN202010425044.4A CN202010425044A CN111554646B CN 111554646 B CN111554646 B CN 111554646B CN 202010425044 A CN202010425044 A CN 202010425044A CN 111554646 B CN111554646 B CN 111554646B
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wafer
chip
layer
silicon
chip structure
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CN111554646A (en
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严阳阳
曹立强
戴风伟
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National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
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National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
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    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract

The invention discloses a wafer-level chip structure, a multi-chip stacking interconnection structure and a preparation method, wherein the wafer-level chip structure comprises the following components: the through silicon via is positioned at a preset distance from the first surface to the second surface of the wafer; the first surface of the wafer includes: the device comprises an active region, a plurality of layers of redistribution layers and bumps; the second surface of the wafer comprises: the number of concave structures of the concave insulating medium layer is consistent with that of the silicon through holes, the bottom of the concave insulating medium layer is isolated by the bottom of the silicon through holes, and the concave insulating medium layer is filled in the convex insulating medium layer and is electrically connected with the silicon through holes. The embodiment provided by the application is insensitive to the depth uniformity in the TSV blind hole etching piece, and the influence of ultrahigh selection ratio Si/SiOx dry etching, copper atom diffusion and the like on an active region in the prior art is avoided.

Description

Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a wafer-level chip structure, a multi-chip stacking interconnection structure and a preparation method.
Background
The key process steps of manufacturing the Through Silicon Via (TSV) are TSV back exposure, and the exposure for the TSV back in the prior art is two types: firstly, stopping the thinning and polishing process until the bottom of the TSV is not exposed, and then performing dry etching back etching to enable the TSV to protrude, deposit SiOx/SiNx at a low temperature, polish a wafer and the like to enable the back of the TSV to expose; in the second category, the TSV back copper is completely exposed through a thinning and polishing process, and then the TSV back exposure is realized through protrusion of the TSV, low-temperature SiOx/SiNx deposition, wafer polishing and the like through dry etching and back etching. The difficulty with the 1 st approach is: the lack of a stop layer through the polish thinning may result in copper exposure at the bottom of the TSV, resulting in a solution failure. In addition, in the back etching process, considering that the thickness of SiOx at the bottom of the TSV is only 100-200nm, the back etching depth of the Si substrate can reach 2-5um, the etching selection ratio of Si/SiOx in the back etching process is up to 20: 1-50: 1, and the process difficulty is high; with regard to option 2, during the course of thinning and polishing until the copper on the back of the TSV is exposed, copper atoms may contaminate the active region of the wafer without a barrier layer, and impurity levels are introduced into the wafer substrate to cause the transistor to fail, and although this risk can be reduced by the subsequent etching back process, it cannot be eliminated.
Disclosure of Invention
Therefore, the invention provides a wafer-level chip structure, a multi-chip stacking interconnection structure and a preparation method thereof, which overcome the defects of high process difficulty or pollution of copper atom diffusion and the like on an active area caused by Si/SiOx dry etching with an ultrahigh selection ratio in the prior art.
In a first aspect, the present invention provides a wafer level chip structure, including: the through silicon via is positioned at a preset distance from the first surface to the second surface of the wafer;
the first surface of the wafer comprises: the device comprises an active region, a plurality of layers of redistribution layers and bumps; the second surface of the wafer comprises: the number of concave structures of the concave insulating medium layer is consistent with that of the silicon through holes, the bottom of the concave insulating medium layer is isolated by the bottom of the silicon through holes, and the concave insulating medium layer is filled in the convex insulating medium layer and is electrically connected with the silicon through holes.
In an embodiment, the wafer-level chip structure further includes: and the photoresist layer is positioned between the concave insulating medium layer and the silicon through hole in the concave insulating medium layer, and the thickness of the photoresist layer is consistent with the length of the silicon through hole in the concave insulating medium layer.
In a second aspect, an embodiment of the present invention provides a wafer-level multi-chip stacking interconnection structure, including: a chip bonding body, a substrate and a leading-out terminal, wherein the chip bonding body is connected with the first surface of the substrate in a switching way, the leading-out terminal is formed on the second surface of the substrate, wherein,
chip bonding body, including piling up a plurality of monomer wafer level chips that set up, a plurality of monomer wafer level chips are direct to be connected through the bonding layer, monomer wafer level chip includes: a first chip structure and at least one second chip structure, the at least one second chip structure being located at the proximal end of the substrate, the first chip structure being located at the distal end of the substrate; the second chip structure is the wafer-level chip structure of the first aspect.
In one embodiment, the first chip structure includes: a through-silicon via connection structure that does not extend completely through a wafer, the first surface comprising: the second surface is a wafer surface.
In one embodiment, the first surfaces of the first chip structure and the second chip structure each include: the non-conductive adhesive film layer wraps the salient points, and the thickness of the non-conductive adhesive film layer is larger than the height of the salient points;
the bonding layer includes: the bump connection between the single wafer level chips and the non-conductive adhesive film layer wrapping the bump connection.
In one embodiment, the structure further comprises: and the plastic packaging layer is used for coating the chip bonding body based on a substrate level.
In a third aspect, an embodiment of the present invention provides a method for manufacturing a wafer-level chip structure, including the following steps:
sequentially preparing an active region, a silicon through hole, a plurality of layers of redistribution layers and salient points on a first surface of a wafer to form a first chip structure;
etching a concave groove on the second surface of the wafer relative to the through silicon vias on the basis of the first chip structure until all the through silicon vias are exposed;
depositing an insulating medium layer on the second surface of the wafer to form a concave insulating medium layer;
spin-coating positive photosensitive photoresist at the bottom of the concave groove insulating medium layer to form a photoresist layer, and exposing the bottom of the silicon through hole in the concave insulating medium layer by regulating the thickness of the photoresist layer in an underexposure mode;
removing the insulating medium layer at the bottom of the through silicon via by reactive ion etching to expose the metal layer at the bottom of the through silicon via;
and sequentially preparing a barrier layer, a seed layer and an under bump metallization layer on the second surface of the wafer to form the wafer-level chip structure.
In a fourth aspect, an embodiment of the present invention provides a method for manufacturing a wafer-level multi-chip stacked interconnection structure, including the following steps:
sequentially preparing an active region, a silicon through hole, a plurality of layers of redistribution layers and salient points on a first surface of a wafer to form a first chip structure;
according to the method for manufacturing the wafer-level chip structure in the third aspect, a second chip structure is formed;
preparing a plastic packaging layer, and carrying out plastic packaging on at least one second chip structure and another first chip structure which are sequentially stacked;
processing the second surface of the first chip structure positioned at the bottom to form a second chip structure, and attaching the second chip structure to the first surface of the substrate;
and preparing a leading-out terminal on the second surface of the substrate to form a wafer-level multi-chip stacking interconnection structure.
In an embodiment, when the first chip structure and the second chip structure are manufactured, after the steps of sequentially manufacturing the active region, the through silicon via, the multiple redistribution layers, and the bump on the first surface of the wafer, the method further includes: preparing a non-conductive adhesive film layer to coat the salient points, wherein the thickness of the non-conductive adhesive film layer is larger than the height of the salient points.
In an embodiment, after the step of preparing the lead-out terminal on the second surface of the substrate, the method further includes: and cutting the wafer-level multi-chip stacking interconnection structure to form a single wafer-level chip structure.
1. The wafer-level chip structure and the preparation method provided by the invention are insensitive to the depth uniformity in the TSV blind hole etching sheet; the influence of ultrahigh selection ratio Si/SiOx dry etching, copper atom diffusion and the like on the active region in the prior art is avoided.
2. According to the wafer-level multi-chip stacking interconnection structure and the preparation method thereof, the multiple chip structures are insensitive to the depth uniformity in the TSV blind hole etching sheet, so that the influence of ultrahigh selection ratio Si/SiOx dry etching, copper atom diffusion and the like on an active region in the prior art is avoided; the bonding layer introduces the non-conductive adhesive film layer, so that the problem of bridging among different salient points of the single wafer level chip during stacking and bonding can be solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a diagram illustrating an exemplary wafer level chip architecture according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another embodiment of a wafer level chip architecture according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating a specific example of a method for fabricating a wafer-level chip structure according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of sequentially manufacturing an active region, a through silicon via, a plurality of redistribution layers, and a bump on a first surface of a wafer according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram illustrating an etching process of a concave groove on a second surface of a wafer corresponding to a through-silicon via according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a concave insulating dielectric layer according to an embodiment of the present invention;
fig. 7 is a schematic diagram illustrating that the bottom of the through-silicon via in the concave insulating dielectric layer is exposed by adjusting the thickness of the photoresist layer in an underexposure manner according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of removing the insulating dielectric layer at the bottom of the through-silicon via by reactive ion etching to expose the metal layer at the bottom of the through-silicon via according to the embodiment of the present invention;
FIG. 9 is a schematic diagram of a wafer level multi-chip stack interconnect structure according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram illustrating a non-conductive adhesive film layer formed on a first surface of a second chip structure according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a bonding layer provided by an embodiment of the invention;
fig. 12 is a schematic view of a molding layer according to an embodiment of the present invention;
FIG. 13 is a flowchart illustrating an exemplary method for fabricating a wafer-level multi-chip stacked interconnect structure according to embodiments of the present invention;
FIG. 14 is a flow chart of another specific example of a method for fabricating a wafer-level multi-chip stack interconnect structure according to an embodiment of the present invention;
fig. 15 is a flowchart illustrating another exemplary method for fabricating a wafer-level multi-chip stacked interconnect structure according to embodiments of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
An embodiment of the present invention provides a wafer level chip structure, as shown in fig. 1, including: the through silicon via is located at a preset distance from the first surface to the second surface of the wafer; the first surface of the wafer comprises: an active region 2, a multilayer redistribution layer 3 and bumps 4; the second surface of the wafer comprises: the number of the concave structures of the concave insulating medium layer 6 is consistent with that of the silicon through holes 1, the bottom of the concave insulating medium layer is isolated by the bottom of the silicon through holes, and the concave insulating medium layer is filled in the convex insulating medium layer and is electrically connected with the silicon through holes. In the embodiment of the invention, the material filled in the through silicon via 1 can be copper, the salient point 4 can be a solder ball, the material of the under-salient point metallization layer can be copper, and the height of the under-salient point metallization layer can be higher than that of the concave insulating medium layer, so that the signal connection with other chips is facilitated.
In an embodiment, as shown in fig. 2, the wafer level chip structure further includes: and the photoresist layer 7 is positioned between the concave insulating medium layer and the through silicon via in the concave insulating medium layer, and the thickness of the photoresist layer is consistent with the length of the through silicon via in the concave insulating medium layer. The photoresist layer of the embodiment of the invention is a positive photosensitive Polyimide photoresist, which can be a photosensitive polymer, such as photosensitive Polyimide (PI), Benzocyclobutene (BCB), PBO, and the like. In practical application, whether the structure has the photoresist layer or not mainly depends on the length of the through silicon via in the concave insulating medium layer, and when the bottom of the through silicon via is just level with the bottom of the concave insulating medium layer, the photoresist layer does not exist.
An embodiment of the present invention further provides a method for manufacturing the wafer-level chip structure, as shown in fig. 3, the method includes:
step 11, preparing an active area, a silicon through hole, a multilayer redistribution layer and a bump on a first surface of a wafer in sequence; the preparation process of this step is the existing mature preparation technology, which is not limited herein, and the formed structure is shown in fig. 4.
Step 12, etching a concave groove on the second surface of the wafer relative to the through silicon vias until all the through silicon vias are exposed; the preparation process of this step is to sequentially perform photolithography (preparation of an etching mask), dry etching, and the like on the back surface of the wafer until the TSV is exposed, and the formed structure is as shown in fig. 5.
Step 13, depositing an insulating medium layer on the second surface of the wafer to form a concave insulating medium layer; in the step, a SiOx insulating medium layer is deposited on the back of the wafer by adopting a low-temperature process, and the formed structure is shown in figure 6.
Step 14, spin-coating positive photosensitive photoresist on the bottom of the concave groove insulating medium layer to form a photoresist layer, and exposing the bottom of the silicon through hole in the concave insulating medium layer by regulating the thickness of the photoresist layer in an underexposure mode; in the step, JSR5100 (a positive photosensitive Polyimide photoresist which is Polyimide, PI) is coated on the back surface of the wafer in a spin coating mode, the Polyimide is completely cured, the PI is adopted, the bottom of the TSV with the lowest depth is exposed by regulating and controlling the thickness of the residual PI in an underexposure mode, and the formed structure is shown in figure 7.
And step 15, removing the insulating medium layer at the bottom of the through silicon via through reactive ion etching to expose the metal layer at the bottom of the through silicon via. By the reactive ion etching process, the SiOx insulating medium layer at the bottom of the TSV is removed, the metal layer at the bottom of the TSV is exposed, and the formed structure is shown in FIG. 8.
And step 16, preparing a barrier layer, a seed layer and an under bump metallization layer on the second surface of the wafer in sequence to form the wafer-level chip structure, as shown in fig. 2. The method comprises the steps of sequentially finishing Barrier/seed layer deposition on the back of a wafer, preparing a UBM electroplating mask by utilizing a photoetching process, realizing UBM electroplating preparation, removing the electroplating mask layer by utilizing wet photoresist removal, and sequentially removing the seed layer/Barrier layer by utilizing wet corrosion. Finally, an ENIG surface treatment is performed on the UBM surface. After ENIG surface treatment, Ni (the thickness is generally 2-3um) and Au (the thickness is generally 50nm) are sequentially deposited on UBM copper, and the Ni layer is used for preventing the problem of reliability failure caused by the fact that metal copper and metal tin of a copper wire or a copper bonding pad are alloyed when a solder ball reflows.
The wafer-level chip structure and the preparation method provided by the embodiment of the invention are insensitive to the depth uniformity in the TSV blind hole etching chip, and avoid the influence of ultrahigh selection ratio Si/SiOx dry etching, copper atom diffusion and the like on an active region in the prior art.
Example 2
An embodiment of the present invention provides a wafer-level multi-chip stacking interconnection structure, as shown in fig. 9, including: a chip bonding body 8, a substrate 9 and a leading-out terminal 10, wherein the chip bonding body 8 is connected with a first surface of the substrate 9 in a switching way, the leading-out terminal 10 is formed on a second surface of the substrate, wherein,
chip bonding body 8, including piling up a plurality of monomer wafer level chips that set up, a plurality of monomer wafer level chips are direct to be connected through the bonding layer, monomer wafer level chip includes: a first chip structure 11 and at least one second chip structure 12, the at least one second chip structure being located at the proximal end of the substrate and the first chip structure being located at the distal end of the substrate; the second chip structure is the wafer-level chip structure described in embodiment 1, and as shown in fig. 9, four second chip structures 12 are included as an example, which is not limited thereto.
In one embodiment, the first chip structure 11, as shown in fig. 3, includes: a through-silicon-via that does not extend completely through the wafer, the first surface comprising: the second surface is a wafer surface.
In one embodiment, the first surfaces of the first chip structure and the second chip structure each include: and the non-conductive adhesive film layer 101 wraps the salient points, and the thickness of the non-conductive adhesive film layer is larger than the height of the salient points. As shown in fig. 10, taking the second chip structure as an example, a Non-Conductive-Film (NCF) layer is formed on the first surface of the second chip structure.
As shown in fig. 11, the bonding layer 111 includes: the bump connection between the single wafer level chips and the non-conductive adhesive film layer wrapping the bump connection. The non-conductive adhesive film layer can be arranged to improve the bridging problem among different salient points when the single wafer level chips are stacked and bonded.
In one embodiment, as shown in fig. 12, the method further includes: and the plastic packaging layer 112 covers the chip bonding body on the basis of a substrate level. And the stacked multilayer chips are plastically packaged through the plastic packaging layer, so that the chips are protected.
Correspondingly, an embodiment of the present invention further provides a method for manufacturing the wafer-level multi-chip stacked interconnection structure, as shown in fig. 13, including:
step S21: an active region, a silicon through hole, a plurality of layers of redistribution layers and bumps are sequentially prepared on a first surface of a wafer to form a first chip structure.
Step S22: a second chip structure is formed according to the method of fabricating a wafer-level chip structure described in embodiment 1.
Step S23: and sequentially stacking at least one second chip structure and another first chip structure on the first surface of the first chip structure positioned at the bottom, wherein the chip structures are stacked based on bump connection bonding.
Step S24: and preparing a plastic package layer, and carrying out plastic package on the at least one second chip structure and the other first chip structure which are sequentially stacked.
Step S25: processing the second surface of the first chip structure positioned at the bottom to form a second chip structure, and attaching the second chip structure to the first surface of the substrate;
step S26: and preparing a leading-out terminal on the second surface of the substrate to form a wafer-level multi-chip stacking interconnection structure. The lead-out terminal in this embodiment may be a solder ball for leading out a signal of the interconnection structure.
In an embodiment, as shown in fig. 14, in preparing the first chip structure, after the steps of sequentially preparing the active region, the through silicon via, the multiple redistribution layers, and the bump on the first surface of the wafer, the method further includes: preparing a non-conductive adhesive film layer to coat the salient points, wherein the thickness of the non-conductive adhesive film layer is larger than the height of the salient points. After the step of forming the second chip structure, the method further comprises: preparing a non-conductive adhesive film layer to coat the salient points, wherein the thickness of the non-conductive adhesive film layer is larger than the height of the salient points. Each chip is heated and pressurized during bonding, so that after the non-conductive adhesive film layer is melted into liquid, the chips are electrically connected through the salient points, the bridging condition caused by metal splashing in the salient point bonding is prevented, and the bonding effect is better.
After the step of preparing the lead-out terminal on the second surface of the substrate, as shown in fig. 15, the method further includes:
step S27: and cutting the wafer-level multi-chip stacking interconnection structure to form a single wafer-level chip structure.
According to the wafer-level multi-chip stacking interconnection structure and the preparation method thereof, the multiple chip structures are insensitive to the depth uniformity in the TSV blind hole etching sheet, so that the influence of ultrahigh selection ratio Si/SiOx dry etching, copper atom diffusion and the like on an active region in the prior art is avoided; the bonding layer introduces the non-conductive adhesive film layer, so that the problem of bridging among different salient points of the single wafer level chip during stacking and bonding can be solved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims (9)

1. A wafer level chip structure, comprising:
the through silicon via extends to a preset distance from the first surface to the second surface of the wafer;
the first surface of the wafer comprises: the device comprises an active region, a plurality of layers of redistribution layers and bumps; the second surface of the wafer comprises: the number of concave structures of the concave insulating medium layer is consistent with that of the silicon through holes, the bottom of the concave insulating medium layer is isolated by the bottom of the silicon through holes, and the concave insulating medium layer is filled in the convex insulating medium layer and is electrically connected with the silicon through holes;
further comprising: the photoresist layer is positioned between the concave insulating medium layer and the silicon through hole in the concave insulating medium layer, and the thickness of the photoresist layer is consistent with the length of the silicon through hole in the concave insulating medium layer.
2. A wafer-level multi-chip stack interconnect structure, comprising: a chip bonding body, a substrate and a leading-out terminal, wherein the chip bonding body is connected with the first surface of the substrate in a switching way, the leading-out terminal is formed on the second surface of the substrate, wherein,
chip bonding body, including piling up a plurality of monomer wafer level chips that set up, a plurality of monomer wafer level chips are direct to be connected through the bonding layer, monomer wafer level chip includes: a first chip structure and at least one second chip structure, the at least one second chip structure being located at the proximal end of the substrate, the first chip structure being located at the distal end of the substrate;
the second chip structure is the chip structure of claim 1.
3. The wafer-level multi-chip stack interconnect structure of claim 2, wherein the first chip structure comprises: a through-silicon via connection structure that does not extend completely through a wafer, the first surface comprising: the second surface is a wafer surface.
4. The wafer-level multi-chip stack interconnect structure of claim 3,
the first surfaces of the first chip structure and the second chip structure respectively comprise: the non-conductive adhesive film layer wraps the salient points, and the thickness of the non-conductive adhesive film layer is larger than the height of the salient points;
the bonding layer includes: the bump connection between the single wafer level chips and the non-conductive adhesive film layer wrapping the bump connection.
5. The wafer-level multi-chip stack interconnect structure of any of claims 2-4, further comprising:
and the plastic packaging layer is used for coating the chip bonding body based on a substrate level.
6. A preparation method of a through silicon via structure is characterized by comprising the following steps:
sequentially preparing an active region, a silicon through hole, a plurality of layers of redistribution layers and salient points on a first surface of a wafer to form a first chip structure;
etching a concave groove on the second surface of the wafer relative to the through silicon vias on the basis of the first chip structure until all the through silicon vias are exposed;
depositing an insulating medium layer on the second surface of the wafer to form a concave insulating medium layer;
spin-coating positive photosensitive photoresist at the bottom of the concave groove insulating medium layer to form a photoresist layer, and exposing the bottom of the silicon through hole in the concave insulating medium layer by regulating the thickness of the photoresist layer in an underexposure mode;
removing the insulating medium layer at the bottom of the through silicon via by reactive ion etching to expose the metal layer at the bottom of the through silicon via;
and sequentially preparing a barrier layer, a seed layer and an under-bump metallization layer on the second surface of the wafer to form the silicon through hole structure, wherein the silicon through hole structure is internally provided with a photoresist layer, the photoresist layer is positioned between the concave insulating medium layer and the silicon through hole in the concave insulating medium layer, and the thickness of the photoresist layer is consistent with the length of the silicon through hole in the concave insulating medium layer.
7. A preparation method of a wafer-level multi-chip stacking interconnection structure is characterized by comprising the following steps:
sequentially preparing an active region, a silicon through hole, a plurality of layers of redistribution layers and salient points on a first surface of a wafer to form a first chip structure;
the method for manufacturing a through silicon via structure according to claim 6, forming a second chip structure;
sequentially stacking at least one second chip structure and another first chip structure on the first surface of the first chip structure positioned at the bottom, wherein the chip structures are connected, bonded and stacked on the basis of bumps;
preparing a plastic packaging layer, and carrying out plastic packaging on at least one second chip structure and another first chip structure which are sequentially stacked;
processing the second surface of the first chip structure positioned at the bottom to form a second chip structure, and attaching the second chip structure to the first surface of the substrate;
and preparing a leading-out terminal on the second surface of the substrate to form a wafer-level multi-chip stacking interconnection structure.
8. The method of claim 7, further comprising, after the steps of sequentially forming the active region, the through-silicon via, the plurality of redistribution layers, and the bump on the first surface of the wafer during the steps of forming the first chip structure and the second chip structure: preparing a non-conductive adhesive film layer to coat the salient points, wherein the thickness of the non-conductive adhesive film layer is larger than the height of the salient points.
9. The method of claim 8, further comprising, after the step of forming the terminal on the second surface of the substrate: and cutting the wafer-level multi-chip stacking interconnection structure to form a single wafer-level chip structure.
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