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CN103579152B - 焊盘上凸块（bop）接合结构 - Google Patents

焊盘上凸块（bop）接合结构 Download PDF

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Publication number
CN103579152B
CN103579152B CN201310136407.2A CN201310136407A CN103579152B CN 103579152 B CN103579152 B CN 103579152B CN 201310136407 A CN201310136407 A CN 201310136407A CN 103579152 B CN103579152 B CN 103579152B
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China
Prior art keywords
metal gasket
copper post
surface region
substrate
metal
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CN201310136407.2A
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CN103579152A (zh
Inventor
庄曜群
庄其达
郭正铮
陈承先
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明描述的实施方式提供了封装体和接合衬底之间接合结构的增大的重叠表面区域。通过使用封装体和/或接合结构上的伸长的接合结构并且通过使这些接合结构定向，接合结构设计成承受由热循环导致的接合应力以减少冷焊。本发明还公开了一种焊盘上凸块(BOP)接合结构。

Description

焊盘上凸块（BOP）接合结构
本申请要求2012年7月31日提交的名称为“Bump on Pad(BOP)BondingStructure”的申请号为61/677,873的美国专利临时申请的利益，所述申请通过引用全部并入本文中。
技术领域
本发明涉及半导体技术领域，更具体地，涉及一种焊盘上凸块(BOP)接合结构。
背景技术
半导体器件用于多种电子应用中，例如，个人电脑、手机、数码相机以及其他电子设备。半导体器件通常通过以下方式来制造：在半导体衬底上方顺序沉积绝缘层或者介电层、导电层以及半导体层的材料，并且使用光刻图案化各种材料层以在其上形成电路部件和元件。
半导体产业通过继续减小最小部件尺寸来持续提高各种电子部件(例如，晶体管、二极管、电阻器、电容器等等)的集成密度，这允许更多部件集成到给定区域内。在一些应用中，这些较小的电子部件也需要比传统的封装体使用更小面积或者更小高度的更小的封装体。
因此，已经开始研发新的封装技术。用于半导体器件的这些相对较新类型的封装技术面临制造挑战。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种封装结构，包括：
具有连接结构的管芯封装体，所述连接结构包括铜柱，其中所述铜柱具有第一表面区域；
衬底，具有填充金属垫上方的开口的焊料层，其中所述焊料层与所述金属垫直接接触，所述开口具有第二表面区域，所述金属垫具有第三表面区域，所述第一表面区域、所述第二表面区域以及所述第三表面区域中的至少之一具有伸长形状，其中所述第三表面区域宽于所述第二表面区域，并且所述焊料层与所述管芯封装体上的所述连接结构形成接合结构。
在可选实施例中，所述开口被焊料层包围，所述焊料层可通过光刻被图案化。
在可选实施例中，所述伸长形状的轴线基本指向所述管芯封装体的中心。
在可选实施例中，所述第一表面区域和所述第二表面区域均具有伸长形状，所述第一表面区域和所述第二表面区域的轴线基本重叠并且指向所述管芯封装体的中心。
在可选实施例中，所述伸长形状是跑道形状。
在可选实施例中，所述第三表面区域也是伸长的，并且所述第三表面区域的轴线基本与所述第一和第二表面区域的轴线重叠。
在可选实施例中，所述封装结构进一步包括另一接合结构，这两个接合结构之间的节距在大约30μm和大约200μm之间。
在可选实施例中，所述伸长形状的宽度在大约10μm和大约100μm之间。
在可选实施例中，所述衬底具有比所述管芯封装体高的热膨胀系数。
在可选实施例中，在所述金属垫和相邻金属垫之间存在至少一根布线金属线；所述至少一根布线金属线具有与所述伸长形状的轴线平行的轴线。
在可选实施例中，存在电连接至所述管芯封装体中的所述铜柱的金属垫，并且在该金属垫和相邻金属垫之间存在至少一根布线金属线，所述至少一根布线金属线具有与所述伸长形状的轴线平行的轴线。
根据本发明的另一方面，还提供了一种封装结构，包括：
通过第一接合结构接合至衬底的封装体，其中，所述第一接合结构包括：
接合至所述封装体中的第一金属垫的铜柱，所述封装体包括至少 一个半导体管芯，
形成在介电材料中的焊料填充开口，所述焊料填充开口形成在第二金属垫上方，所述焊料填充开口中的焊料层直接接触所述第二金属垫，所述铜柱的凸块、所述第一金属垫、所述焊料填充开口以及所述第二金属垫的轴线基本重叠并且所述铜柱的凸块、所述第一金属垫以及所述焊料填充开口中的至少一个的轴线是伸长的并且指向所述封装体的所述中心。
在可选实施例中，所述封装结构包括与所述第一接合结构相邻的第二接合结构，并且这两个相邻的接合结构的节距在大约30μm和大约200μm之间。
在可选实施例中，在与所述第一金属垫或者所述第二金属垫相同的水平上存在至少一根布线金属线，所述至少一根布线金属线位于这两个接合结构之间。
在可选实施例中，在所述铜柱和所述第一金属垫之间存在凸点下金属化(UBM)层。
在可选实施例中，所述衬底包括选自双马来酰亚胺三嗪树脂(BT)树脂、FR-4、FR-5、陶瓷、玻璃、塑料以及胶带的材料。
在可选实施例中，所述焊料填充开口由阻焊层围绕。
在可选实施例中，所述铜柱的所述凸块、所述第一金属垫、所述焊料填充开口以及所述第二金属垫都具有伸长形状。
在可选实施例中，所述伸长形状成形为跑道形状。
在可选实施例中，所述铜柱的所述凸块和所述焊料填充开口是伸长的。
附图说明
为更完整的理解实施例及其优点，现将结合附图所进行的以下描述作为参考，其中：
图1A是根据一些实施例的封装结构的立体图；
图1B示出根据一些实施例的在封装体和衬底接合在一起之前部分封装体和部分衬底的截面图；
图1C示出根据一些实施例的部分衬底的截面图；
图2A示出根据一些实施例的具有互连金属线的金属垫的俯视图；
图2B示出根据一些其他实施例的具有互连金属线的金属垫的俯视图；
图3A是根据一些实施例的在接合之前封装体和衬底的截面图；
图3B示出根据一些实施例的图3A的铜柱和阻焊开口的俯视图；
图3C是根据一些实施例的封装体和衬底后接合的截面图；
图3D是根据一些实施例的图3C的铜柱和阻焊开口的俯视图；
图4A是根据一些实施例的封装体和衬底后接合的截面图；
图4B示出根据一些实施例的图4A的铜柱和阻焊开口的俯视图；
图5A是根据一些实施例的封装体和衬底后接合的截面图；
图5B示出根据一些实施例的图5A的铜柱和阻焊开口的俯视图；
图6示例性示出根据一些实施例的封装体上的伸长铜柱；
图7A-图7F示出根据一些实施例的在接合之前，封装体的铜柱以及衬底的阻焊开口和金属垫的各种布置的俯视图；以及
图8示出根据一些实施例的封装体的铜柱和金属垫的俯视图。
除非另有说明，不同附图中的相应标号和符号通常指相应部件。将附图绘制成清楚地示出实施例的相关方面而不必须成比例绘制。
具体实施方式
下面，详细讨论本发明实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所讨论的具体实施例是示例性的，而不限制本发明的范围。
图1A是根据一些实施例的包括接合至衬底(或者接合衬底)120的封装体110的封装结构100的立体图，衬底120进一步接合至衬底130。封装体110至少包括半导体管芯(未示出)。半导体管芯包括如半导体集成电路制造中采用的半导体衬底，并且集成电路可形成在其中和/或其上。所述半导体衬底指包括半导体材料但不限于体硅，半导体晶圆，绝缘体上硅(SOI)衬底，或者硅锗衬底的任何结构。包括III族、IV族和V族元素的其他半导体材料也可使用。所述半导体衬底可进一步包括多个隔离部件(未 示出)，例如，浅沟槽隔离(STI)部件或者硅的局部氧化(LOCOS)部件。所述隔离部件可限定并且隔离各种微电子元件。可形成在半导体衬底中的各种微电子元件的实例包括晶体管(例如，金属氧化物场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管)、双极结型晶体管(BJT)、高压晶体管、高频晶体管，p-沟道和/或n-沟道场效应晶体管(PFET/NFET)；电阻器、二极管；电容器；电感器；熔丝；以及其他合适的元件。实施各种工艺(包括沉积、蚀刻、注入、光刻、退火和/或其他合适的工艺)以形成微电子元件。微电子元件被互连以形成集成电路器件，例如，逻辑器件、存储器件(例如，SRAM)、RF器件、输入/输出(I/O)器件、系统级芯片(SoC)器件、它们的组合，以及其他合适类型的器件。
根据一些实施例，衬底120包括半导体晶圆的一部分。衬底120可包括硅，砷化镓，绝缘体上硅(“SOI”)或者其他类似的材料。在一些实施例中，衬底120还包括无源器件(例如，电阻器、电容器、电感器等)或者有源器件(例如，晶体管)。在一些实施例中，衬底120包括附加的集成电路。衬底120可进一步包括衬底通孔(TSV)并且可以为中介层。根据一些实施例，衬底120可以为堆叠的管芯。在一些实施例中，衬底130包括双马来酰亚胺-三嗪(BT)树脂、FR-4(具有为阻燃剂的环氧树脂粘合剂的玻璃纤维编织物构成的复合材料)、陶瓷、玻璃、塑料、胶带、薄膜或者可带有需要接收导电端子的导电垫或者导电盘的其他支撑材料。
衬底130可由用于制造衬底120的材料制造。在一些实施例中，衬底130是多层电路板。封装体110通过连接件115接合至衬底120，并且衬底120通过连接件125接合至衬底130。
图1B示出根据一些实施例的部分封装体110的截面图，图1C示出根据一些实施例的在它们接合在一起之前接合结构附近的部分衬底120的截面图。图1B示出封装体110包括具有器件的衬底102，器件具有形成在其内的互连件(未示出)。如上所述，尽管它可包括其他半导体材料，衬底102可包括诸如硅衬底的半导体衬底。互连结构104包括形成在其内并且连接至半导体器件的金属线和通孔106并且互连结构104形成在衬底102上。金属线和通孔106可由铜或者铜合金形成，并且可使用双镶嵌工艺形 成。互连结构104可包括常见的层间电介质(ILD，未示出)以及金属间电介质(IMD)108。IMD108可包括低k介电材料，并且可具有低于大约3.0的介电常数。低k介电材料还可以为具有低于大约2.5的k值的极低k介电材料。
封装体110包括凸点下金属化(UBM)层111以及UBM层111上的铜柱112。在整个说明书中，铜柱112还称为含铜凸块或者金属凸块。尽管铜柱112在此处和下面的说明书中用作实例，其他类型的金属凸块(例如，焊锡块)也可代替铜柱112。根据一些实施例，焊料层113形成在铜柱112上方。在一些实施例中，焊料层不形成在铜柱112上方。在一些实施例中，金属势垒层(未示出)形成在铜柱112和焊料层113之间以阻止通过混合焊料和铜形成的金属间复合物(IMC)的形成。在一些实施例中，势垒层由Ti制造。UBM层111设置在金属垫105上，金属垫105连接至封装体110中的互连结构。在互连结构104和不接触金属垫105的UBM层111之间，存在钝化层107。在一些实施例中，钝化层107由聚酰亚胺制造。在一些实施例中，钝化层107包括多于一个的子层。金属垫105可通过金属线连接至相同金属层上的输入/输出结构或者其他导电结构。在一些实施例中，金属垫105包括铜并且可以为纯铜或者铜合金。在一些可选的实施例中，可使用其他导电材料以替代铜。例如，金属垫105可包括铝、铝合金、金或者金合金等。
在一些实施例中，UBM层111包括扩散势垒层和种子层。扩散势垒层可由氮化钽形成，然而它也可由其他材料(例如，氮化钛、钽、钛等)形成。种子层可为形成在扩散势垒层上的铜种层。铜种层可由铜或者含有银、铬、镍、锡、金以及它们的组合的铜合金之一形成。在一些实施例中，UBM层111包括由Ti形成的扩散势垒层和由Cu形成的种子层。
根据一些实施例，图1C示出包括基衬底150的衬底120。衬底120包括连接在衬底120的相对侧上的金属部件的金属线和通孔(未示出)。衬底120的通孔可包括填充导电金属的镀通孔(PTH)。衬底120还包括金属垫210，其被钝化层207部分覆盖。在一些实施例中，钝化层207为可通过光刻图案化的阻焊层(没有另外的光刻胶层)。金属垫210可以通过 金属线和通孔(未示出)电连接至在衬底120的底侧上的球栅阵列(BGA)球(未示出)。金属线和通孔形成在介电层中，介电层可形成在半导体层上方。
金属垫210形成在顶部介电层上方。金属垫210可由基本纯铜、铝铜，或者其他金属材料(例如，钨、镍、钯、金和/或它们的合金)形成。金属垫210被钝化层207部分覆盖。焊料层220形成在金属垫210上方以填充形成在钝化层207中的开口以实现后续与封装体110的焊料层113或者铜柱112(如果没有焊料层113)接合。在一些实施例中，形成在钝化层207中的开口称为阻焊开口(SRO)117。金属垫210可通过金属线连接至相同金属层上的输入/输出结构或者其他导电结构。在一些实施例中，金属垫210包括铜并且可以为纯铜或者铜合金。在一些可选的实施例中，可以使用其他导电材料以代替铜。例如，金属垫210可包括铝、铝合金、金或者金合金等。用于形成衬底120的示例性结构的细节在2010年8月6日提交的名称为“Flip Chip Substrate Package Assembly and Process for Making Same”(代理卷号No.TSM10-0271)的美国专利申请号为No.12/852,196的专利申请中描述，该专利申请通过引用全部并入本文中。
如上所述，金属垫105和210可通过金属线连接至相同金属层上的输入/输出结构或者其他导电结构。图2A示出根据一些实施例的带有互连金属线215的金属垫210的俯视图。图2A中金属垫210是圆形的并且金属垫210之间具有节距P和间距S。金属垫210的直径为D。图2A还示出不适合金属垫215之间的间距S但对金属垫210不短路的三条金属线215。图2B示出根据一些实施例的带有图2A的相同金属线215的金属垫210’的俯视图。图2B的每个金属垫210’具有与图2A的金属垫210相同的表面区域。金属垫210还具有节距P。金属垫210’是伸长的并且具有跑道形状。金属垫210’的宽度为W，也为金属垫210’的圆形部分的直径。由于金属垫210’是伸长的，因而金属垫210’的宽度W小于金属垫210的直径D。结果，金属垫210’之间的间距S’大于S。三个金属线215可适合金属垫210’之间的间距S’内而且不对金属垫210’短路。伸长的金属垫为布置金属线路径提供了附加间距。在一些实施例中，节距P在大约30μm和大约200μm之间。 在一些实施例中，金属垫210的直径D在大约20μm和大约150μm之间。在一些实施例中，金属垫210的宽度W在大约10μm和大约100μm之间。
除提供布置金属线路径的附加间距之外，伸长的金属垫还具有其他优势。图3A示出根据一些实施例的在回流焊之前衬底120的焊料层220直接上方的封装体110的铜柱112的截面图。铜柱112与焊料层220对准，铜柱112的中心与焊料层220的中心形成与衬底120的平坦表面基本垂直的线。图3B示出铜柱112和用于焊料层220的SRO117的俯视图。在图3A和图3B示出的实施例中，铜柱112和SRO117都是圆形的并且具有大约相同的直径。铜柱112的俯视形状与铜柱112下面的UBM层111相同。铜柱112的俯视形状还与铜柱112下面的焊料层113相同。在一些实施例中，焊料层113没有形成在铜柱112上方。封装体110和衬底120的相对位置在回流之前以将焊料层220与铜柱112接合。图3B示出铜柱112完全重叠SRO117，并且所重叠的表面为铜柱112或者SRO117的表面区域。在接合工艺之前，铜柱112与焊料层220对准，并且铜柱112的中心与焊料层220的中心形成与衬底120的平坦表面123基本垂直的线350。
由于封装体110和衬底120中的材料之间的不同的热膨胀系数(CTE)，它们的相对位置在热处理(例如，回流焊)之后可能移动。例如，封装体110包括硅衬底并且具有大约2-3ppm/℃的总体CTE，这比衬底120的总体CTE(为大约17ppm/℃)低。在热处理之后，衬底120会在水平和垂直方向的膨胀超出封装体110，该膨胀导致它们相对位置的移动。它们相对位置的移动在边缘处相对于封装体110和衬底120的中心处更突出。
图3C示出根据一些实施例的在它们接合在一起之后图3A的封装体110和衬底120的结构的截面图。图3C示出由于它的高CTE衬底120相对于封装体110的位置更向边缘移动。图3D示出根据一些实施例的图3C的接合结构的铜柱112和SRO117的俯视图。铜柱112和SRO117的重叠表面300*与图3B(在回流之前)的面积300相比减小了。
图4A示出根据一些实施例的在回流焊之后衬底120的焊料层220上方的封装体110’的铜柱112’的截面图。铜柱112’是伸长的并且具有跑道形状的截面图。在接合工艺之前，铜柱112’与焊料层220对准，并且铜柱112’ 的中心与焊料层220的中心形成与衬底120的平坦表面基本垂直的线。图4A示出衬底120相对于封装体110’的位置更向边缘移动。
图4B示出铜柱112’和用于焊料层220的SRO117的俯视图。铜柱112’和SRO117的重叠面积为400。面积400小于图3B的面积300。然而，面积400大于图3D的面积300*。铜柱112’和SRO117的越大的重叠表面区域使得接合结构更强固，这减少了接合结构上的应力以及界面分层(interfacial delamination)和冷焊(或者虚焊)的风险。
图5A示出根据一些实施例的在回流焊之后衬底120’的焊料层220’上方的封装体110’的铜柱112’的截面图。铜柱112’和焊料层220’具有为跑道形状的伸长截面。在回流焊工艺(或者接合工艺)之前，铜柱112’与焊料层220’对准并且铜柱112’的中心和焊料层220’的中心形成与衬底120的平坦表面基本垂直的线。图5B示出铜柱112’和用于焊料层220’的SRO117’的俯视图。铜柱112’和SRO117’的重叠面积为500。面积500小于图3B的面积300。然而，面积500大于图3D的面积300*。铜柱112’和SRO117’的较大的重叠表面区域使接合结构更强固，这降低了接合结构上的应力以及界面分层和冷焊的风险。
为了降低封装体上接合结构的应力，伸长的接合结构被布置以使伸长的接合结构的轴线基本对准衬底的封装体的中心。图6示出根据一些实施例的在封装体角部的两个示范性的伸长铜柱610以及靠近封装体边缘的中心的铜柱。图6示出伸长铜柱610和610’被布置成使它们的轴线基本对准封装体110的中心C。相类似地，如果金属垫(以及金属垫上的焊料层)也成形为是伸长的，它们应定向为与铜柱610和610’相似以最大化接合面积。伸长铜柱610和610’的这种方位布置，并因而形成接合结构，降低了接合结构(包括铜柱)上的应力。如上所述，由于封装体110和接合衬底120之间的CTE差，封装体110和接合衬底120在热循环期间在不同的温度膨胀和收缩。通过将封装体110上的铜柱的轴线对准以指向封装体110的中心，铜柱的膨胀(加热期间)和收缩(冷却期间)将跟随封装体110的下方衬底的膨胀或者收缩的方向。
在上面图3A-图6描述了轮廓类似于SRO的铜柱和焊料层的形状和方 向的各种实施例。焊料层220下面的金属垫210的形状和方向还影响接合结构的强度和界面分层的可能性。图7A-图7F示出根据一些实施例的在封装体110接合到衬底120之前金属垫210、SRO117、SRO117下面的铜柱112的各种布置的俯视图。这些布置仅是示例性的。其他布置和结构也是可能的。
图7A示出根据一些实施例的铜柱1121与SRO1171以及SRO1171下面的金属垫2101的形状以及对准的俯视图。如上所述，焊料层220的形状与SRO117的形状紧密配合。另外，在铜柱112上方可能存在焊料层113。然而，焊料层113的保护轮廓随同铜柱112的轮廓。如图7A中所示，金属垫2101的直径大于SRO1171的直径。SRO117位于金属垫210的表面内。如上所述，图7A中示出的实施例在接合之后可能具有铜柱1121和SRO1171的表面的较小重叠。铜柱1121的凸块，SRO1171以及SRO1171下面的金属垫2101是同心的。另外，这三个结构的中心C1基本在彼此的顶部。
图7B示出根据一些实施例的铜柱1122与SRO1172以及SRO1172下面的金属垫2102的形状以及对准的俯视图。铜柱1122是伸长的并且成形为跑道形状。SRO1173和SRO1173下面的金属垫2103具有环形表面区域。铜柱1122，SRO1172以及SRO1172下面的金属垫2102的中心和轴线对准为基本一样或者平行以使横穿封装体110和衬底120的接合结构强固和平衡。如上所述，图7B的布置会导致铜柱1122和SRO1172(或者焊料层220)之间重叠更多。另外，这三个结构的中心C2基本在彼此的顶部上。在一些实施例中，这种布置会使得封装体110和衬底120之间的接合结构比在图7A示出的布置具有更低的总体应力，尤其对于接合的封装体的边缘区域附近的接合结构来说。
图7C示出根据一些实施例的铜柱1123与SRO1173和SRO1173下面的金属垫2103的形状以及铜柱1123与SRO1173和SRO1173下面的金属垫2103对准的俯视图。在俯视图中铜柱1123、SRO1173以及SRO1173下面的金属垫2103是伸长的并且呈跑道形状。铜柱1123、SRO1173以及SRO1173下面的金属垫2103的轴线对准并且指向相同的方向。另外，这三个结构的中心C3基本在彼此的顶部。在一些实施例中，这种布置会使得封装体110 和衬底120之间的接合结构具有比图7A中示出布置更低的总体应力，尤其对于接合的封装体的边缘区域附近的接合结构来说。
图7D示出根据一些实施例的铜柱1124与SRO1174和SRO1174下面的金属垫2104的形状以及铜柱1124与SRO1174和SRO1174下面的金属垫2104对准的俯视图。图7D示出SRO1174和金属垫2104具有跑道形状的凸块。SRO1174和金属垫2104的轴线对准以均匀分配来自接合和接合结构的应力。铜柱1124具有环形凸块。另外，这三种结构的中心C4在彼此的顶部上。在一些实施例中，这种布置会使得封装体110和衬底120之间的接合结构比图7A中示出的布置具有较低的总体应力，尤其对于接合的封装体的边缘区域附近的接合结构来说。
图7E示出根据一些实施例的铜柱1125与SRO1175和SRO1175下面的金属垫2105的形状以及铜柱1125与SRO1175和SRO1175下面的金属垫2105对准的俯视图。图7E示出SRO1175和金属垫2105具有呈跑道状的凸块。SRO1175和金属垫2105的轴线对准以均匀分配来自接合和接合结构的应力。SRO1175具有环形凸块。另外，这三种结构的中心C5基本在彼此的顶部上。在一些实施例中这种布置会使得封装体110和衬底120之间的接合结构比图7A中示出的布置具有较低的总体应力，尤其对于接合的封装体的边缘区域附近的接合结构来说。
图7F示出一些实施例的铜柱1126与SRO1176和金属垫2106的形状以及铜柱1126与SRO1176和金属垫2106对准的俯视图。图7F示出铜柱1125和SRO1176具有环形的凸块。金属垫2106具有跑道形状的凸块。为了减小由热循环造成的应力，金属垫2106的轴线应当也基本指向接合的封装体的中心。这三个结构的中心C6基本在彼此的顶部上。
图7A-图7F中所述的实施例示出铜柱112具有比SRO117大的表面区域。然而，这不是必需的或者必要的。铜柱112的表面区域可能等于或者小于SRO117的表面区域。如图4A-5B中所述的伸长铜柱112和/或SRO117的较小应力的优势仍然适用。当铜柱112和/或SRO117是伸长的时，增大了它们之间的接合表面区域，例如，在一个例子中提高了35％，这个例子导致更好的接合完整性。金属垫105与铜柱112的形状、布置和关系类似 于SRO117和金属垫210之间的那些。金属垫105的表面区域等于或者大于铜柱112的表面区域(或者凸块)。图8示出根据一些实施例的铜柱112和金属垫105(或者凸块)的俯视图。铜柱112和金属垫105的中心C8基本重叠。另外，铜柱112和金属垫105的轴线也基本重叠。铜柱112和金属垫105的其他布置和结构也是可能的。
上述的实施例提供了位于封装体和接合衬底之间的接合结构的增大的重叠表面区域。通过在封装体和/或在接合衬底上使用伸长的接合结构并且通过使这些接合结构定向，接合结构被设计成承受由热循环导致的接合应力以减小冷焊。
在一些实施例中，提供了封装结构。所述封装结构包括具有连接结构的管芯封装体，所述连接结构包括铜柱，并且铜柱具有第一截面积。所述封装结构还包括衬底并且焊料层填充金属垫上方的开口。所述焊料层与金属垫直接接触，并且所述开口具有第二截面积。所述金属垫具有第三表面区域，并且第一表面区域、第二表面区域以及第三表面区域中的至少之一具有伸长的形状。所述第三表面区域比第二表面区域大。焊料层形成具有在管芯封装体上的连接结构的接合结构。
在一些实施例中，提供了封装结构。所述封装结构包括通过第一接合结构接合至衬底的封装体。所述第一接合结构包括接合至封装体中的第一金属垫的铜柱，并且所述封装体包括至少一个半导体管芯。所述第一接合结构还包括形成在介电材料中的焊料填充开口，并且所述焊料填充开口形成在第二金属垫上方。焊料填充开口中的焊料层直接接触第二金属垫。铜柱的凸块、第一金属垫、焊料填充开口以及第二金属垫的轴线基本重叠并且指向封装体的中心。凸块的至少之一具有伸长形状。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。例如，本领域普通技术人员应当理解可以改变本文所述的许多部件，功能，工艺，以及材料，而保留在本发明的范围内。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明， 现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该将这样的工艺、机器、制造、材料组分、装置、方法或步骤包括在范围内。

Claims (20)

1.一种封装结构，包括：
具有连接结构的管芯封装体，所述连接结构包括铜柱，其中所述铜柱具有第一表面区域；
衬底，具有填充金属垫上方的开口的焊料层，其中所述焊料层与所述金属垫直接接触，所述开口具有第二表面区域，所述金属垫具有第三表面区域，所述第一表面区域、所述第二表面区域以及所述第三表面区域中的至少之一具有伸长形状，其中所述第三表面区域宽于所述第二表面区域，并且所述焊料层与所述管芯封装体上的所述连接结构形成接合结构。
2.如权利要求1所述的封装结构，其中，所述开口被焊料层包围，所述焊料层可通过光刻被图案化。
3.如权利要求1所述的封装结构，其中，所述伸长形状的轴线指向所述管芯封装体的中心。
4.如权利要求1所述的封装结构，其中，所述第一表面区域和所述第二表面区域均具有伸长形状，所述第一表面区域和所述第二表面区域的轴线重叠并且指向所述管芯封装体的中心。
5.如权利要求1所述的封装结构，其中，所述伸长形状是跑道形状。
6.如权利要求4所述的封装结构，其中，所述第三表面区域也是伸长的，并且所述第三表面区域的轴线与所述第一表面区域和所述第二表面区域的轴线重叠。
7.如权利要求1所述的封装结构，进一步包括另一接合结构，这两个接合结构之间的节距在30μm和200μm之间。
8.如权利要求1所述的封装结构，其中，所述伸长形状的宽度在10μm和100μm之间。
9.如权利要求1所述的封装结构，其中，所述衬底具有比所述管芯封装体高的热膨胀系数。
10.如权利要求1所述的封装结构，其中，在所述金属垫和相邻金属垫之间存在至少一根布线金属线；所述至少一根布线金属线具有与所述伸长形状的轴线平行的轴线。
11.如权利要求1所述的封装结构，其中，存在电连接至所述管芯封装体中的所述铜柱的金属垫，并且在该金属垫和相邻金属垫之间存在至少一根布线金属线，所述至少一根布线金属线具有与所述伸长形状的轴线平行的轴线。
12.一种封装结构，包括：
通过第一接合结构接合至衬底的封装体，其中，所述第一接合结构包括：
接合至所述封装体中的第一金属垫的铜柱，所述封装体包括至少一个半导体管芯，
形成在介电材料中的焊料填充开口，所述焊料填充开口形成在第二金属垫上方，所述焊料填充开口中的焊料层直接接触所述第二金属垫，所述铜柱的凸块、所述第一金属垫、所述焊料填充开口以及所述第二金属垫的轴线重叠并且所述铜柱的凸块、所述第一金属垫以及所述焊料填充开口中的至少一个的轴线是伸长的并且指向所述封装体的中心。
13.如权利要求12所述的封装结构，其中，所述封装结构包括与所述第一接合结构相邻的第二接合结构，并且这两个相邻的接合结构的节距在30μm和200μm之间。
14.如权利要求13所述的封装结构，其中，在与所述第一金属垫或者所述第二金属垫相同的水平上存在至少一根布线金属线，所述至少一根布线金属线位于这两个接合结构之间。
15.如权利要求12所述的封装结构，其中，在所述铜柱和所述第一金属垫之间存在凸点下金属化(UBM)层。
16.如权利要求12所述的封装结构，其中，所述衬底包括选自双马来酰亚胺三嗪(BT)树脂、FR-4、FR-5、陶瓷、玻璃、塑料以及胶带的材料。
17.如权利要求12所述的封装结构，其中，所述焊料填充开口由阻焊层围绕。
18.如权利要求12所述的封装结构，其中，所述铜柱的所述凸块、所述第一金属垫、所述焊料填充开口以及所述第二金属垫都具有伸长形状。
19.如权利要求18所述的封装结构，其中，所述伸长形状成形为跑道形状。
20.如权利要求18所述的封装结构，其中，所述铜柱的所述凸块和所述焊料填充开口是伸长的。
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8624392B2 (en) 2011-06-03 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
CN103814439B (zh) * 2011-09-09 2016-10-19 株式会社村田制作所 模块基板
US9548281B2 (en) 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US8912668B2 (en) 2012-03-01 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
US9196573B2 (en) 2012-07-31 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure
US8829673B2 (en) 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US9673161B2 (en) 2012-08-17 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US20150022987A1 (en) * 2013-07-18 2015-01-22 Stmicroelectronics (Crolles 2) Sas Electronic device comprising an integrated circuit chip provided with projecting electrical connection pads
US9824990B2 (en) 2014-06-12 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9881857B2 (en) * 2014-06-12 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
CN104835796A (zh) * 2015-05-07 2015-08-12 嘉兴斯达微电子有限公司 一种无铅扩散焊的功率模块
US10049996B2 (en) * 2016-04-01 2018-08-14 Intel Corporation Surface finishes for high density interconnect architectures
US20180047692A1 (en) * 2016-08-10 2018-02-15 Amkor Technology, Inc. Method and System for Packing Optimization of Semiconductor Devices
US10120424B2 (en) 2017-01-19 2018-11-06 Intel Corporation Conductive stress-relief washers in microelectronic assemblies
US10818624B2 (en) * 2017-10-24 2020-10-27 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method for manufacturing the same
KR102746088B1 (ko) * 2019-10-08 2024-12-26 삼성전자주식회사 반도체 패키지
KR20220022762A (ko) 2020-08-19 2022-02-28 삼성전자주식회사 반도체 패키지
TWI821835B (zh) * 2021-12-23 2023-11-11 大陸商青島新核芯科技有限公司 基板結構及其製造方法
CN115360158B (zh) * 2022-08-04 2025-03-07 深圳市聚飞光电股份有限公司 一种芯片安装结构和光源板

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5859474A (en) * 1997-04-23 1999-01-12 Lsi Logic Corporation Reflow ball grid array assembly
US6913948B2 (en) * 1999-11-10 2005-07-05 International Business Machines Corporation Partially captured oriented interconnections for BGA packages and a method of forming the interconnections

Family Cites Families (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02170548A (ja) 1988-12-23 1990-07-02 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
US5591941A (en) 1993-10-28 1997-01-07 International Business Machines Corporation Solder ball interconnected assembly
JP2867313B2 (ja) * 1993-12-10 1999-03-08 日本特殊陶業株式会社 セラミック基板
US6284563B1 (en) 1995-10-31 2001-09-04 Tessera, Inc. Method of making compliant microelectronic assemblies
US5898223A (en) 1997-10-08 1999-04-27 Lucent Technologies Inc. Chip-on-chip IC packages
JP3416040B2 (ja) 1997-11-11 2003-06-16 富士通株式会社 半導体装置
US6268568B1 (en) 1999-05-04 2001-07-31 Anam Semiconductor, Inc. Printed circuit board with oval solder ball lands for BGA semiconductor packages
US6181569B1 (en) 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6387734B1 (en) 1999-06-11 2002-05-14 Fujikura Ltd. Semiconductor package, semiconductor device, electronic device and production method for semiconductor package
US6861345B2 (en) 1999-08-27 2005-03-01 Micron Technology, Inc. Method of disposing conductive bumps onto a semiconductor device
US6339534B1 (en) 1999-11-05 2002-01-15 International Business Machines Corporation Compliant leads for area array surface mounted components
US6294840B1 (en) 1999-11-18 2001-09-25 Lsi Logic Corporation Dual-thickness solder mask in integrated circuit package
JP4313520B2 (ja) 2001-03-19 2009-08-12 株式会社フジクラ 半導体パッケージ
TW498506B (en) 2001-04-20 2002-08-11 Advanced Semiconductor Eng Flip-chip joint structure and the processing thereof
US20020164836A1 (en) 2001-05-07 2002-11-07 Advanced Semiconductor Engineering Inc. Method of manufacturing printed circuit board
WO2003023851A1 (en) 2001-09-07 2003-03-20 Ricoh Company, Ltd. Semiconductor device and voltage regulator
US6864565B1 (en) 2001-12-06 2005-03-08 Altera Corporation Post-passivation thick metal pre-routing for flip chip packaging
JP3829325B2 (ja) 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
JP3560599B2 (ja) 2002-04-26 2004-09-02 松下電器産業株式会社 電子回路装置
JP3542350B2 (ja) 2002-05-31 2004-07-14 沖電気工業株式会社 半導体装置及びその製造方法
AU2003256360A1 (en) 2002-06-25 2004-01-06 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
US6984545B2 (en) 2002-07-22 2006-01-10 Micron Technology, Inc. Methods of encapsulating selected locations of a semiconductor die assembly using a thick solder mask
JP3580803B2 (ja) 2002-08-09 2004-10-27 沖電気工業株式会社 半導体装置
US6642597B1 (en) 2002-10-16 2003-11-04 Lsi Logic Corporation Inter-layer interconnection structure for large electrical connections
JP3611561B2 (ja) 2002-11-18 2005-01-19 沖電気工業株式会社 半導体装置
KR100463442B1 (ko) 2002-12-23 2004-12-23 삼성전기주식회사 볼 그리드 어레이 기판 및 이의 제조방법
US6998532B2 (en) 2002-12-24 2006-02-14 Matsushita Electric Industrial Co., Ltd. Electronic component-built-in module
US7038917B2 (en) 2002-12-27 2006-05-02 Vlt, Inc. Low loss, high density array interconnection
US6946744B2 (en) * 2003-04-24 2005-09-20 Power-One Limited System and method of reducing die attach stress and strain
JP2005129663A (ja) 2003-10-22 2005-05-19 Internatl Business Mach Corp <Ibm> 多層配線基板
US6927498B2 (en) * 2003-11-19 2005-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad for flip chip package
JP2005301056A (ja) 2004-04-14 2005-10-27 Hitachi Displays Ltd 表示装置とその製造方法
TWI243462B (en) 2004-05-14 2005-11-11 Advanced Semiconductor Eng Semiconductor package including passive component
EP1769531A2 (en) 2004-07-13 2007-04-04 Koninklijke Philips Electronics N.V. Assembly and method of placing the assembly on an external board
WO2006050127A2 (en) 2004-10-29 2006-05-11 Flipchip International, Llc Semiconductor device package with bump overlying a polymer layer
US7288472B2 (en) * 2004-12-21 2007-10-30 Intel Corporation Method and system for performing die attach using a flame
US20060160346A1 (en) 2005-01-19 2006-07-20 Intel Corporation Substrate bump formation
US7361990B2 (en) 2005-03-17 2008-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads
US7566650B2 (en) 2005-09-23 2009-07-28 Stats Chippac Ltd. Integrated circuit solder bumping system
US7397121B2 (en) 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
KR100804392B1 (ko) 2005-12-02 2008-02-15 주식회사 네패스 반도체 패키지 및 그 제조 방법
US20070148951A1 (en) 2005-12-27 2007-06-28 Mengzhi Pang System and method for flip chip substrate pad
TWI293789B (en) 2006-02-27 2008-02-21 Advanced Semiconductor Eng Redistribution connecting structure of solder balls
TWI307132B (en) 2006-03-24 2009-03-01 Via Tech Inc Chip package and fabricating method thereof
US8188590B2 (en) 2006-03-30 2012-05-29 Stats Chippac Ltd. Integrated circuit package system with post-passivation interconnection and integration
US20100117231A1 (en) 2006-08-30 2010-05-13 Dennis Lang Reliable wafer-level chip-scale solder bump structure
JP4219951B2 (ja) 2006-10-25 2009-02-04 新光電気工業株式会社 はんだボール搭載方法及びはんだボール搭載基板の製造方法
US20080182398A1 (en) 2007-01-30 2008-07-31 Carpenter Burton J Varied Solder Mask Opening Diameters Within a Ball Grid Array Substrate
US7973418B2 (en) 2007-04-23 2011-07-05 Flipchip International, Llc Solder bump interconnect for improved mechanical and thermo-mechanical performance
US8178392B2 (en) * 2007-05-18 2012-05-15 Stats Chippac Ltd. Electronic system with expansion feature
KR100852176B1 (ko) 2007-06-04 2008-08-13 삼성전자주식회사 인쇄회로보드 및 이를 갖는 반도체 모듈
KR100876899B1 (ko) 2007-10-10 2009-01-07 주식회사 하이닉스반도체 반도체 패키지
US7863742B2 (en) 2007-11-01 2011-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Back end integrated WLCSP structure without aluminum pads
JP5079456B2 (ja) 2007-11-06 2012-11-21 新光電気工業株式会社 半導体装置及びその製造方法
TWI357644B (en) 2007-12-18 2012-02-01 Advanced Semiconductor Eng A semiconductor package and method for manufacturi
US7812438B2 (en) 2008-01-07 2010-10-12 International Business Machines Corporation Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packaging
JP5150518B2 (ja) 2008-03-25 2013-02-20 パナソニック株式会社 半導体装置および多層配線基板ならびにそれらの製造方法
JP2009277916A (ja) 2008-05-15 2009-11-26 Shinko Electric Ind Co Ltd 配線基板及びその製造方法並びに半導体パッケージ
TW201009963A (en) 2008-08-18 2010-03-01 Unimicron Technology Corp Flip-chip package and method thereof
GB2464549B (en) 2008-10-22 2013-03-27 Cambridge Silicon Radio Ltd Improved wafer level chip scale packaging
KR20100104377A (ko) 2009-03-17 2010-09-29 삼성전자주식회사 내부 스트레스를 줄일 수 있는 반도체 패키지
US8080880B2 (en) 2009-03-20 2011-12-20 Infineon Technologies Ag Semiconductor device with arrangement of parallel conductor lines being insulated, between and orthogonal to external contact pads
US8405211B2 (en) 2009-05-08 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Bump pad structure
JP5185885B2 (ja) 2009-05-21 2013-04-17 新光電気工業株式会社 配線基板および半導体装置
US8227918B2 (en) 2009-09-16 2012-07-24 International Business Machines Corporation Robust FBEOL and UBM structure of C4 interconnects
US8445329B2 (en) 2009-09-30 2013-05-21 Ati Technologies Ulc Circuit board with oval micro via
US8299632B2 (en) 2009-10-23 2012-10-30 Ati Technologies Ulc Routing layer for mitigating stress in a semiconductor die
US8227926B2 (en) 2009-10-23 2012-07-24 Ati Technologies Ulc Routing layer for mitigating stress in a semiconductor die
US9607936B2 (en) * 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
US8847387B2 (en) * 2009-10-29 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Robust joint structure for flip-chip bonding
US8084871B2 (en) 2009-11-10 2011-12-27 Maxim Integrated Products, Inc. Redistribution layer enhancement to improve reliability of wafer level packaging
TWI392066B (zh) * 2009-12-28 2013-04-01 矽品精密工業股份有限公司 封裝結構及其製法
US20110227216A1 (en) 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices
US8891246B2 (en) 2010-03-17 2014-11-18 Intel Corporation System-in-package using embedded-die coreless substrates, and processes of forming same
US8686560B2 (en) 2010-04-07 2014-04-01 Maxim Integrated Products, Inc. Wafer-level chip-scale package device having bump assemblies configured to mitigate failures due to stress
US9142533B2 (en) * 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US20120032337A1 (en) 2010-08-06 2012-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Flip Chip Substrate Package Assembly and Process for Making Same
US8390119B2 (en) * 2010-08-06 2013-03-05 Mediatek Inc. Flip chip package utilizing trace bump trace interconnection
US8293636B2 (en) 2010-08-24 2012-10-23 GlobalFoundries, Inc. Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method
KR101695353B1 (ko) 2010-10-06 2017-01-11 삼성전자 주식회사 반도체 패키지 및 반도체 패키지 모듈
US20120098120A1 (en) * 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Centripetal layout for low stress chip package
US8445355B2 (en) 2010-12-15 2013-05-21 International Business Machines Corporation Metal-insulator-metal capacitors with high capacitance density
KR101189081B1 (ko) * 2010-12-16 2012-10-10 엘지이노텍 주식회사 웨이퍼 기판 접합 구조, 이를 포함하는 발광 소자 및 그 제조 방법
US20120193778A1 (en) 2011-01-27 2012-08-02 Texas Instruments Incorporated Integrated circuit having protruding bonding features with reinforcing dielectric supports
US8624392B2 (en) 2011-06-03 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US8496159B2 (en) 2011-06-06 2013-07-30 International Business Machines Corporation Injection molded solder process for forming solder bumps on substrates
US9905524B2 (en) * 2011-07-29 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures in semiconductor device and packaging assembly
US9053989B2 (en) * 2011-09-08 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated bump structure in semiconductor device
US8598691B2 (en) * 2011-09-09 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing and packaging thereof
US8912668B2 (en) 2012-03-01 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
US9548281B2 (en) 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US8729699B2 (en) 2011-10-18 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connector structures of integrated circuits
US20130099371A1 (en) * 2011-10-21 2013-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having solder jointed region with controlled ag content
US9257385B2 (en) * 2011-12-07 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Landing areas of bonding structures
US9418947B2 (en) * 2012-02-27 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming connectors with a molding compound for package on package
US9196573B2 (en) 2012-07-31 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure
US8829673B2 (en) 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5859474A (en) * 1997-04-23 1999-01-12 Lsi Logic Corporation Reflow ball grid array assembly
US6913948B2 (en) * 1999-11-10 2005-07-05 International Business Machines Corporation Partially captured oriented interconnections for BGA packages and a method of forming the interconnections

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US20190123008A1 (en) 2019-04-25
US9196573B2 (en) 2015-11-24
TWI531036B (zh) 2016-04-21
TW201405742A (zh) 2014-02-01
US9748188B2 (en) 2017-08-29
US20170345783A1 (en) 2017-11-30
US20160064347A1 (en) 2016-03-03
US10163839B2 (en) 2018-12-25
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US20140035148A1 (en) 2014-02-06
US10515917B2 (en) 2019-12-24

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