CN102005430A - Double-sided graphics chip flip-chip module packaging method adopting plating firstly and etching secondly - Google Patents
Double-sided graphics chip flip-chip module packaging method adopting plating firstly and etching secondly Download PDFInfo
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- CN102005430A CN102005430A CN2010102729997A CN201010272999A CN102005430A CN 102005430 A CN102005430 A CN 102005430A CN 2010102729997 A CN2010102729997 A CN 2010102729997A CN 201010272999 A CN201010272999 A CN 201010272999A CN 102005430 A CN102005430 A CN 102005430A
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000005530 etching Methods 0.000 title claims abstract description 22
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 9
- 238000007747 plating Methods 0.000 title description 15
- 239000002184 metal Substances 0.000 claims abstract description 155
- 229910052751 metal Inorganic materials 0.000 claims abstract description 155
- 239000000758 substrate Substances 0.000 claims abstract description 108
- 239000004033 plastic Substances 0.000 claims abstract description 52
- 239000000945 filler Substances 0.000 claims abstract description 32
- 239000011248 coating agent Substances 0.000 claims abstract description 14
- 238000000576 coating method Methods 0.000 claims abstract description 14
- 239000011265 semifinished product Substances 0.000 claims abstract description 7
- 238000009713 electroplating Methods 0.000 claims abstract description 5
- 150000001875 compounds Chemical class 0.000 claims abstract 14
- 238000012856 packing Methods 0.000 claims description 14
- 238000005538 encapsulation Methods 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 239000000047 product Substances 0.000 claims description 7
- 238000005520 cutting process Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims 22
- 238000000465 moulding Methods 0.000 claims 4
- 239000007888 film coating Substances 0.000 claims 2
- 238000009501 film coating Methods 0.000 claims 2
- 238000002360 preparation method Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 239000003822 epoxy resin Substances 0.000 abstract description 23
- 229920000647 polyepoxide Polymers 0.000 abstract description 23
- 239000012528 membrane Substances 0.000 description 58
- 239000005022 packaging material Substances 0.000 description 39
- 238000003384 imaging method Methods 0.000 description 18
- 239000000463 material Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 238000007789 sealing Methods 0.000 description 8
- 238000011112 process operation Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本发明涉及一种双面图形芯片倒装先镀后刻模组封装方法，所述方法包括以下工艺步骤：取金属基板；金属基板正面进行金属层电镀被覆；金属基板进行背面蚀刻作业；金属基板背面进行包封无填料的塑封料(环氧树脂)作业；金属基板正面进行各图形的蚀刻作业，蚀刻出引脚的正面，且使所述引脚的背面尺寸小于引脚的正面尺寸，形成上大下小的引脚结构；装片；半成品正面进行包封有填料塑封料(环氧树脂)作业；引脚的背面进行金属层电镀被覆；切割，使原本以列阵式集合体方式连在一起的芯片一颗颗独立开来，制得双面图形芯片倒装模组封装结构成品。本发明方法制备的芯片封装结构不会再有产生掉脚的问题。
The invention relates to a double-sided graphic chip flip-chip packaging method firstly plated and then engraved with a module. The method includes the following process steps: taking a metal substrate; performing metal layer electroplating coating on the front of the metal substrate; performing etching on the back of the metal substrate; Encapsulate the plastic compound (epoxy resin) without filler on the back; etch each pattern on the front of the metal substrate to etch the front of the pin, and make the back of the pin smaller than the front of the pin to form Pin structure with upper and lower pins; chip loading; the front of the semi-finished product is encapsulated with filler plastic compound (epoxy resin); the back of the pin is electroplated and coated with a metal layer; The combined chips are separated one by one to obtain a finished double-sided graphic chip flip-chip module packaging structure. The chip packaging structure prepared by the method of the invention will not have the problem of pin drop.
Description
(1) technical field
The present invention relates to a kind of two-sided graphic chips upside-down mounting plating back die sinking earlier group method for packing.Belong to the semiconductor packaging field.
(2) background technology
The production method of traditional chip-packaging structure is: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in figure 13) of lead frame.Etching is then carried out at the back side of lead frame again in encapsulation process.This method has the following disadvantages:
Because only carried out the work that etches partially before the plastic packaging in the metal substrate front, and plastic packaging material only wraps the height of half pin of pin in the plastic packaging process, so the constraint ability of plastic-sealed body and pin has just diminished, when if the plastic-sealed body paster is not fine to pcb board, do over again again and heavily paste, with regard to the problem (as shown in figure 14) that is easy to generate pin.Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
In addition, because the distance between chip and the pin is far away, the length of metal wire is longer, shown in Figure 15～16, and metal wire cost higher (the especially metal wire of Ang Gui proof gold matter); Same because the length of metal wire is longer, make that the signal output speed of chip is slow (especially the product of storage class and the calculating that needs mass data are more outstanding); Too because the length of metal wire is longer, so also higher to the interference of signal in existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole; Because the distance between chip and the pin is far away, make that the volume and the area of encapsulation are bigger again, material cost is higher, and discarded object is more.
(3) summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, a kind of two-sided graphic chips upside-down mounting plating back die sinking earlier group method for packing of not having the problem that produces pin again is provided.
The object of the present invention is achieved like this: a kind of two-sided graphic chips upside-down mounting plating back die sinking earlier group method for packing, and described method comprises following processing step:
Get the suitable metal substrate of a slice thickness,
Utilization by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up electroplated metal layer process operation,
The photoresistance glued membrane in step 3, metal substrate front needs the exposure of plated metal layer region/develop and windows
The metal substrate front that utilizes exposure imaging equipment that step 2 is finished photoresistance glued membrane lining operation is carried out exposure imaging and is removed part photoresistance glued membrane, carries out the zone of electroplated metal layer to expose the positive follow-up needs of metal substrate,
The zone of having windowed in step 4, metal substrate front is carried out metal level and is electroplated lining
The first metal layer plating lining is carried out in the zone of having windowed in metal substrate front in the step 3, and this first metal layer places the front of described pin,
Photoresistance glued membrane striping is carried out at step 5, metal substrate front and the back side
The positive remaining photoresistance glued membrane of metal substrate and the photoresistance glued membrane at the metal substrate back side are all removed,
Utilization by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up etch process operation,
The photoresistance glued membrane at step 7, the metal substrate back side needs the exposure of etching area/develop and windows
Exposure imaging removal part photoresistance glued membrane is carried out at the metal substrate back side that utilizes exposure imaging equipment that step 6 is finished photoresistance glued membrane lining operation, prepares against the metal substrate back etched operation that follow-up needs carry out to expose the localized metallic substrate,
Step 8, metal substrate carry out the back etched operation
After the exposure/development and windowing task of completing steps seven, promptly carry out the etching operation of each figure, etch the back side of pin, simultaneously the pin front is extended to the below of described follow-up pasting chip at the back side of metal substrate,
Photoresistance glued membrane striping is carried out at step 9, metal substrate front and the back side
The photoresistance glued membrane of metal substrate back side remainder and the photoresistance glued membrane in metal substrate front are all removed,
Step 10, seal packless plastic packaging material (epoxy resin)
Packless plastic packaging material operation is sealed at the metal substrate back side of completing steps nine described striping operations, and carry out curing operation after plastic packaging material is sealed, make the zone and the zone between pin and the pin of pin periphery all set packless plastic packaging material (epoxy resin), this packless plastic packaging material (epoxy resin) links into an integrated entity periphery, pin bottom and pin bottom and pin bottom
Step 11, lining photoresistance glued membrane
Utilization by coating equipment in the front that will finish the metal substrate of sealing the operation of no filler plastic packaging material and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up etch process operation,
Step 12, the front of having finished the metal substrate of sealing the operation of no filler plastic packaging material need the exposure of etching area/develop and window
Exposure imaging removal part photoresistance glued membrane is carried out in the metal substrate front of sealing the operation of no filler plastic packaging material of finishing that utilizes exposure imaging equipment that step 11 is finished photoresistance glued membrane lining operation, carries out the operation of metal substrate front-side etch in order to follow-up needs,
Step 13, the operation of metal substrate front-side etch
After the exposure/development and windowing task of completing steps 12, promptly finish the etching operation that each figure is carried out in the metal substrate front of sealing the operation of no filler plastic packaging material, etch the front of pin, and make the positive size of the back side size of described pin less than pin, form up big and down small pin configuration
Photoresistance glued membrane striping is carried out at step 14, metal substrate front and the back side
The positive remaining photoresistance glued membrane of the metal substrate of completing steps 13 etching operations and the photoresistance glued membrane at the metal substrate back side are all removed, make lead frame,
On the pin front the first metal layer below the described follow-up pasting chip, carry out the implantation of chip by the bonding material of tin metal,
Step 10 six, be encapsulated with filler plastic packaging material (epoxy resin)
The semi-finished product front that load is finished is encapsulated with filler plastic packaging material (epoxy resin) operation, and carries out the curing operation after plastic packaging material is sealed, and makes the top of pin and chip all be had filler plastic packaging material (epoxy resin) to seal outward,
The back side of step 10 seven, pin is carried out metal level and is electroplated lining
The back side that completing steps 16 is encapsulated with the described pin of filler plastic packaging material (epoxy resin) operation is carried out second metal level and is electroplated the lining operation,
Step 10 eight, cutting finished product
The semi-finished product of ten seven the second metal levels of completing steps being electroplated lining carry out cutting operation, make originally more than of chips that connect together in array formula aggregate mode independent, make two-sided graphic chips upside-down mounting module package structure finished product.
The invention has the beneficial effects as follows:
1, guarantees not have again the problem that produces pin
Because lead frame has adopted two-sided etched technology, so planning and designing easily with produce up big and down small pin configuration, the levels plastic packaging material is wrapped up big and down small pin configuration closely together, so the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again.
2, separate etched technology owing to used the lead frame back side with the front, so the pin in lead frame front can be extended to as much as possible the center of packaging body, impel chip and the Pin locations can be identical with the position of chip bonding, as shown in figure 12, so electrical transmission can promote (especially the product of storage class and the calculating that needs mass data are more outstanding) significantly.
3, the volume of encapsulation and area can significantly be dwindled
Because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin.
4, material cost and material usage reduce
Because volume after being encapsulated is significantly dwindled, more direct embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
(4) description of drawings
Fig. 1 (A)～Fig. 1 (Q) is the two-sided graphic chips upside-down mounting of the present invention plating back die sinking earlier group method for packing embodiment 1 each operation schematic diagram.
Fig. 2 is the two-sided graphic chips upside-down mounting of the present invention module package structure embodiment 1 structural representation.
Fig. 3 is the vertical view of Fig. 2.
Fig. 4 (A)～Fig. 4 (Q) is the two-sided graphic chips upside-down mounting of the present invention plating back die sinking earlier group method for packing embodiment 2 each operation schematic diagram.
Fig. 5 is the two-sided graphic chips upside-down mounting of the present invention module package structure embodiment 2 structural representations.
Fig. 6 is the vertical view of Fig. 5.
Fig. 7 (A)～Fig. 7 (Q) is the two-sided graphic chips upside-down mounting of the present invention plating back die sinking earlier group method for packing embodiment 3 each operation schematic diagram.
Fig. 8 is the two-sided graphic chips upside-down mounting of the present invention module package structure embodiment 3 structural representations.
Fig. 9 is the vertical view of Fig. 8.
Figure 10 (A)～Figure 10 (Q) is the two-sided graphic chips upside-down mounting of the present invention plating back die sinking earlier group method for packing embodiment 4 each operation schematic diagram.
Figure 11 is the two-sided graphic chips upside-down mounting of the present invention module package structure embodiment 4 structural representations.
Figure 12 is the vertical view of Figure 11.
Figure 13 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Figure 14 pin figure for what formed in the past.
Figure 15 is encapsulating structure one schematic diagram in the past.
Figure 16 is the vertical view of Figure 15.
Reference numeral among the figure:
(5) embodiment
The two-sided graphic chips upside-down mounting of the present invention plating back die sinking earlier group method for packing is as follows:
Embodiment 1: single-chip individual pen pin
Referring to Fig. 2 and Fig. 3, Fig. 2 is the two-sided graphic chips upside-down mounting of the present invention module package structure embodiment 1 structural representation.Fig. 3 is the vertical view of Fig. 2.By Fig. 2 and Fig. 3 as can be seen, the two-sided graphic chips upside-down mounting of the present invention module package structure, comprise pin 2, packless plastic packaging material (epoxy resin) 3, the bonding material 6 of tin metal, chip 7 and filler plastic packaging material (epoxy resin) 9 is arranged, described pin 2 fronts extend to the below of follow-up pasting chip, be provided with the first metal layer 4 in the front of described pin 2, be provided with second metal level 5 at the back side of described pin 2, bonding material 6 by tin metal on the 2 front the first metal layers 4 of the pin below the described follow-up pasting chip is provided with chip 7, outside the top of described pin 2 and chip 7, be encapsulated with filler plastic packaging material (epoxy resin) 9, be equipped with packless plastic packaging material (epoxy resin) 3 in the zone of described pin 2 peripheries and the zone between pin 2 and the pin 2, described packless plastic packaging material (epoxy resin) 3 links into an integrated entity periphery, pin bottom and pin 2 bottoms and pin 2 bottoms, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration.
Its method for packing is as follows:
Referring to Fig. 1 (A), get the suitable metal substrate of a slice thickness 10.The material of metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper, aluminium, iron, copper alloy or dilval etc.
Referring to Fig. 1 (B), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 11 and 12 of exposure imaging, to protect follow-up electroplated metal layer process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane in step 3, metal substrate front needs the exposure of plated metal layer region/develop and windows
Referring to Fig. 1 (C), the metal substrate front that utilizes exposure imaging equipment that step 2 is finished photoresistance glued membrane lining operation is carried out exposure imaging and is removed part photoresistance glued membrane, carries out the zone of electroplated metal layer to expose the positive follow-up needs of metal substrate.
The zone of having windowed in step 4, metal substrate front is carried out metal level and is electroplated lining
Referring to Fig. 1 (D), the first metal layer 4 plating linings are carried out in the zone of having windowed in metal substrate front in the step 3, this first metal layer 4 places the front of described pin 2.
Photoresistance glued membrane striping is carried out at step 5, metal substrate front and the back side
Referring to Fig. 1 (E), the positive remaining photoresistance glued membrane of metal substrate and the photoresistance glued membrane at the metal substrate back side are all removed.
Referring to Fig. 1 (F), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 13 and 14 of exposure imaging, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane at step 7, the metal substrate back side needs the exposure of etching area/develop and windows
Referring to Fig. 1 (G), exposure imaging removal part photoresistance glued membrane is carried out at the metal substrate back side that utilizes exposure imaging equipment that step 6 is finished photoresistance glued membrane lining operation, to expose the metal substrate back etched operation that the localized metallic substrate carries out in order to follow-up needs.
Step 8, metal substrate carry out the back etched operation
Referring to Fig. 1 (H), after the exposure/development and windowing task of completing steps seven, promptly carry out the etching operation of each figure at the back side of metal substrate, etch the back side of pin 2, simultaneously the pin front is extended to as much as possible the below of described follow-up pasting chip.
Photoresistance glued membrane striping is carried out at step 9, metal substrate front and the back side
Referring to Fig. 1 (I), the photoresistance glued membrane of metal substrate back side remainder and the photoresistance glued membrane in metal substrate front are all removed.
Step 10, seal packless plastic packaging material (epoxy resin)
Referring to Fig. 1 (J), packless plastic packaging material (epoxy resin) operation is sealed at the metal substrate back side of completing steps nine described striping operations, and carry out curing operation after plastic packaging material is sealed, make the zone of pin 2 peripheries and the zone between pin 2 and the pin 2 all set packless plastic packaging material (epoxy resin) 3, this packless plastic packaging material 3 links into an integrated entity periphery, pin bottom and pin 2 bottoms and pin 2 bottoms.
Step 11, lining photoresistance glued membrane
Referring to Fig. 1 (K), utilize by coating equipment in the front that will finish the metal substrate of sealing the operation of no filler plastic packaging material and the back side be covered respectively and can carry out the photoresistance glued membrane 15 and 16 of exposure imaging, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
Step 12, the front of having finished the metal substrate of sealing the operation of no filler plastic packaging material need the exposure of etching area/develop and window
Referring to Fig. 1 (L), exposure imaging removal part photoresistance glued membrane is carried out in the metal substrate front of sealing the operation of no filler plastic packaging material of finishing that utilizes exposure imaging equipment that step 11 is finished photoresistance glued membrane lining operation, carries out the operation of metal substrate front-side etch in order to follow-up needs.
Step 13, the operation of metal substrate front-side etch
Referring to Fig. 1 (M), after the exposure/development and windowing task of completing steps 12, promptly finish the etching operation that each figure is carried out in the metal substrate front of sealing the operation of no filler plastic packaging material, etch the front of pin 2, and make the positive size of the back side size of described pin 2, form up big and down small pin 2 structures less than pin 2.
Photoresistance glued membrane striping is carried out at step 14, metal substrate front and the back side
Referring to Fig. 1 (N), the positive remaining photoresistance glued membrane of the metal substrate of completing steps 13 etching operations and the photoresistance glued membrane at the metal substrate back side are all removed, make lead frame.
Referring to Fig. 1 (O), the bonding material 6 by tin metal on the 2 front the first metal layers 4 of the pin below the described follow-up pasting chip carries out the implantation of chip 7.
Step 10 six, be encapsulated with filler plastic packaging material (epoxy resin)
Referring to Fig. 1 (P), the semi-finished product front that load is finished is encapsulated with filler plastic packaging material (epoxy resin) 9 operations, and carries out the curing operation after plastic packaging material is sealed, and makes the top of pin and chip all be had filler plastic packaging material (epoxy resin) to seal outward.
The back side of step 10 seven, pin is carried out metal level and is electroplated lining
Referring to Fig. 1 (Q), the back side that completing steps 16 is encapsulated with the described pin of filler plastic packaging material (epoxy resin) operation is carried out second metal level 5 and is electroplated the lining operations, and the material of electroplating can be tin, nickel gold, NiPdAu .... wait metal material.
Step 10 eight, cutting finished product
Referring to Fig. 2 and Fig. 3, the semi-finished product of ten seven the second metal levels of completing steps being electroplated lining carry out cutting operation, make originally more than of chips that connect together in array formula aggregate mode independent, make two-sided graphic chips upside-down mounting module package structure finished product.
Embodiment 2: single-chip multi-turn pin
Referring to Fig. 4～6, Fig. 4 (A)～Fig. 4 (R) is the two-sided graphic chips upside-down mounting of the present invention plating back die sinking earlier group method for packing embodiment 2 each operation schematic diagram.Fig. 5 is the two-sided graphic chips upside-down mounting of the present invention module package structure embodiment 2 structural representations.Fig. 6 is the vertical view of Fig. 5.By Fig. 4, Fig. 5 and Fig. 6 as can be seen, embodiment 2 only is with the difference of embodiment 1: described pin 2 equipment have multi-turn.
Embodiment 3: multicore sheet individual pen pin
Referring to Fig. 7～9, Fig. 7 (A)～Fig. 7 (R) is the two-sided graphic chips upside-down mounting of the present invention plating back die sinking earlier group method for packing embodiment 3 each operation schematic diagram.Fig. 8 is the two-sided graphic chips upside-down mounting of the present invention module package structure embodiment 3 structural representations.Fig. 9 is the vertical view of Fig. 8.By Fig. 7, Fig. 8 and Fig. 9 as can be seen, embodiment 3 only is with the difference of embodiment 1: described chip 7 is provided with many.
Embodiment 4: multicore sheet multi-turn pin
Referring to Figure 10～12, Figure 10 (A)～Figure 10 (R) is the two-sided graphic chips upside-down mounting of the present invention plating back die sinking earlier group method for packing embodiment 4 each operation schematic diagram.Figure 11 is the two-sided graphic chips upside-down mounting of the present invention module package structure embodiment 4 structural representations.Figure 12 is the vertical view of Figure 11.By Figure 10, Figure 11 and Figure 12 as can be seen, embodiment 4 only is with the difference of embodiment 1: described pin 2 equipment have multi-turn, and chip 7 is provided with many.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010102729997A CN102005430B (en) | 2010-09-04 | 2010-09-04 | Double-sided graphics chip flip-chip module packaging method adopting plating firstly and etching secondly |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010102729997A CN102005430B (en) | 2010-09-04 | 2010-09-04 | Double-sided graphics chip flip-chip module packaging method adopting plating firstly and etching secondly |
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| CN102005430B CN102005430B (en) | 2011-12-21 |
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| CN102867802A (en) * | 2012-05-09 | 2013-01-09 | 江苏长电科技股份有限公司 | Multi-chip reversely-arranged etched-encapsulated base island-exposed encapsulating structure and manufacturing method thereof |
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| CN102867802B (en) * | 2012-05-09 | 2015-03-04 | 江苏长电科技股份有限公司 | Multi-chip reversely-arranged etched-encapsulated base island-exposed encapsulating structure and manufacturing method thereof |
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| CN102005430B (en) | 2011-12-21 |
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