CN101950726B - First-coating last-etching single package method for positively packaging double-sided graphic chip - Google Patents
First-coating last-etching single package method for positively packaging double-sided graphic chip Download PDFInfo
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- 238000005530 etching Methods 0.000 title claims abstract description 30
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- 238000000576 coating method Methods 0.000 title claims abstract description 16
- 238000004806 packaging method and process Methods 0.000 title abstract description 36
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- 239000003822 epoxy resin Substances 0.000 abstract description 33
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- 238000005538 encapsulation Methods 0.000 abstract description 13
- 238000009713 electroplating Methods 0.000 abstract description 11
- 238000010137 moulding (plastic) Methods 0.000 abstract 1
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
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- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract
本发明涉及一种双面图形芯片正装先镀后刻单颗封装方法,所述方法包括以下工艺步骤:取金属基板;金属基板进行金属层电镀被覆;金属基板进行背面蚀刻作业;金属基板背面进行包封无填料的塑封料(环氧树脂)作业;金属基板正面蚀刻作业;蚀刻出基岛和引脚的正面,且使所述基岛和引脚的背面尺寸小于基岛和引脚的正面尺寸,形成上大下小的基岛和引脚结构;装片;打金属线;半成品正面进行局部单元包封有填料塑封料(环氧树脂)作业,使引脚正面局部单元区域露出有填料塑封料(环氧树脂);岛和引脚的背面以及引脚的正面进行金属层电镀被覆;切割。本发明方法制备的芯片封装结构不会再有产生掉脚的问题和能使金属线的长度缩短。
The invention relates to a double-sided graphic chip packaging method firstly plated and then engraved for a single chip. The method comprises the following process steps: taking a metal substrate; performing metal layer electroplating coating on the metal substrate; performing back etching of the metal substrate; Encapsulation of filler-free molding compound (epoxy resin) operations; metal substrate front etching operations; etching out the front of the base island and pins, and making the size of the back of the base island and pins smaller than the front of the base island and pins Size, forming a base island and pin structure with a large top and a small bottom; loading chips; punching metal wires; the front of the semi-finished product is partially encapsulated with filler plastic molding compound (epoxy resin), so that the partial unit area on the front of the pin is exposed with filler Molding compound (epoxy resin); backside of islands and pins, and front side of pins with metal plating; cutting. The chip packaging structure prepared by the method of the invention will no longer have the problem of pin drop and can shorten the length of the metal wire.
Description
(一)技术领域 (1) Technical field
本发明涉及一种双面图形芯片正装先镀后刻单颗封装方法。属于半导体封装技术领域。The invention relates to a single packaging method for a double-sided graphics chip, which is first plated and then engraved. It belongs to the technical field of semiconductor packaging.
(二)背景技术 (2) Background technology
传统的芯片封装结构的制作方式是:采用金属基板的正面进行化学蚀刻及表面电镀层后,即完成引线框的制作(如图43所示)。而引线框的背面则在封装过程中再进行蚀刻。该法存在以下不足:The traditional manufacturing method of the chip package structure is: after chemical etching and surface electroplating are performed on the front side of the metal substrate, the production of the lead frame is completed (as shown in FIG. 43 ). The backside of the leadframe is etched during the packaging process. This law has the following shortcomings:
因为塑封前只在金属基板正面进行了半蚀刻工作,而在塑封过程中塑封料只有包裹住引脚半只脚的高度,所以塑封体与引脚的束缚能力就变小了,如果塑封体贴片到PCB板上不是很好时,再进行返工重贴,就容易产生掉脚的问题(如图44所示)。尤其塑封料的种类是采用有填料时候,因为材料在生产过程的环境与后续表面贴装的应力变化关系,会造成金属与塑封料产生垂直型的裂缝,其特性是填料比例越高则越硬越脆越容易产生裂缝。Because only half-etching work is done on the front of the metal substrate before plastic sealing, and the plastic sealing material is only half a foot high to cover the pins during the plastic sealing process, so the binding ability between the plastic package and the pins becomes smaller. If the plastic package is considerate When the chip is not well attached to the PCB board, rework and re-attachment will easily cause the problem of foot drop (as shown in Figure 44). Especially when the type of molding compound is filled, because the relationship between the environment of the material in the production process and the stress change of the subsequent surface mount will cause vertical cracks between the metal and the molding compound, the characteristic is that the higher the filler ratio, the harder it is The more brittle the easier it is to crack.
另外,由于芯片与引脚之间的距离较远,金属线的长度较长,如图45~46所示,金属线成本较高(尤其是昂贵的纯金质的金属线);同样由于金属线的长度较长,使得芯片的信号输出速度较慢(尤其是存储类的产品以及需要大量数据的计算,更为突出);也同样由于金属线的长度较长,所以在金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也较高;再由于芯片与引脚之间的距离较远,使得封装的体积与面积较大,材料成本较高,废弃物较多。In addition, due to the long distance between the chip and the pins, the length of the metal wire is relatively long, as shown in Figures 45-46, the cost of the metal wire is relatively high (especially the expensive pure gold metal wire); The length of the wire is longer, which makes the signal output speed of the chip slower (especially for storage products and calculations that require a large amount of data); The interference of parasitic resistance/capacitance and parasitic poles on the signal is also high; and because the distance between the chip and the pins is long, the volume and area of the package are large, the cost of materials is high, and there is more waste.
(三)发明内容 (3) Contents of the invention
本发明的目的在于克服上述不足,提供一种不会再有产生掉脚的问题和能使金属线的长度缩短的双面图形芯片正装先镀后刻单颗封装方法。The purpose of the present invention is to overcome the above-mentioned disadvantages, to provide a double-sided graphic chip packaging method that does not have the problem of missing feet and can shorten the length of the metal wire.
本发明的目的是这样实现的:一种双面图形芯片正装先镀后刻单颗封装方法,所述方法包括以下工艺步骤:The purpose of the present invention is achieved in this way: a double-sided graphics chip is mounted first and then engraved a single packaging method, said method comprising the following process steps:
步骤一、取金属基板
取一片厚度合适的金属基板,Take a piece of metal substrate with appropriate thickness,
步骤二、金属基板正面及背面被覆光阻胶膜
利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜,以保护后续的电镀金属层工艺作业,Use the coating equipment to cover the front and back of the metal substrate with photoresist film that can be exposed and developed to protect the subsequent electroplating metal layer process.
步骤三、金属基板正面的光阻胶膜进行需要电镀金属层区域的曝光/显影以及开窗Step 3: Expose/develop the photoresist film on the front of the metal substrate and open the window where the metal layer needs to be plated
利用曝光显影设备将步骤二完成光阻胶膜被覆作业的金属基板正面进行曝光显影去除部分光阻胶膜,以露出金属基板正面后续需要进行电镀金属层的区域,Use exposure and development equipment to expose and develop the front of the metal substrate that has completed the photoresist film coating operation in
步骤四、金属基板正面已开窗的区域进行金属层电镀被覆
对步骤三中金属基板正面已开窗的区域进行第一金属层电镀被覆,该第一金属层置于所述基岛与引脚的正面,The first metal layer is electroplated on the area where the window has been opened on the front of the metal substrate in
步骤五、金属基板正面及背面进行光阻胶膜去膜
将金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除,Remove the remaining photoresist film on the front of the metal substrate and the photoresist film on the back of the metal substrate.
步骤六、金属基板正面及背面被覆光阻胶膜
利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜,以保护后续的蚀刻工艺作业,Use the coating equipment to cover the front and back of the metal substrate with a photoresist film that can be exposed and developed to protect the subsequent etching process.
步骤七、金属基板背面的光阻胶膜进行需要蚀刻区域的曝光/显影以及开窗
利用曝光显影设备将步骤六完成光阻胶膜被覆作业的金属基板背面进行曝光显影去除部分光阻胶膜,以露出局部金属基板以备后续需要进行的金属基板背面蚀刻作业,Use exposure and development equipment to expose and develop the back of the metal substrate that has completed the photoresist film coating operation in
步骤八、金属基板进行背面蚀刻作业
完成步骤七的曝光/显影以及开窗作业后,即在金属基板的背面进行各图形的蚀刻作业,蚀刻出基岛和引脚的背面,同时将引脚正面尽可能的延伸到基岛旁边,After completing the exposure/development and window opening operations in
步骤九、金属基板正面及背面进行光阻胶膜去膜
将金属基板正面和背面余下的光阻胶膜全部揭除,Remove all the remaining photoresist film on the front and back of the metal substrate,
步骤十、包封无填料的塑封料(环氧树脂)
将已完成步骤九所述去膜作业的金属基板背面进行包封无填料的塑封料(环氧树脂)作业,并进行塑封料包封后的固化作业,使基岛和引脚外围的区域、引脚与基岛之间的区域以及引脚与引脚之间的区域均嵌置无填料的塑封料(环氧树脂),该无填料的塑封料(环氧树脂)将基岛和引脚下部外围、引脚下部与基岛下部以及引脚下部与引脚下部连接成一体,Carry out the operation of encapsulating the plastic compound (epoxy resin) without filler on the back of the metal substrate that has completed the film removal operation described in
步骤十一、被覆光阻胶膜
利用被覆设备在将已完成包封无填料塑封料作业的金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜,以保护后续的蚀刻工艺作业,Use the coating equipment to cover the front and back of the metal substrate that has completed the encapsulation of the non-filler molding compound with a photoresist film that can be exposed and developed to protect the subsequent etching process.
步骤十二、已完成包封无填料塑封料作业的金属基板的正面进行需要蚀刻区域的曝光/显影以及开窗Step 12: Expose/develop the area to be etched and open the window on the front side of the metal substrate that has completed the encapsulation of the non-filler molding compound
利用曝光显影设备将步骤十一完成光阻胶膜被覆作业的已完成包封无填料塑封料作业的金属基板正面进行曝光显影去除部分光阻胶膜,以备后续需要进行金属基板正面蚀刻作业,Use the exposure and development equipment to expose and develop the front side of the metal substrate that has completed the encapsulation of the non-filler plastic encapsulation operation in
步骤十三、金属基板正面蚀刻作业
完成步骤十二的曝光/显影以及开窗作业后,即在完成包封无填料塑封料作业的金属基板正面进行各图形的蚀刻作业,蚀刻出基岛和引脚的正面,且使所述基岛和引脚的背面尺寸小于基岛和引脚的正面尺寸,形成上大下小的基岛和引脚结构,After completing the exposure/development and window opening operation in
步骤十四、金属基板正面及背面进行光阻胶膜去膜
将完成步骤十三蚀刻作业的金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除,制成引线框,Remove the remaining photoresist film on the front of the metal substrate and the photoresist film on the back of the metal substrate after
步骤十五、装片Step fifteen, loading film
在基岛正面第一金属层上通过导电或不导电粘结物质进行芯片的植入,Chip implantation is carried out on the first metal layer on the front side of the base island through a conductive or non-conductive adhesive substance,
步骤十六、打金属线Step 16, hit the metal wire
将已完成芯片植入作业的半成品进行芯片正面与引脚正面第一金属层之间打金属线作业,The semi-finished product that has completed the chip implantation operation is put into the metal line operation between the front side of the chip and the first metal layer on the front side of the pin,
步骤十七、包封有填料塑封料(环氧树脂)Step 17. Encapsulate with filler molding compound (epoxy resin)
将已打线完成的半成品正面进行局部单元包封有填料塑封料(环氧树脂)作业,使引脚正面局部单元区域露出有填料塑封料(环氧树脂),并进行塑封料包封后的固化作业,使基岛和引脚的上部以及芯片和金属线外均被有填料塑封料(环氧树脂)包封,Partial unit encapsulation with filler molding compound (epoxy resin) on the front side of the semi-finished product that has been wired, so that the filler molding compound (epoxy resin) is exposed in the partial unit area on the front side of the pin, and the molding compound is encapsulated. Curing operation, so that the base island and the upper part of the pin, as well as the outside of the chip and the metal wire are encapsulated by a filler molding compound (epoxy resin),
步骤十八、基岛和引脚的背面以及引脚的正面进行金属层电镀被覆Step 18, the base island and the back of the pin and the front of the pin are electroplated with a metal layer
对已完成步骤十七包封有填料塑封料(环氧树脂)作业的所述基岛和引脚的背面以及步骤十七所述露出有填料塑封料(环氧树脂)的引脚正面局部单元区域分别进行第二金属层和第一金属层电镀被覆作业,For the back side of the base island and pins that have been encapsulated with filler molding compound (epoxy resin) in step 17 and the front part of the pins that are exposed with filler molding compound (epoxy resin) as described in step 17 The second metal layer and the first metal layer are respectively electroplated and coated in the area,
步骤十九、切割成品Step nineteen, cut the finished product
将已完成步骤十八第二金属层电镀被覆的半成品进行切割作业,使原本以列阵式集合体方式连在一起的芯片一颗颗独立开来,制得双面图形芯片正装单颗封装结构成品。Cutting the semi-finished product that has completed the electroplating and coating of the second metal layer in step 18, so that the chips that were originally connected together in the form of an array assembly are separated one by one, and a double-sided graphic chip is mounted on a single package structure finished product.
本发明的有益效果是:The beneficial effects of the present invention are:
1、确保不会再有产生掉脚的问题1. Ensure that there will be no more problems with feet falling
由于引线框采用了双面蚀刻的工艺技术,所以可以轻松的规划设计与制造出上大下小的引脚结构,可以使上下层塑封料紧密的将上大下小的引脚结构一起包裹住,所以塑封体与引脚的束缚能力就变大了,不会再有产生掉脚的问题。Since the lead frame adopts the double-sided etching process technology, it is easy to plan, design and manufacture the pin structure with large upper and lower pins, so that the upper and lower layers of plastic compound can tightly wrap the pin structure with large upper and lower pins. , so the binding ability between the plastic package and the pins becomes larger, and there will be no more problems of falling feet.
2、确保金属线的长度缩短2. Ensure that the length of the metal wire is shortened
1)由于应用了引线框背面与正面分开蚀刻的技术,所以能够将引线框正面的引脚尽可能的延伸到后续需装芯片的区域旁边,促使芯片与引脚距离大幅的缩短,如图2~图3,如此金属线的长度也缩短了,金属线的成本也可以大幅的降低(尤其是昂贵的纯金质的金属线);1) Due to the application of the technology of separate etching on the back and front of the lead frame, the pins on the front of the lead frame can be extended as far as possible to the side of the area where the chip needs to be installed later, which greatly shortens the distance between the chip and the pin, as shown in Figure 2 ~Figure 3, so the length of the metal wire is also shortened, and the cost of the metal wire can also be greatly reduced (especially the expensive pure gold metal wire);
2)也因为金属线的长度缩短使得芯片的信号输出速度也大幅的增速(尤其存储类的产品以及需要大量数据的计算,更为突出),由于金属线的长度变短了,所以金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也大幅度的降低。2) Also because the length of the metal wire is shortened, the signal output speed of the chip is also greatly increased (especially for storage products and calculations that require a large amount of data). The interference of the existing parasitic resistance/capacitance and parasitic poles to the signal is also greatly reduced.
3、使封装的体积与面积可以大幅度的缩小3. The volume and area of the package can be greatly reduced
因运用了引脚的延伸技术,所以可以容易的制作出高脚数与高密度的脚与脚之间的距离,使得封装的体积与面积可以大幅度的缩小。Due to the use of pin extension technology, it is easy to produce a high number of pins and a high-density pin-to-pin distance, so that the volume and area of the package can be greatly reduced.
4、材料成本和材料用量减少4. Reduced material cost and material consumption
因为将封装后的体积大幅度的缩小,更直接的体现出材料成本大幅度的下降与因为材料用量的减少也大幅度的减少废弃物环保的困扰。Because the volume after packaging is greatly reduced, it more directly reflects the substantial reduction in material costs and the reduction in the amount of materials used also greatly reduces the problem of waste and environmental protection.
5、采用局部單元的单颗封装的优点有:5. The advantages of using a single package of local units are:
1)在不同的应用中可以将塑封体边缘的引脚伸出塑封体。1) In different applications, the pins on the edge of the plastic package can be extended out of the plastic package.
2)塑封体边缘的引脚伸出塑封体外可以清楚的检查出焊接在PCB板上的情况。2) The pins on the edge of the plastic package extend out of the plastic package to clearly check the soldering on the PCB.
3)模块型的面积较大会容易因为多种不同的材料结构所产生收缩率不同的应立变形,而局部单元的单颗封装就可以完全分散多种不同的材料结构所产生收缩率不同的应立变形。3) The large area of the modular type will easily cause the deformation of the different shrinkage rates due to a variety of different material structures, and the single package of the local unit can completely disperse the different shrinkage rates of the different material structures. vertical deformation.
4)单颗封装在进行塑封体切割分离时,因为要切割的厚度只有引脚的厚度,所以切割的速度可以比模块型的封装结构要来得快很多,且切割用的刀片因为切割的厚度便薄了所以切割刀片的寿命相对的也就变的更长了。4) When a single package is cut and separated from the plastic package, because the thickness to be cut is only the thickness of the pin, the cutting speed can be much faster than that of the modular package structure, and the cutting blade is easy to cut because of the cutting thickness. It is thinner, so the life of the cutting blade is relatively longer.
(四)附图说明 (4) Description of drawings
图1(A)~图1(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例1各工序示意图。1(A) to 1(R) are schematic diagrams of each process in
图2为本发明双面图形芯片正装单颗封装结构实施例1结构示意图。Fig. 2 is a structural schematic diagram of
图3为图2的俯视图。FIG. 3 is a top view of FIG. 2 .
图4(A)~图4(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例2各工序示意图。4(A) to 4(R) are schematic diagrams of each process in
图5为本发明双面图形芯片正装单颗封装结构实施例2结构示意图。FIG. 5 is a structural schematic diagram of
图6为图5的俯视图。FIG. 6 is a top view of FIG. 5 .
图7(A)~图7(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例3各工序示意图。7(A) to 7(R) are schematic diagrams of each process in
图8为本发明双面图形芯片正装单颗封装结构实施例3结构示意图。FIG. 8 is a structural schematic diagram of
图9为图8的俯视图。FIG. 9 is a top view of FIG. 8 .
图10(A)~图10(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例4各工序示意图。10(A) to 10(R) are schematic diagrams of each process in
图11为本发明双面图形芯片正装单颗封装结构实施例4结构示意图。Fig. 11 is a structural schematic diagram of
图12为图11的俯视图。FIG. 12 is a top view of FIG. 11 .
图13(A)~图13(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例5各工序示意图。13(A) to 13(R) are schematic diagrams of each process in
图14为本发明双面图形芯片正装单颗封装结构实施例5结构示意图。Fig. 14 is a structural schematic diagram of
图15为图14的俯视图。FIG. 15 is a top view of FIG. 14 .
图16(A)~图16(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例6各工序示意图。16(A) to 16(R) are schematic diagrams of each process in
图17为本发明双面图形芯片正装单颗封装结构实施例6结构示意图。FIG. 17 is a schematic structural diagram of
图18为图17的俯视图。FIG. 18 is a top view of FIG. 17 .
图19(A)~图19(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例7各工序示意图。19(A) to 19(R) are schematic diagrams of each process in
图20为本发明双面图形芯片正装单颗封装结构实施例7结构示意图。FIG. 20 is a structural schematic diagram of
图21为图20的俯视图。FIG. 21 is a top view of FIG. 20 .
图22(A)~图22(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例8各工序示意图。22(A) to 22(R) are schematic diagrams of each process in
图23为本发明双面图形芯片正装单颗封装结构实施例8结构示意图。Fig. 23 is a structural schematic diagram of
图24为图23的俯视图。FIG. 24 is a top view of FIG. 23 .
图25(A)~图25(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例5各工序示意图。25(A) to 25(R) are schematic diagrams of each process in
图26为本发明双面图形芯片正装单颗封装结构实施例5结构示意图。Fig. 26 is a structural schematic diagram of
图27为图26的俯视图。FIG. 27 is a top view of FIG. 26 .
图28(A)~图28(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例6各工序示意图。28(A) to 28(R) are schematic diagrams of each process in
图29为本发明双面图形芯片正装单颗封装结构实施例6结构示意图。Fig. 29 is a structural schematic diagram of
图30为图29的俯视图。FIG. 30 is a top view of FIG. 29 .
图31(A)~图31(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例11各工序示意图。31(A) to 31(R) are schematic diagrams of each process in
图32为本发明双面图形芯片正装单颗封装结构实施例11结构示意图。Fig. 32 is a structural schematic diagram of
图33为图32的俯视图。FIG. 33 is a top view of FIG. 32 .
图34(A)~图34(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例12各工序示意图。34(A) to 34(R) are schematic diagrams of each process in
图35为本发明双面图形芯片正装单颗封装结构实施例12结构示意图。Fig. 35 is a structural schematic diagram of
图36为图35的俯视图。FIG. 36 is a top view of FIG. 35 .
图37(A)~图37(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例13各工序示意图。37(A) to 37(R) are schematic diagrams of each process in
图38为本发明双面图形芯片正装单颗封装结构实施例13结构示意图。Fig. 38 is a structural schematic diagram of
图39为图38的俯视图。FIG. 39 is a top view of FIG. 38 .
图40(A)~图40(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例14各工序示意图。40(A) to 40(R) are schematic diagrams of each process in
图41为本发明双面图形芯片正装单颗封装结构实施例14结构示意图。Fig. 41 is a structural schematic diagram of
图42为图41的俯视图。FIG. 42 is a top view of FIG. 41 .
图43为以往采用金属基板的正面进行化学蚀刻及表面电镀层作业图。Fig. 43 is a working diagram of chemical etching and surface electroplating on the front side of a metal substrate in the past.
图44为以往形成的掉脚图。Fig. 44 is a diagram of a footfall formed in the past.
图45为以往的封装结构示意图。Fig. 45 is a schematic diagram of a conventional package structure.
图46为45的俯视图。FIG. 46 is a top view of 45 .
图中附图标记:Reference signs in the figure:
基岛1、引脚2、无填料的塑封料(环氧树脂))3、第一金属层4、第二金属层5、导电或不导电粘结物质6、芯片7、金属线8、有填料塑封料(环氧树脂)9、金属基板10、光阻胶膜11、光阻胶膜12、光阻胶膜13、光阻胶膜14、光阻胶膜15、光阻胶膜16;
第三基岛1.1、第三基岛1.2、第三基岛1.3、第四基岛1.4。The third base island 1.1, the third base island 1.2, the third base island 1.3, and the fourth base island 1.4.
(五)具体实施方式 (5) Specific implementation methods
本发明双面图形芯片正装先镀后刻单颗封装方法如下:The double-sided graphics chip of the present invention is mounted first and then engraved with a single packaging method as follows:
实施例1:单基岛单圈引脚Example 1: Single base island single turn pin
参见图2和图3,图2为本发明双面图形芯片正装单颗封装结构实施例1结构示意图。图3为图2的俯视图。由图2和图3可以看出,本发明双面图形芯片正装单颗封装结构,包括基岛1、引脚2、无填料的塑封料(环氧树脂)3、导电或不导电粘结物质6、芯片7、金属线8和有填料塑封料(环氧树脂)9,所述引脚2正面尽可能的延伸到基岛1旁边,在所述基岛1和引脚2的正面设置有第一金属层4,在所述基岛1和引脚2的背面设置有第二金属层5,在所述基岛1正面第一金属层4上通过导电或不导电粘结物质6设置有芯片7,芯片7正面与引脚2正面第一金属层4之间用金属线8连接,在所述基岛1和引脚2的上部以及芯片7和金属线8外包封有填料塑封料(环氧树脂)9,该有填料塑封料(环氧树脂)9将引脚2正面局部单元进行包覆,在所述基岛1和引脚2外围的区域、引脚2与基岛1之间的区域以及引脚2与引脚2之间的区域嵌置有无填料的塑封料(环氧树脂)3,所述无填料的塑封料(环氧树脂)3将基岛1和引脚下部外围、引脚2下部与基岛1下部以及引脚2下部与引脚2下部连接成一体,且使所述基岛和引脚背面尺寸小于基岛和引脚正面尺寸,形成上大下小的基岛和引脚结构。Referring to FIG. 2 and FIG. 3 , FIG. 2 is a structural schematic diagram of
其封装方法如下:Its packaging method is as follows:
步骤一、取金属基板
参见图1(A),取一片厚度合适的金属基板10。金属基板的材质可以依据芯片的功能与特性进行变换,例如:铜、铝、铁、铜合金或镍铁合金等。Referring to FIG. 1(A), take a
步骤二、金属基板正面及背面被覆光阻胶膜
参见图1(B),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜11和12,以保护后续的电镀金属层工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(B), the front and back sides of the metal substrate are coated with
步骤三、金属基板正面的光阻胶膜进行需要电镀金属层区域的曝光/显影以及开窗Step 3: Expose/develop the photoresist film on the front of the metal substrate and open the window where the metal layer needs to be plated
参见图1(C),利用曝光显影设备将步骤二完成光阻胶膜被覆作业的金属基板正面进行曝光显影去除部分光阻胶膜,以露出金属基板正面后续需要进行电镀金属层的区域。Referring to FIG. 1(C), use exposure and development equipment to expose and develop the front of the metal substrate that has completed the photoresist film coating operation in
步骤四、金属基板正面已开窗的区域进行金属层电镀被覆
参见图1(D),对步骤三中金属基板正面已开窗的区域进行第一金属层4电镀被覆,该第一金属层4置于所述基岛1与引脚2的正面。Referring to FIG. 1(D), the
步骤五、金属基板正面及背面进行光阻胶膜去膜
参见图1(E),将金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除。Referring to FIG. 1(E), remove the remaining photoresist film on the front side of the metal substrate and the photoresist film on the back side of the metal substrate.
步骤六、金属基板正面及背面被覆光阻胶膜
参见图1(F),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜13和14,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(F), the front and back sides of the metal substrate are coated with
步骤七、金属基板背面的光阻胶膜进行需要蚀刻区域的曝光/显影以及开窗
参见图1(G),利用曝光显影设备将步骤六完成光阻胶膜被覆作业的金属基板背面进行曝光显影去除部分光阻胶膜,以露出局部金属基板以备后续需要进行的金属基板背面蚀刻作业。Referring to Figure 1(G), use the exposure and development equipment to expose and develop the back of the metal substrate that has completed the photoresist film coating operation in
步骤八、金属基板进行背面蚀刻作业
参见图1(H),完成步骤七的曝光/显影以及开窗作业后,即在金属基板的背面进行各图形的蚀刻作业,蚀刻出基岛1和引脚2的背面,同时将引脚正面尽可能的延伸到基岛旁边。Referring to Figure 1(H), after completing the exposure/development and window opening operations in
步骤九、金属基板正面及背面进行光阻胶膜去膜
参见图1(I),将金属基板正面和背面余下的光阻胶膜全部揭除。Referring to FIG. 1(I), the remaining photoresist films on the front and back of the metal substrate are all removed.
步骤十、包封无填料的塑封料(环氧树脂)
参见图1(J),将已完成步骤九所述去膜作业的金属基板背面进行包封无填料的塑封料(环氧树脂)作业,并进行塑封料包封后的固化作业,使基岛1和引脚2外围的区域、引脚2与基岛1之间的区域以及引脚2与引脚2之间的区域均嵌置无填料的塑封料(环氧树脂)3,该无填料的塑封料(环氧树脂)3将基岛1和引脚下部外围、引脚2下部与基岛1下部以及引脚2下部与引脚2下部连接成一体。Referring to Figure 1(J), the back of the metal substrate that has completed the film removal operation described in
步骤十一、被覆光阻胶膜
参见图1(K),利用被覆设备在将已完成包封无填料塑封料作业的金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜15和16,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to Fig. 1(K), use the coating equipment to coat the front and back of the metal substrate that has completed the encapsulation of the filler-free molding compound with photoresist films 15 and 16 that can be exposed and developed, so as to protect the subsequent etching process. . The photoresist film can be a dry photoresist thin film or a wet photoresist film.
步骤十二、已完成包封无填料塑封料作业的金属基板的正面进行需要蚀刻区域的曝光/显影以及开窗Step 12: Expose/develop the area to be etched and open the window on the front side of the metal substrate that has completed the encapsulation of the non-filler molding compound
参见图1(L),利用曝光显影设备将步骤十一完成光阻胶膜被覆作业的已完成包封无填料塑封料作业的金属基板正面进行曝光显影去除部分光阻胶膜,以备后续需要进行金属基板正面蚀刻作业。Referring to Figure 1(L), use the exposure and development equipment to expose and develop the front side of the metal substrate that has completed the encapsulation and non-filler molding compound operation in
步骤十三、金属基板正面蚀刻作业
参见图1(M),完成步骤十二的曝光/显影以及开窗作业后,即在完成包封无填料塑封料作业的金属基板正面进行各图形的蚀刻作业,蚀刻出基岛1和引脚2的正面,且使所述基岛1和引脚2的背面尺寸小于基岛1和引脚2的正面尺寸,形成上大下小的基岛1和引脚2结构。Referring to Figure 1(M), after completing the exposure/development and window opening operations in
步骤十四、金属基板正面及背面进行光阻胶膜去膜
参见图1(N),将完成步骤十三蚀刻作业的金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除,制成引线框。Referring to FIG. 1(N), the remaining photoresist film on the front side of the metal substrate and the photoresist film on the back side of the metal substrate after
步骤十五、装片Step 15, loading film
参见图1(O),在基岛1正面第一金属层4上通过导电或不导电粘结物质6进行芯片7的植入。Referring to FIG. 1(O), the
步骤十六、打金属线Step 16, hit the metal wire
参见图1(P),将已完成芯片植入作业的半成品进行芯片正面与引脚正面第一金属层之间打金属线8作业。Referring to FIG. 1(P), the semi-finished product that has completed the chip implantation operation is put into
步骤十七、包封有填料塑封料(环氧树脂)Step 17. Encapsulate with filler molding compound (epoxy resin)
参见图1(Q),将已打线完成的半成品正面进行局部单元包封有填料塑封料9作业,使引脚2正面局部单元区域露出有填料塑封料(环氧树脂)9,并进行塑封料包封后的固化作业,使基岛和引脚的上部以及芯片和金属线外均被有填料塑封料(环氧树脂)包封。Referring to Figure 1(Q), the front side of the semi-finished product that has been wired is partially encapsulated with
步骤十八、基岛和引脚的背面以及引脚的正面进行金属层电镀被覆Step 18, the base island and the back of the pin and the front of the pin are electroplated with a metal layer
参见图1(R),对已完成步骤十七包封有填料塑封料(环氧树脂)作业的所述基岛和引脚的背面以及步骤十七所述露出有填料塑封料(环氧树脂)9的引脚2正面局部单元区域分别进行第二金属层5和第一金属层4电镀被覆作业,而电镀的材料可以是锡、镍金、镍钯金....等金属材质。Referring to Fig. 1 (R), the back side of the base island and pins that have completed step 17 encapsulation with filler molding compound (epoxy resin) and the exposed filler molding compound (epoxy resin) described in step 17 ) The partial unit area on the front side of the
步骤十九、切割成品Step nineteen, cut the finished product
参见图2和图3,将已完成步骤十八第二金属层电镀被覆的半成品进行切割作业,使原本以列阵式集合体方式连在一起的芯片一颗颗独立开来,制得双面图形芯片正装单颗封装结构成品。Referring to Figure 2 and Figure 3, the semi-finished product that has completed the electroplating and coating of the second metal layer in step 18 is cut, so that the chips that were originally connected together in the form of an array assembly are separated one by one to obtain a double-sided The graphics chip is being installed in a single package structure.
实施例2:下沉基岛露出型单圈引脚Embodiment 2: sunken base island exposed type single-turn pin
参见图4~6,图4(A)~图4(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例2各工序示意图。图5为本发明双面图形芯片正装单颗封装结构实施例2结构示意图。图6为图5的俯视图。由图4、图5和图6可以看出,实施例2与实施例1的不同之处仅在于:所述基岛1为下沉型基岛,即基岛1正面中央区域下沉。Referring to Figures 4 to 6, Figures 4(A) to 4(R) are schematic diagrams of each process in
实施例3:埋入型基岛单圈引脚Embodiment 3: Embedded base island single-turn pin
参见图7~9,图7(A)~图7(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例3各工序示意图。图8为本发明双面图形芯片正装单颗封装结构实施例3结构示意图。图9为图8的俯视图。由图7、图8和图9可以看出,实施例3与实施例1的不同之处仅在于:所述基岛1为埋入型基岛,即基岛1背面埋入所述无填料的塑封料(环氧树脂)3内。Referring to Figures 7 to 9, Figures 7(A) to 7(R) are schematic diagrams of each process in
实施例4:多凸点基岛露出型单圈引脚Embodiment 4: Multi-bump base island exposed single-turn pin
参见图10~12,图10(A)~图10(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例4各工序示意图。图11为本发明双面图形芯片正装单颗封装结构实施例4结构示意图。图12为图11的俯视图。由图10、图11和图12可以看出,实施例4与实施例1的不同之处仅在于:所述基岛1为多凸点基岛,即基岛1表面设置有多个凸点。Referring to Figures 10-12, Figures 10(A)-10(R) are schematic diagrams of each process in
实施例5:多个基岛露出型单圈引脚Embodiment 5: Multiple base island exposed single-turn pins
参见图13~15,图13(A)~图13(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例5各工序示意图。图14为本发明双面图形芯片正装单颗封装结构实施例5结构示意图。图15为图14的俯视图。由图13~15可以看出,实施例5与实施例1的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 13-15, Figures 13(A)-13(R) are schematic diagrams of each process in
实施例6:多个下沉基岛露出型单圈引脚Embodiment 6: Multiple sunken base island exposed single-turn pins
参见图16~18,图16(A)~图16(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例6各工序示意图。图17为本发明双面图形芯片正装单颗封装结构实施例6结构示意图。图18为图17的俯视图。由图16~18可以看出,实施例6与实施例2的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 16-18, Figures 16(A)-16(R) are schematic diagrams of each process in
实施例7:多个埋入型基岛单圈引脚Example 7: Multiple Buried Base Island Single Turn Pins
参见图19~21,图19(A)~图19(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例7各工序示意图。图20为本发明双面图形芯片正装单颗封装结构实施例7结构示意图。图21为图20的俯视图。由图19~21可以看出,实施例7与实施例3的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 19-21, Figures 19(A)-19(R) are schematic diagrams of each process in
实施例8:多个多凸点基岛露出型单圈引脚Embodiment 8: Multiple multi-bump base island exposed single-turn pins
参见图22~24,图22(A)~图22(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例8各工序示意图。图23为本发明双面图形芯片正装单颗封装结构实施例8结构示意图。图24为图23的俯视图。由图22~24可以看出,实施例8与实施例4的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 22-24, Figures 22(A)-22(R) are schematic diagrams of each process in
实施例9:基岛露出型及下沉基岛露出型单圈引脚Embodiment 9: base island exposed type and sunken base island exposed type single-turn pin
参见图25~27,图25(A)~图25(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例9各工序示意图。图26为本发明双面图形芯片正装单颗封装结构实施例9结构示意图。图27为图26的俯视图。由图25~27可以看出,实施例9与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第二基岛1.2,所述第二基岛1.2正面中央区域下沉,在所述第一基岛1.1和引脚2的正面设置第一金属层4,在所述第一基岛1.1、第二基岛1.2和引脚2的背面设置第二金属层5,在第二基岛1.2正面中央下沉区域和第一基岛1.1正面通过导电或不导电粘结物质6设置芯片7,芯片7正面与引脚2正面第一金属层4之间以及芯片7与芯片7之间均用金属线8连接,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第一基岛1.1与第二基岛1.2之间的区域、第二基岛1.2与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第一基岛1.1下部、第一基岛1.1与第二基岛1.2下部、第二基岛1.2与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2有单圈。Referring to Fig. 25-27, Fig. 25(A)-Fig. 25(R) are schematic diagrams of each process in
实施例10:基岛露出型及埋入型基岛单圈引脚Embodiment 10: base island exposed type and embedded type base island single-turn pin
参见图28~30,图28(A)~图28(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例10各工序示意图。图29为本发明双面图形芯片正装单颗封装结构实施例10结构示意图。图30为图29的俯视图。由图28~30可以看出,实施例10与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第三基岛1.3,在所述第一基岛1.1第三基岛1.3和引脚2的正面设置第一金属层4,在所述第一基岛1.1和引脚2的背面设置第二金属层5,芯片7正面与引脚2正面第一金属层4之间以及芯片7与芯片7之间均用金属线8连接,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第三基岛1.3背面、第三基岛1.3与第一基岛1.1之间的区域、第三基岛1.3与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第一基岛1.1下部、第三基岛1.3背面、第三基岛1.3背面与第一基岛1.1下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有单圈。Referring to Figures 28-30, Figures 28(A)-28(R) are schematic diagrams of each process in
实施例11:基岛露出型及多凸点基岛露出型单圈引脚Embodiment 11: base island exposed type and multi-bump base island exposed type single-turn pin
参见图31~33,图31(A)~图31(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例11各工序示意图。图32为本发明双面图形芯片正装单颗封装结构实施例11结构示意图。图33为图32的俯视图。由图31~33可以看出,实施例11与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第四基岛1.4,所述第四基岛1.4正面设置成多凸点状结构,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第一基岛1.1与第四基岛1.4之间的区域、第四基岛1.4与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料的塑封料(环氧树脂)3将引脚下部外围、引脚2与第一基岛1.1下部、第一基岛1.1与第四基岛1.4下部、第四基岛1.4与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有单圈。Referring to Figures 31-33, Figures 31(A)-31(R) are schematic diagrams of each process in
实施例12:下沉基岛露出型及埋入型基岛露出型单圈引脚Embodiment 12: Sunken base island exposed type and buried base island exposed type single-turn pin
参见图34~36,图34(A)~图34(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例12各工序示意图。图35为本发明双面图形芯片正装单颗封装结构实施例12结构示意图。图36为图35的俯视图。由图34~36可以看出,实施例12与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第二基岛1.2,另一组为第三基岛1.3,所述第二基岛1.2正面中央区域下沉,在第二基岛1.2正面中央下沉区域和第三基岛1.3正面通过导电或不导电粘结物质6设置芯片7,在所述引脚2外围的区域、引脚2与第二基岛1.2之间的区域、第三基岛1.3背面、第二基岛背面1.2与第二基岛1.2之间的区域、第三基岛1.3背面与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第二基岛1.2下部、第三基岛1.3、第三基岛1.3与第二基岛1.2下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 34 to 36, Figures 34(A) to 34(R) are schematic diagrams of each process in
实施例13:下沉基岛露出型及多凸点基岛露出型单圈引脚Embodiment 13: Sunken base island exposed type and multi-bump base island exposed type single-turn pin
参见图37~39,图37(A)~图37(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例13各工序示意图。图38为本发明双面图形芯片正装单颗封装结构实施例13结构示意图。图39为图38的俯视图。由图37~39可以看出,实施例13与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第二基岛1.2,另一组为第四基岛1.4,所述第二基岛1.2正面中央区域下沉,第四基岛1.4正面设置成多凸点状结构,在所述第四基岛1.4和引脚2的正面设置第一金属层4,在所述第二基岛1.2、第四基岛1.4和引脚2的背面设置第二金属层5,在所述第二基岛1.2正面中央下沉区域和第四基岛1.4正面通过导电或不导电粘结物质6设置芯片7,在所述引脚2外围的区域、引脚2与第二基岛1.2之间的区域、第二基岛1.2与第四基岛1.4之间的区域、第四基岛1.4与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料的塑封料(环氧树脂)3将引脚下部外围、引脚2与第二基岛1.2下部、第二基岛1.2与第四基岛1.4下部、第四基岛1.4与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 37 to 39, Figures 37(A) to 37(R) are schematic diagrams of each process in
实施例14:埋入型基岛及多凸点基岛露出型单圈引脚Embodiment 14: Embedded base island and multi-bump base island exposed single-turn pin
参见图40~42,图40(A)~图40(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例14各工序示意图。41为本发明双面图形芯片正装单颗封装结构实施例14结构示意图。图42为41的俯视图。由图40~42可以看出,实施例14与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第三基岛1.3,另一组为第四基岛1.4,所述第四基岛1.4正面设置成多凸点状结构,在所述第三基岛1.3、第四基岛1.4和引脚2的正面设置第一金属层4,在所述第四基岛1.4和引脚2的背面设置第二金属层5,在所述引脚2外围的区域、引脚2与第四基岛1.4之间的区域、第三基岛1.3背面、第二基岛1.2与第四基岛1.4之间的区域、第三基岛1.3与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第四基岛1.4下部、第三基岛1.3背面、第三基岛1.3背面与第四基岛1.4下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 40-42, Figures 40(A)-40(R) are schematic diagrams of each process in
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