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CN101950726B - First-coating last-etching single package method for positively packaging double-sided graphic chip - Google Patents

First-coating last-etching single package method for positively packaging double-sided graphic chip Download PDF

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CN101950726B
CN101950726B CN2010102730015A CN201010273001A CN101950726B CN 101950726 B CN101950726 B CN 101950726B CN 2010102730015 A CN2010102730015 A CN 2010102730015A CN 201010273001 A CN201010273001 A CN 201010273001A CN 101950726 B CN101950726 B CN 101950726B
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pin
dao
metal substrate
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back side
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CN101950726A (en
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王新潮
梁志忠
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

本发明涉及一种双面图形芯片正装先镀后刻单颗封装方法,所述方法包括以下工艺步骤:取金属基板;金属基板进行金属层电镀被覆;金属基板进行背面蚀刻作业;金属基板背面进行包封无填料的塑封料(环氧树脂)作业;金属基板正面蚀刻作业;蚀刻出基岛和引脚的正面,且使所述基岛和引脚的背面尺寸小于基岛和引脚的正面尺寸,形成上大下小的基岛和引脚结构;装片;打金属线;半成品正面进行局部单元包封有填料塑封料(环氧树脂)作业,使引脚正面局部单元区域露出有填料塑封料(环氧树脂);岛和引脚的背面以及引脚的正面进行金属层电镀被覆;切割。本发明方法制备的芯片封装结构不会再有产生掉脚的问题和能使金属线的长度缩短。

The invention relates to a double-sided graphic chip packaging method firstly plated and then engraved for a single chip. The method comprises the following process steps: taking a metal substrate; performing metal layer electroplating coating on the metal substrate; performing back etching of the metal substrate; Encapsulation of filler-free molding compound (epoxy resin) operations; metal substrate front etching operations; etching out the front of the base island and pins, and making the size of the back of the base island and pins smaller than the front of the base island and pins Size, forming a base island and pin structure with a large top and a small bottom; loading chips; punching metal wires; the front of the semi-finished product is partially encapsulated with filler plastic molding compound (epoxy resin), so that the partial unit area on the front of the pin is exposed with filler Molding compound (epoxy resin); backside of islands and pins, and front side of pins with metal plating; cutting. The chip packaging structure prepared by the method of the invention will no longer have the problem of pin drop and can shorten the length of the metal wire.

Description

双面图形芯片正装先镀后刻单颗封装方法Double-sided graphics chip front-mounting first plating and engraving single-chip packaging method

(一)技术领域 (1) Technical field

本发明涉及一种双面图形芯片正装先镀后刻单颗封装方法。属于半导体封装技术领域。The invention relates to a single packaging method for a double-sided graphics chip, which is first plated and then engraved. It belongs to the technical field of semiconductor packaging.

(二)背景技术 (2) Background technology

传统的芯片封装结构的制作方式是:采用金属基板的正面进行化学蚀刻及表面电镀层后,即完成引线框的制作(如图43所示)。而引线框的背面则在封装过程中再进行蚀刻。该法存在以下不足:The traditional manufacturing method of the chip package structure is: after chemical etching and surface electroplating are performed on the front side of the metal substrate, the production of the lead frame is completed (as shown in FIG. 43 ). The backside of the leadframe is etched during the packaging process. This law has the following shortcomings:

因为塑封前只在金属基板正面进行了半蚀刻工作,而在塑封过程中塑封料只有包裹住引脚半只脚的高度,所以塑封体与引脚的束缚能力就变小了,如果塑封体贴片到PCB板上不是很好时,再进行返工重贴,就容易产生掉脚的问题(如图44所示)。尤其塑封料的种类是采用有填料时候,因为材料在生产过程的环境与后续表面贴装的应力变化关系,会造成金属与塑封料产生垂直型的裂缝,其特性是填料比例越高则越硬越脆越容易产生裂缝。Because only half-etching work is done on the front of the metal substrate before plastic sealing, and the plastic sealing material is only half a foot high to cover the pins during the plastic sealing process, so the binding ability between the plastic package and the pins becomes smaller. If the plastic package is considerate When the chip is not well attached to the PCB board, rework and re-attachment will easily cause the problem of foot drop (as shown in Figure 44). Especially when the type of molding compound is filled, because the relationship between the environment of the material in the production process and the stress change of the subsequent surface mount will cause vertical cracks between the metal and the molding compound, the characteristic is that the higher the filler ratio, the harder it is The more brittle the easier it is to crack.

另外,由于芯片与引脚之间的距离较远,金属线的长度较长,如图45~46所示,金属线成本较高(尤其是昂贵的纯金质的金属线);同样由于金属线的长度较长,使得芯片的信号输出速度较慢(尤其是存储类的产品以及需要大量数据的计算,更为突出);也同样由于金属线的长度较长,所以在金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也较高;再由于芯片与引脚之间的距离较远,使得封装的体积与面积较大,材料成本较高,废弃物较多。In addition, due to the long distance between the chip and the pins, the length of the metal wire is relatively long, as shown in Figures 45-46, the cost of the metal wire is relatively high (especially the expensive pure gold metal wire); The length of the wire is longer, which makes the signal output speed of the chip slower (especially for storage products and calculations that require a large amount of data); The interference of parasitic resistance/capacitance and parasitic poles on the signal is also high; and because the distance between the chip and the pins is long, the volume and area of the package are large, the cost of materials is high, and there is more waste.

(三)发明内容 (3) Contents of the invention

本发明的目的在于克服上述不足,提供一种不会再有产生掉脚的问题和能使金属线的长度缩短的双面图形芯片正装先镀后刻单颗封装方法。The purpose of the present invention is to overcome the above-mentioned disadvantages, to provide a double-sided graphic chip packaging method that does not have the problem of missing feet and can shorten the length of the metal wire.

本发明的目的是这样实现的:一种双面图形芯片正装先镀后刻单颗封装方法,所述方法包括以下工艺步骤:The purpose of the present invention is achieved in this way: a double-sided graphics chip is mounted first and then engraved a single packaging method, said method comprising the following process steps:

步骤一、取金属基板Step 1. Take the metal substrate

取一片厚度合适的金属基板,Take a piece of metal substrate with appropriate thickness,

步骤二、金属基板正面及背面被覆光阻胶膜Step 2. The front and back of the metal substrate are coated with photoresist film

利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜,以保护后续的电镀金属层工艺作业,Use the coating equipment to cover the front and back of the metal substrate with photoresist film that can be exposed and developed to protect the subsequent electroplating metal layer process.

步骤三、金属基板正面的光阻胶膜进行需要电镀金属层区域的曝光/显影以及开窗Step 3: Expose/develop the photoresist film on the front of the metal substrate and open the window where the metal layer needs to be plated

利用曝光显影设备将步骤二完成光阻胶膜被覆作业的金属基板正面进行曝光显影去除部分光阻胶膜,以露出金属基板正面后续需要进行电镀金属层的区域,Use exposure and development equipment to expose and develop the front of the metal substrate that has completed the photoresist film coating operation in step 2 to remove part of the photoresist film to expose the area that needs to be electroplated on the front of the metal substrate.

步骤四、金属基板正面已开窗的区域进行金属层电镀被覆Step 4. Electroplating and coating the metal layer on the windowed area on the front of the metal substrate

对步骤三中金属基板正面已开窗的区域进行第一金属层电镀被覆,该第一金属层置于所述基岛与引脚的正面,The first metal layer is electroplated on the area where the window has been opened on the front of the metal substrate in step 3, and the first metal layer is placed on the front of the base island and the pin,

步骤五、金属基板正面及背面进行光阻胶膜去膜Step 5. Remove the photoresist film on the front and back of the metal substrate

将金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除,Remove the remaining photoresist film on the front of the metal substrate and the photoresist film on the back of the metal substrate.

步骤六、金属基板正面及背面被覆光阻胶膜Step 6. Cover the front and back of the metal substrate with photoresist film

利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜,以保护后续的蚀刻工艺作业,Use the coating equipment to cover the front and back of the metal substrate with a photoresist film that can be exposed and developed to protect the subsequent etching process.

步骤七、金属基板背面的光阻胶膜进行需要蚀刻区域的曝光/显影以及开窗Step 7. Expose/develop the photoresist film on the back of the metal substrate and open the window for the area to be etched

利用曝光显影设备将步骤六完成光阻胶膜被覆作业的金属基板背面进行曝光显影去除部分光阻胶膜,以露出局部金属基板以备后续需要进行的金属基板背面蚀刻作业,Use exposure and development equipment to expose and develop the back of the metal substrate that has completed the photoresist film coating operation in step 6 to remove part of the photoresist film, so as to expose a part of the metal substrate for the subsequent metal substrate backside etching operation,

步骤八、金属基板进行背面蚀刻作业Step 8. Etching the back of the metal substrate

完成步骤七的曝光/显影以及开窗作业后,即在金属基板的背面进行各图形的蚀刻作业,蚀刻出基岛和引脚的背面,同时将引脚正面尽可能的延伸到基岛旁边,After completing the exposure/development and window opening operations in step 7, the etching operation of each pattern is performed on the back of the metal substrate to etch the base island and the back of the pins, and at the same time, the front of the pins is extended to the side of the base island as much as possible.

步骤九、金属基板正面及背面进行光阻胶膜去膜Step 9. Remove the photoresist film on the front and back of the metal substrate

将金属基板正面和背面余下的光阻胶膜全部揭除,Remove all the remaining photoresist film on the front and back of the metal substrate,

步骤十、包封无填料的塑封料(环氧树脂)Step 10. Encapsulate the plastic compound (epoxy resin) without filler

将已完成步骤九所述去膜作业的金属基板背面进行包封无填料的塑封料(环氧树脂)作业,并进行塑封料包封后的固化作业,使基岛和引脚外围的区域、引脚与基岛之间的区域以及引脚与引脚之间的区域均嵌置无填料的塑封料(环氧树脂),该无填料的塑封料(环氧树脂)将基岛和引脚下部外围、引脚下部与基岛下部以及引脚下部与引脚下部连接成一体,Carry out the operation of encapsulating the plastic compound (epoxy resin) without filler on the back of the metal substrate that has completed the film removal operation described in step 9, and perform the curing operation after encapsulation of the plastic compound, so that the area around the base island and the pin, The area between the lead and the base island and the area between the lead and the lead are embedded with a filler-free molding compound (epoxy resin), and the filler-free molding compound (epoxy resin) connects the base island and the lead The periphery of the lower part, the lower part of the pin and the lower part of the base island, and the lower part of the pin and the lower part of the pin are connected into one body,

步骤十一、被覆光阻胶膜Step 11. Coating photoresist film

利用被覆设备在将已完成包封无填料塑封料作业的金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜,以保护后续的蚀刻工艺作业,Use the coating equipment to cover the front and back of the metal substrate that has completed the encapsulation of the non-filler molding compound with a photoresist film that can be exposed and developed to protect the subsequent etching process.

步骤十二、已完成包封无填料塑封料作业的金属基板的正面进行需要蚀刻区域的曝光/显影以及开窗Step 12: Expose/develop the area to be etched and open the window on the front side of the metal substrate that has completed the encapsulation of the non-filler molding compound

利用曝光显影设备将步骤十一完成光阻胶膜被覆作业的已完成包封无填料塑封料作业的金属基板正面进行曝光显影去除部分光阻胶膜,以备后续需要进行金属基板正面蚀刻作业,Use the exposure and development equipment to expose and develop the front side of the metal substrate that has completed the encapsulation of the non-filler plastic encapsulation operation in step 11 to remove part of the photoresist film, in preparation for the subsequent etching of the front side of the metal substrate.

步骤十三、金属基板正面蚀刻作业Step 13. Etching the front side of the metal substrate

完成步骤十二的曝光/显影以及开窗作业后,即在完成包封无填料塑封料作业的金属基板正面进行各图形的蚀刻作业,蚀刻出基岛和引脚的正面,且使所述基岛和引脚的背面尺寸小于基岛和引脚的正面尺寸,形成上大下小的基岛和引脚结构,After completing the exposure/development and window opening operation in step 12, the etching operation of each pattern is carried out on the front of the metal substrate that has completed the operation of encapsulating the non-filler plastic encapsulant, and the front of the base island and the pin is etched out, and the base is made The size of the back side of the island and pins is smaller than the front size of the base island and pins, forming a base island and pin structure with a large top and a small bottom,

步骤十四、金属基板正面及背面进行光阻胶膜去膜Step 14. Remove the photoresist film on the front and back of the metal substrate

将完成步骤十三蚀刻作业的金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除,制成引线框,Remove the remaining photoresist film on the front of the metal substrate and the photoresist film on the back of the metal substrate after step 13 etching to form a lead frame.

步骤十五、装片Step fifteen, loading film

在基岛正面第一金属层上通过导电或不导电粘结物质进行芯片的植入,Chip implantation is carried out on the first metal layer on the front side of the base island through a conductive or non-conductive adhesive substance,

步骤十六、打金属线Step 16, hit the metal wire

将已完成芯片植入作业的半成品进行芯片正面与引脚正面第一金属层之间打金属线作业,The semi-finished product that has completed the chip implantation operation is put into the metal line operation between the front side of the chip and the first metal layer on the front side of the pin,

步骤十七、包封有填料塑封料(环氧树脂)Step 17. Encapsulate with filler molding compound (epoxy resin)

将已打线完成的半成品正面进行局部单元包封有填料塑封料(环氧树脂)作业,使引脚正面局部单元区域露出有填料塑封料(环氧树脂),并进行塑封料包封后的固化作业,使基岛和引脚的上部以及芯片和金属线外均被有填料塑封料(环氧树脂)包封,Partial unit encapsulation with filler molding compound (epoxy resin) on the front side of the semi-finished product that has been wired, so that the filler molding compound (epoxy resin) is exposed in the partial unit area on the front side of the pin, and the molding compound is encapsulated. Curing operation, so that the base island and the upper part of the pin, as well as the outside of the chip and the metal wire are encapsulated by a filler molding compound (epoxy resin),

步骤十八、基岛和引脚的背面以及引脚的正面进行金属层电镀被覆Step 18, the base island and the back of the pin and the front of the pin are electroplated with a metal layer

对已完成步骤十七包封有填料塑封料(环氧树脂)作业的所述基岛和引脚的背面以及步骤十七所述露出有填料塑封料(环氧树脂)的引脚正面局部单元区域分别进行第二金属层和第一金属层电镀被覆作业,For the back side of the base island and pins that have been encapsulated with filler molding compound (epoxy resin) in step 17 and the front part of the pins that are exposed with filler molding compound (epoxy resin) as described in step 17 The second metal layer and the first metal layer are respectively electroplated and coated in the area,

步骤十九、切割成品Step nineteen, cut the finished product

将已完成步骤十八第二金属层电镀被覆的半成品进行切割作业,使原本以列阵式集合体方式连在一起的芯片一颗颗独立开来,制得双面图形芯片正装单颗封装结构成品。Cutting the semi-finished product that has completed the electroplating and coating of the second metal layer in step 18, so that the chips that were originally connected together in the form of an array assembly are separated one by one, and a double-sided graphic chip is mounted on a single package structure finished product.

本发明的有益效果是:The beneficial effects of the present invention are:

1、确保不会再有产生掉脚的问题1. Ensure that there will be no more problems with feet falling

由于引线框采用了双面蚀刻的工艺技术,所以可以轻松的规划设计与制造出上大下小的引脚结构,可以使上下层塑封料紧密的将上大下小的引脚结构一起包裹住,所以塑封体与引脚的束缚能力就变大了,不会再有产生掉脚的问题。Since the lead frame adopts the double-sided etching process technology, it is easy to plan, design and manufacture the pin structure with large upper and lower pins, so that the upper and lower layers of plastic compound can tightly wrap the pin structure with large upper and lower pins. , so the binding ability between the plastic package and the pins becomes larger, and there will be no more problems of falling feet.

2、确保金属线的长度缩短2. Ensure that the length of the metal wire is shortened

1)由于应用了引线框背面与正面分开蚀刻的技术,所以能够将引线框正面的引脚尽可能的延伸到后续需装芯片的区域旁边,促使芯片与引脚距离大幅的缩短,如图2~图3,如此金属线的长度也缩短了,金属线的成本也可以大幅的降低(尤其是昂贵的纯金质的金属线);1) Due to the application of the technology of separate etching on the back and front of the lead frame, the pins on the front of the lead frame can be extended as far as possible to the side of the area where the chip needs to be installed later, which greatly shortens the distance between the chip and the pin, as shown in Figure 2 ~Figure 3, so the length of the metal wire is also shortened, and the cost of the metal wire can also be greatly reduced (especially the expensive pure gold metal wire);

2)也因为金属线的长度缩短使得芯片的信号输出速度也大幅的增速(尤其存储类的产品以及需要大量数据的计算,更为突出),由于金属线的长度变短了,所以金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也大幅度的降低。2) Also because the length of the metal wire is shortened, the signal output speed of the chip is also greatly increased (especially for storage products and calculations that require a large amount of data). The interference of the existing parasitic resistance/capacitance and parasitic poles to the signal is also greatly reduced.

3、使封装的体积与面积可以大幅度的缩小3. The volume and area of the package can be greatly reduced

因运用了引脚的延伸技术,所以可以容易的制作出高脚数与高密度的脚与脚之间的距离,使得封装的体积与面积可以大幅度的缩小。Due to the use of pin extension technology, it is easy to produce a high number of pins and a high-density pin-to-pin distance, so that the volume and area of the package can be greatly reduced.

4、材料成本和材料用量减少4. Reduced material cost and material consumption

因为将封装后的体积大幅度的缩小,更直接的体现出材料成本大幅度的下降与因为材料用量的减少也大幅度的减少废弃物环保的困扰。Because the volume after packaging is greatly reduced, it more directly reflects the substantial reduction in material costs and the reduction in the amount of materials used also greatly reduces the problem of waste and environmental protection.

5、采用局部單元的单颗封装的优点有:5. The advantages of using a single package of local units are:

1)在不同的应用中可以将塑封体边缘的引脚伸出塑封体。1) In different applications, the pins on the edge of the plastic package can be extended out of the plastic package.

2)塑封体边缘的引脚伸出塑封体外可以清楚的检查出焊接在PCB板上的情况。2) The pins on the edge of the plastic package extend out of the plastic package to clearly check the soldering on the PCB.

3)模块型的面积较大会容易因为多种不同的材料结构所产生收缩率不同的应立变形,而局部单元的单颗封装就可以完全分散多种不同的材料结构所产生收缩率不同的应立变形。3) The large area of the modular type will easily cause the deformation of the different shrinkage rates due to a variety of different material structures, and the single package of the local unit can completely disperse the different shrinkage rates of the different material structures. vertical deformation.

4)单颗封装在进行塑封体切割分离时,因为要切割的厚度只有引脚的厚度,所以切割的速度可以比模块型的封装结构要来得快很多,且切割用的刀片因为切割的厚度便薄了所以切割刀片的寿命相对的也就变的更长了。4) When a single package is cut and separated from the plastic package, because the thickness to be cut is only the thickness of the pin, the cutting speed can be much faster than that of the modular package structure, and the cutting blade is easy to cut because of the cutting thickness. It is thinner, so the life of the cutting blade is relatively longer.

(四)附图说明 (4) Description of drawings

图1(A)~图1(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例1各工序示意图。1(A) to 1(R) are schematic diagrams of each process in Embodiment 1 of the double-sided graphics chip packaging method of the present invention, first plating and then engraving a single chip.

图2为本发明双面图形芯片正装单颗封装结构实施例1结构示意图。Fig. 2 is a structural schematic diagram of Embodiment 1 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图3为图2的俯视图。FIG. 3 is a top view of FIG. 2 .

图4(A)~图4(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例2各工序示意图。4(A) to 4(R) are schematic diagrams of each process in Embodiment 2 of the double-sided graphics chip packaging method of the present invention.

图5为本发明双面图形芯片正装单颗封装结构实施例2结构示意图。FIG. 5 is a structural schematic diagram of Embodiment 2 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图6为图5的俯视图。FIG. 6 is a top view of FIG. 5 .

图7(A)~图7(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例3各工序示意图。7(A) to 7(R) are schematic diagrams of each process in Embodiment 3 of the packaging method for a double-sided graphics chip, first plated and then engraved, according to the present invention.

图8为本发明双面图形芯片正装单颗封装结构实施例3结构示意图。FIG. 8 is a structural schematic diagram of Embodiment 3 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图9为图8的俯视图。FIG. 9 is a top view of FIG. 8 .

图10(A)~图10(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例4各工序示意图。10(A) to 10(R) are schematic diagrams of each process in Embodiment 4 of the double-sided graphics chip packaging method of the present invention, which is packaged first by plating and then engraved.

图11为本发明双面图形芯片正装单颗封装结构实施例4结构示意图。Fig. 11 is a structural schematic diagram of Embodiment 4 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图12为图11的俯视图。FIG. 12 is a top view of FIG. 11 .

图13(A)~图13(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例5各工序示意图。13(A) to 13(R) are schematic diagrams of each process in Embodiment 5 of the double-sided graphics chip packaging method of the present invention.

图14为本发明双面图形芯片正装单颗封装结构实施例5结构示意图。Fig. 14 is a structural schematic diagram of Embodiment 5 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图15为图14的俯视图。FIG. 15 is a top view of FIG. 14 .

图16(A)~图16(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例6各工序示意图。16(A) to 16(R) are schematic diagrams of each process in Embodiment 6 of the double-sided graphics chip packaging method of the present invention.

图17为本发明双面图形芯片正装单颗封装结构实施例6结构示意图。FIG. 17 is a schematic structural diagram of Embodiment 6 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图18为图17的俯视图。FIG. 18 is a top view of FIG. 17 .

图19(A)~图19(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例7各工序示意图。19(A) to 19(R) are schematic diagrams of each process in Embodiment 7 of the double-sided graphics chip packaging method of the present invention, which is packaged first by plating and then engraved.

图20为本发明双面图形芯片正装单颗封装结构实施例7结构示意图。FIG. 20 is a structural schematic diagram of Embodiment 7 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图21为图20的俯视图。FIG. 21 is a top view of FIG. 20 .

图22(A)~图22(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例8各工序示意图。22(A) to 22(R) are schematic diagrams of each process in Embodiment 8 of the double-sided graphics chip packaging method of the present invention, which is first plated and then engraved on a single chip.

图23为本发明双面图形芯片正装单颗封装结构实施例8结构示意图。Fig. 23 is a structural schematic diagram of Embodiment 8 of a front-mounted single-chip package structure of a double-sided graphics chip according to the present invention.

图24为图23的俯视图。FIG. 24 is a top view of FIG. 23 .

图25(A)~图25(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例5各工序示意图。25(A) to 25(R) are schematic diagrams of each process in Embodiment 5 of the double-sided graphics chip package method of the present invention, which is first plated and then engraved for a single chip.

图26为本发明双面图形芯片正装单颗封装结构实施例5结构示意图。Fig. 26 is a structural schematic diagram of Embodiment 5 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图27为图26的俯视图。FIG. 27 is a top view of FIG. 26 .

图28(A)~图28(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例6各工序示意图。28(A) to 28(R) are schematic diagrams of each process in Embodiment 6 of the double-sided graphics chip packaging method of the present invention, which is packaged first by plating and then engraved.

图29为本发明双面图形芯片正装单颗封装结构实施例6结构示意图。Fig. 29 is a structural schematic diagram of Embodiment 6 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图30为图29的俯视图。FIG. 30 is a top view of FIG. 29 .

图31(A)~图31(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例11各工序示意图。31(A) to 31(R) are schematic diagrams of each process in Embodiment 11 of the double-sided graphics chip packaging method of the present invention, which is packaged first by plating and then engraved.

图32为本发明双面图形芯片正装单颗封装结构实施例11结构示意图。Fig. 32 is a structural schematic diagram of Embodiment 11 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图33为图32的俯视图。FIG. 33 is a top view of FIG. 32 .

图34(A)~图34(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例12各工序示意图。34(A) to 34(R) are schematic diagrams of each process in Embodiment 12 of the double-sided graphics chip packaging method of the present invention, which is packaged first and then engraved.

图35为本发明双面图形芯片正装单颗封装结构实施例12结构示意图。Fig. 35 is a structural schematic diagram of Embodiment 12 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图36为图35的俯视图。FIG. 36 is a top view of FIG. 35 .

图37(A)~图37(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例13各工序示意图。37(A) to 37(R) are schematic diagrams of each process in Embodiment 13 of the double-sided graphics chip packaging method of the present invention.

图38为本发明双面图形芯片正装单颗封装结构实施例13结构示意图。Fig. 38 is a structural schematic diagram of Embodiment 13 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图39为图38的俯视图。FIG. 39 is a top view of FIG. 38 .

图40(A)~图40(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例14各工序示意图。40(A) to 40(R) are schematic diagrams of each process in Embodiment 14 of the double-sided graphics chip packaging method of the present invention.

图41为本发明双面图形芯片正装单颗封装结构实施例14结构示意图。Fig. 41 is a structural schematic diagram of Embodiment 14 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.

图42为图41的俯视图。FIG. 42 is a top view of FIG. 41 .

图43为以往采用金属基板的正面进行化学蚀刻及表面电镀层作业图。Fig. 43 is a working diagram of chemical etching and surface electroplating on the front side of a metal substrate in the past.

图44为以往形成的掉脚图。Fig. 44 is a diagram of a footfall formed in the past.

图45为以往的封装结构示意图。Fig. 45 is a schematic diagram of a conventional package structure.

图46为45的俯视图。FIG. 46 is a top view of 45 .

图中附图标记:Reference signs in the figure:

基岛1、引脚2、无填料的塑封料(环氧树脂))3、第一金属层4、第二金属层5、导电或不导电粘结物质6、芯片7、金属线8、有填料塑封料(环氧树脂)9、金属基板10、光阻胶膜11、光阻胶膜12、光阻胶膜13、光阻胶膜14、光阻胶膜15、光阻胶膜16;base island 1, pins 2, plastic encapsulant (epoxy resin) without filler) 3, first metal layer 4, second metal layer 5, conductive or non-conductive bonding substance 6, chip 7, metal wire 8, with Filler molding compound (epoxy resin) 9, metal substrate 10, photoresist film 11, photoresist film 12, photoresist film 13, photoresist film 14, photoresist film 15, photoresist film 16;

第三基岛1.1、第三基岛1.2、第三基岛1.3、第四基岛1.4。The third base island 1.1, the third base island 1.2, the third base island 1.3, and the fourth base island 1.4.

(五)具体实施方式 (5) Specific implementation methods

本发明双面图形芯片正装先镀后刻单颗封装方法如下:The double-sided graphics chip of the present invention is mounted first and then engraved with a single packaging method as follows:

实施例1:单基岛单圈引脚Example 1: Single base island single turn pin

参见图2和图3,图2为本发明双面图形芯片正装单颗封装结构实施例1结构示意图。图3为图2的俯视图。由图2和图3可以看出,本发明双面图形芯片正装单颗封装结构,包括基岛1、引脚2、无填料的塑封料(环氧树脂)3、导电或不导电粘结物质6、芯片7、金属线8和有填料塑封料(环氧树脂)9,所述引脚2正面尽可能的延伸到基岛1旁边,在所述基岛1和引脚2的正面设置有第一金属层4,在所述基岛1和引脚2的背面设置有第二金属层5,在所述基岛1正面第一金属层4上通过导电或不导电粘结物质6设置有芯片7,芯片7正面与引脚2正面第一金属层4之间用金属线8连接,在所述基岛1和引脚2的上部以及芯片7和金属线8外包封有填料塑封料(环氧树脂)9,该有填料塑封料(环氧树脂)9将引脚2正面局部单元进行包覆,在所述基岛1和引脚2外围的区域、引脚2与基岛1之间的区域以及引脚2与引脚2之间的区域嵌置有无填料的塑封料(环氧树脂)3,所述无填料的塑封料(环氧树脂)3将基岛1和引脚下部外围、引脚2下部与基岛1下部以及引脚2下部与引脚2下部连接成一体,且使所述基岛和引脚背面尺寸小于基岛和引脚正面尺寸,形成上大下小的基岛和引脚结构。Referring to FIG. 2 and FIG. 3 , FIG. 2 is a structural schematic diagram of Embodiment 1 of the double-sided graphic chip front-mount single-chip package structure of the present invention. FIG. 3 is a top view of FIG. 2 . As can be seen from Fig. 2 and Fig. 3, the double-sided graphics chip of the present invention is mounted on a single package structure, including base island 1, pin 2, plastic encapsulant (epoxy resin) 3 without filler, conductive or non-conductive bonding substance 6. Chip 7, metal wire 8 and filler molding compound (epoxy resin) 9, the front of the pin 2 extends to the side of the base island 1 as much as possible, and the front of the base island 1 and the pin 2 is provided with The first metal layer 4 is provided with a second metal layer 5 on the back of the base island 1 and the pin 2, and a conductive or non-conductive adhesive substance 6 is provided on the first metal layer 4 on the front of the base island 1. Chip 7, the front of the chip 7 is connected with the first metal layer 4 on the front of the pin 2 with a metal wire 8, and the top of the base island 1 and the pin 2, as well as the chip 7 and the metal wire 8 are encapsulated with a filler plastic compound ( Epoxy resin) 9, the filler molding compound (epoxy resin) 9 covers the front part of the pin 2, in the area around the base island 1 and the pin 2, between the pin 2 and the base island 1 The area between the pin 2 and the pin 2 is embedded with a filler-free molding compound (epoxy resin) 3, and the filler-free molding compound (epoxy resin) 3 connects the base island 1 and the pin The periphery of the lower part, the lower part of the pin 2 and the lower part of the base island 1, and the lower part of the pin 2 and the lower part of the pin 2 are connected into one body, and the size of the base island and the back of the pin is smaller than the size of the base island and the front of the pin, forming an upper and a lower Small base island and pin structure.

其封装方法如下:Its packaging method is as follows:

步骤一、取金属基板Step 1. Take the metal substrate

参见图1(A),取一片厚度合适的金属基板10。金属基板的材质可以依据芯片的功能与特性进行变换,例如:铜、铝、铁、铜合金或镍铁合金等。Referring to FIG. 1(A), take a metal substrate 10 with an appropriate thickness. The material of the metal substrate can be changed according to the functions and characteristics of the chip, for example: copper, aluminum, iron, copper alloy or nickel-iron alloy.

步骤二、金属基板正面及背面被覆光阻胶膜Step 2. The front and back of the metal substrate are coated with photoresist film

参见图1(B),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜11和12,以保护后续的电镀金属层工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(B), the front and back sides of the metal substrate are coated with photoresist films 11 and 12 that can be exposed and developed by coating equipment to protect the subsequent electroplating metal layer process. The photoresist film can be a dry photoresist thin film or a wet photoresist film.

步骤三、金属基板正面的光阻胶膜进行需要电镀金属层区域的曝光/显影以及开窗Step 3: Expose/develop the photoresist film on the front of the metal substrate and open the window where the metal layer needs to be plated

参见图1(C),利用曝光显影设备将步骤二完成光阻胶膜被覆作业的金属基板正面进行曝光显影去除部分光阻胶膜,以露出金属基板正面后续需要进行电镀金属层的区域。Referring to FIG. 1(C), use exposure and development equipment to expose and develop the front of the metal substrate that has completed the photoresist film coating operation in step 2 to remove part of the photoresist film to expose the area on the front of the metal substrate that needs to be subsequently electroplated with a metal layer.

步骤四、金属基板正面已开窗的区域进行金属层电镀被覆Step 4. Electroplating and coating the metal layer on the windowed area on the front of the metal substrate

参见图1(D),对步骤三中金属基板正面已开窗的区域进行第一金属层4电镀被覆,该第一金属层4置于所述基岛1与引脚2的正面。Referring to FIG. 1(D), the first metal layer 4 is electroplated on the area where the window has been opened on the front side of the metal substrate in step 3, and the first metal layer 4 is placed on the front side of the base island 1 and the pin 2 .

步骤五、金属基板正面及背面进行光阻胶膜去膜Step 5. Remove the photoresist film on the front and back of the metal substrate

参见图1(E),将金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除。Referring to FIG. 1(E), remove the remaining photoresist film on the front side of the metal substrate and the photoresist film on the back side of the metal substrate.

步骤六、金属基板正面及背面被覆光阻胶膜Step 6. Cover the front and back of the metal substrate with photoresist film

参见图1(F),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜13和14,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(F), the front and back sides of the metal substrate are coated with photoresist films 13 and 14 that can be exposed and developed by coating equipment, so as to protect the subsequent etching process. The photoresist film can be a dry photoresist thin film or a wet photoresist film.

步骤七、金属基板背面的光阻胶膜进行需要蚀刻区域的曝光/显影以及开窗Step 7. Expose/develop the photoresist film on the back of the metal substrate and open the window for the area to be etched

参见图1(G),利用曝光显影设备将步骤六完成光阻胶膜被覆作业的金属基板背面进行曝光显影去除部分光阻胶膜,以露出局部金属基板以备后续需要进行的金属基板背面蚀刻作业。Referring to Figure 1(G), use the exposure and development equipment to expose and develop the back of the metal substrate that has completed the photoresist film coating operation in step 6 to remove part of the photoresist film, so as to expose a part of the metal substrate for subsequent etching on the back of the metal substrate Operation.

步骤八、金属基板进行背面蚀刻作业Step 8. Etching the back of the metal substrate

参见图1(H),完成步骤七的曝光/显影以及开窗作业后,即在金属基板的背面进行各图形的蚀刻作业,蚀刻出基岛1和引脚2的背面,同时将引脚正面尽可能的延伸到基岛旁边。Referring to Figure 1(H), after completing the exposure/development and window opening operations in step 7, the etching operation of each pattern is performed on the back of the metal substrate to etch the back of the base island 1 and pin 2, and at the same time, the front of the pin is etched. Extend as far as possible to the side of the base island.

步骤九、金属基板正面及背面进行光阻胶膜去膜Step 9. Remove the photoresist film on the front and back of the metal substrate

参见图1(I),将金属基板正面和背面余下的光阻胶膜全部揭除。Referring to FIG. 1(I), the remaining photoresist films on the front and back of the metal substrate are all removed.

步骤十、包封无填料的塑封料(环氧树脂)Step 10. Encapsulate the plastic compound (epoxy resin) without filler

参见图1(J),将已完成步骤九所述去膜作业的金属基板背面进行包封无填料的塑封料(环氧树脂)作业,并进行塑封料包封后的固化作业,使基岛1和引脚2外围的区域、引脚2与基岛1之间的区域以及引脚2与引脚2之间的区域均嵌置无填料的塑封料(环氧树脂)3,该无填料的塑封料(环氧树脂)3将基岛1和引脚下部外围、引脚2下部与基岛1下部以及引脚2下部与引脚2下部连接成一体。Referring to Figure 1(J), the back of the metal substrate that has completed the film removal operation described in step 9 is encapsulated with no filler molding compound (epoxy resin), and the curing operation is performed after the molding compound is encapsulated, so that the base island 1 and the peripheral area of pin 2, the area between pin 2 and base island 1, and the area between pin 2 and pin 2 are all embedded with no filler molding compound (epoxy resin) 3, the filler-free The molding compound (epoxy resin) 3 connects the base island 1 and the periphery of the lower part of the pin, the lower part of the pin 2 and the lower part of the base island 1, and the lower part of the pin 2 and the lower part of the pin 2 into one body.

步骤十一、被覆光阻胶膜Step 11. Coating photoresist film

参见图1(K),利用被覆设备在将已完成包封无填料塑封料作业的金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜15和16,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to Fig. 1(K), use the coating equipment to coat the front and back of the metal substrate that has completed the encapsulation of the filler-free molding compound with photoresist films 15 and 16 that can be exposed and developed, so as to protect the subsequent etching process. . The photoresist film can be a dry photoresist thin film or a wet photoresist film.

步骤十二、已完成包封无填料塑封料作业的金属基板的正面进行需要蚀刻区域的曝光/显影以及开窗Step 12: Expose/develop the area to be etched and open the window on the front side of the metal substrate that has completed the encapsulation of the non-filler molding compound

参见图1(L),利用曝光显影设备将步骤十一完成光阻胶膜被覆作业的已完成包封无填料塑封料作业的金属基板正面进行曝光显影去除部分光阻胶膜,以备后续需要进行金属基板正面蚀刻作业。Referring to Figure 1(L), use the exposure and development equipment to expose and develop the front side of the metal substrate that has completed the encapsulation and non-filler molding compound operation in step 11 to remove part of the photoresist film for subsequent needs Perform front side etching of metal substrates.

步骤十三、金属基板正面蚀刻作业Step 13. Etching the front side of the metal substrate

参见图1(M),完成步骤十二的曝光/显影以及开窗作业后,即在完成包封无填料塑封料作业的金属基板正面进行各图形的蚀刻作业,蚀刻出基岛1和引脚2的正面,且使所述基岛1和引脚2的背面尺寸小于基岛1和引脚2的正面尺寸,形成上大下小的基岛1和引脚2结构。Referring to Figure 1(M), after completing the exposure/development and window opening operations in step 12, the etching operation of each pattern is performed on the front of the metal substrate that has completed the encapsulation of the non-filler plastic encapsulant, and the base island 1 and the pins are etched out 2, and make the size of the back side of the base island 1 and the pin 2 smaller than the front size of the base island 1 and the pin 2, forming a structure of the base island 1 and the pin 2 with a large top and a small bottom.

步骤十四、金属基板正面及背面进行光阻胶膜去膜Step 14. Remove the photoresist film on the front and back of the metal substrate

参见图1(N),将完成步骤十三蚀刻作业的金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除,制成引线框。Referring to FIG. 1(N), the remaining photoresist film on the front side of the metal substrate and the photoresist film on the back side of the metal substrate after step 13 etching is removed to form a lead frame.

步骤十五、装片Step 15, loading film

参见图1(O),在基岛1正面第一金属层4上通过导电或不导电粘结物质6进行芯片7的植入。Referring to FIG. 1(O), the chip 7 is implanted on the first metal layer 4 on the front side of the base island 1 through a conductive or non-conductive adhesive substance 6 .

步骤十六、打金属线Step 16, hit the metal wire

参见图1(P),将已完成芯片植入作业的半成品进行芯片正面与引脚正面第一金属层之间打金属线8作业。Referring to FIG. 1(P), the semi-finished product that has completed the chip implantation operation is put into metal wire 8 between the front side of the chip and the first metal layer on the front side of the pin.

步骤十七、包封有填料塑封料(环氧树脂)Step 17. Encapsulate with filler molding compound (epoxy resin)

参见图1(Q),将已打线完成的半成品正面进行局部单元包封有填料塑封料9作业,使引脚2正面局部单元区域露出有填料塑封料(环氧树脂)9,并进行塑封料包封后的固化作业,使基岛和引脚的上部以及芯片和金属线外均被有填料塑封料(环氧树脂)包封。Referring to Figure 1(Q), the front side of the semi-finished product that has been wired is partially encapsulated with filler molding compound 9, so that the filler molding compound (epoxy resin) 9 is exposed in the partial unit area on the front side of the pin 2, and plastic sealing is carried out. The curing operation after material encapsulation makes the base island and the upper part of the pin, as well as the outside of the chip and the metal wire all be encapsulated by a filler plastic encapsulant (epoxy resin).

步骤十八、基岛和引脚的背面以及引脚的正面进行金属层电镀被覆Step 18, the base island and the back of the pin and the front of the pin are electroplated with a metal layer

参见图1(R),对已完成步骤十七包封有填料塑封料(环氧树脂)作业的所述基岛和引脚的背面以及步骤十七所述露出有填料塑封料(环氧树脂)9的引脚2正面局部单元区域分别进行第二金属层5和第一金属层4电镀被覆作业,而电镀的材料可以是锡、镍金、镍钯金....等金属材质。Referring to Fig. 1 (R), the back side of the base island and pins that have completed step 17 encapsulation with filler molding compound (epoxy resin) and the exposed filler molding compound (epoxy resin) described in step 17 ) The partial unit area on the front side of the pin 2 of 9 is subjected to the electroplating and coating operation of the second metal layer 5 and the first metal layer 4 respectively, and the electroplating material can be tin, nickel gold, nickel palladium gold...etc. metal materials.

步骤十九、切割成品Step nineteen, cut the finished product

参见图2和图3,将已完成步骤十八第二金属层电镀被覆的半成品进行切割作业,使原本以列阵式集合体方式连在一起的芯片一颗颗独立开来,制得双面图形芯片正装单颗封装结构成品。Referring to Figure 2 and Figure 3, the semi-finished product that has completed the electroplating and coating of the second metal layer in step 18 is cut, so that the chips that were originally connected together in the form of an array assembly are separated one by one to obtain a double-sided The graphics chip is being installed in a single package structure.

实施例2:下沉基岛露出型单圈引脚Embodiment 2: sunken base island exposed type single-turn pin

参见图4~6,图4(A)~图4(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例2各工序示意图。图5为本发明双面图形芯片正装单颗封装结构实施例2结构示意图。图6为图5的俯视图。由图4、图5和图6可以看出,实施例2与实施例1的不同之处仅在于:所述基岛1为下沉型基岛,即基岛1正面中央区域下沉。Referring to Figures 4 to 6, Figures 4(A) to 4(R) are schematic diagrams of each process in Embodiment 2 of the double-sided graphics chip packaging method of the present invention, first plated and then engraved. FIG. 5 is a structural schematic diagram of Embodiment 2 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 6 is a top view of FIG. 5 . It can be seen from FIG. 4 , FIG. 5 and FIG. 6 that the only difference between Embodiment 2 and Embodiment 1 is that the base island 1 is a sunken base island, that is, the central area of the front of the base island 1 is sunken.

实施例3:埋入型基岛单圈引脚Embodiment 3: Embedded base island single-turn pin

参见图7~9,图7(A)~图7(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例3各工序示意图。图8为本发明双面图形芯片正装单颗封装结构实施例3结构示意图。图9为图8的俯视图。由图7、图8和图9可以看出,实施例3与实施例1的不同之处仅在于:所述基岛1为埋入型基岛,即基岛1背面埋入所述无填料的塑封料(环氧树脂)3内。Referring to Figures 7 to 9, Figures 7(A) to 7(R) are schematic diagrams of each process in Embodiment 3 of the double-sided graphics chip packaging method of the present invention, first plating and then engraving a single chip. FIG. 8 is a structural schematic diagram of Embodiment 3 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 9 is a top view of FIG. 8 . It can be seen from Fig. 7, Fig. 8 and Fig. 9 that the only difference between Embodiment 3 and Embodiment 1 is that the base island 1 is an embedded type base island, that is, the back of the base island 1 is embedded with the non-filler The molding compound (epoxy resin) 3 inside.

实施例4:多凸点基岛露出型单圈引脚Embodiment 4: Multi-bump base island exposed single-turn pin

参见图10~12,图10(A)~图10(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例4各工序示意图。图11为本发明双面图形芯片正装单颗封装结构实施例4结构示意图。图12为图11的俯视图。由图10、图11和图12可以看出,实施例4与实施例1的不同之处仅在于:所述基岛1为多凸点基岛,即基岛1表面设置有多个凸点。Referring to Figures 10-12, Figures 10(A)-10(R) are schematic diagrams of each process in Embodiment 4 of the double-sided graphics chip packaging method of the present invention, which is first plated and then engraved. Fig. 11 is a structural schematic diagram of Embodiment 4 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 12 is a top view of FIG. 11 . It can be seen from Figure 10, Figure 11 and Figure 12 that the difference between Embodiment 4 and Embodiment 1 is that the base island 1 is a multi-bump base island, that is, the surface of the base island 1 is provided with multiple bumps .

实施例5:多个基岛露出型单圈引脚Embodiment 5: Multiple base island exposed single-turn pins

参见图13~15,图13(A)~图13(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例5各工序示意图。图14为本发明双面图形芯片正装单颗封装结构实施例5结构示意图。图15为图14的俯视图。由图13~15可以看出,实施例5与实施例1的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 13-15, Figures 13(A)-13(R) are schematic diagrams of each process in Embodiment 5 of the double-sided graphics chip packaging method of the present invention, which is packaged first by plating and then engraved. Fig. 14 is a structural schematic diagram of Embodiment 5 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 15 is a top view of FIG. 14 . It can be seen from FIGS. 13 to 15 that the difference between Embodiment 5 and Embodiment 1 lies in that: there are multiple base islands 1 , and the pin 2 has a single turn.

实施例6:多个下沉基岛露出型单圈引脚Embodiment 6: Multiple sunken base island exposed single-turn pins

参见图16~18,图16(A)~图16(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例6各工序示意图。图17为本发明双面图形芯片正装单颗封装结构实施例6结构示意图。图18为图17的俯视图。由图16~18可以看出,实施例6与实施例2的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 16-18, Figures 16(A)-16(R) are schematic diagrams of each process in Embodiment 6 of the double-sided graphics chip packaging method of the present invention, which is packaged first by plating and then engraved. FIG. 17 is a schematic structural diagram of Embodiment 6 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 18 is a top view of FIG. 17 . It can be seen from FIGS. 16 to 18 that the difference between Embodiment 6 and Embodiment 2 lies in that: there are multiple base islands 1 , and the pin 2 has a single turn.

实施例7:多个埋入型基岛单圈引脚Example 7: Multiple Buried Base Island Single Turn Pins

参见图19~21,图19(A)~图19(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例7各工序示意图。图20为本发明双面图形芯片正装单颗封装结构实施例7结构示意图。图21为图20的俯视图。由图19~21可以看出,实施例7与实施例3的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 19-21, Figures 19(A)-19(R) are schematic diagrams of each process in Embodiment 7 of the double-sided graphics chip packaging method of the present invention. FIG. 20 is a structural schematic diagram of Embodiment 7 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 21 is a top view of FIG. 20 . It can be seen from FIGS. 19-21 that the difference between Embodiment 7 and Embodiment 3 lies in that: there are multiple base islands 1 , and the pin 2 has a single turn.

实施例8:多个多凸点基岛露出型单圈引脚Embodiment 8: Multiple multi-bump base island exposed single-turn pins

参见图22~24,图22(A)~图22(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例8各工序示意图。图23为本发明双面图形芯片正装单颗封装结构实施例8结构示意图。图24为图23的俯视图。由图22~24可以看出,实施例8与实施例4的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 22-24, Figures 22(A)-22(R) are schematic diagrams of each process in Embodiment 8 of the packaging method for double-sided graphics chips of the present invention, which are first plated and then engraved on a single chip. Fig. 23 is a structural schematic diagram of Embodiment 8 of a front-mounted single-chip package structure of a double-sided graphics chip according to the present invention. FIG. 24 is a top view of FIG. 23 . It can be seen from FIGS. 22 to 24 that the difference between Embodiment 8 and Embodiment 4 lies in that: there are multiple base islands 1 , and the pin 2 has a single turn.

实施例9:基岛露出型及下沉基岛露出型单圈引脚Embodiment 9: base island exposed type and sunken base island exposed type single-turn pin

参见图25~27,图25(A)~图25(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例9各工序示意图。图26为本发明双面图形芯片正装单颗封装结构实施例9结构示意图。图27为图26的俯视图。由图25~27可以看出,实施例9与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第二基岛1.2,所述第二基岛1.2正面中央区域下沉,在所述第一基岛1.1和引脚2的正面设置第一金属层4,在所述第一基岛1.1、第二基岛1.2和引脚2的背面设置第二金属层5,在第二基岛1.2正面中央下沉区域和第一基岛1.1正面通过导电或不导电粘结物质6设置芯片7,芯片7正面与引脚2正面第一金属层4之间以及芯片7与芯片7之间均用金属线8连接,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第一基岛1.1与第二基岛1.2之间的区域、第二基岛1.2与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第一基岛1.1下部、第一基岛1.1与第二基岛1.2下部、第二基岛1.2与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2有单圈。Referring to Fig. 25-27, Fig. 25(A)-Fig. 25(R) are schematic diagrams of each process in Embodiment 9 of the packaging method for double-sided graphics chips of the present invention. Fig. 26 is a structural schematic diagram of Embodiment 9 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 27 is a top view of FIG. 26 . It can be seen from Figures 25 to 27 that the difference between Embodiment 9 and Embodiment 1 is that: the base island 1 has two groups or multiple groups of base islands, one group is the first base island 1.1, and the other group is the first base island 1.1. For the second base island 1.2, the central area of the front of the second base island 1.2 sinks, and the first metal layer 4 is set on the front of the first base island 1.1 and the pin 2, and on the first base island 1.1, The second metal layer 5 is arranged on the back of the second base island 1.2 and the pin 2, and the chip 7 is arranged on the central sunken area of the front of the second base island 1.2 and the front of the first base island 1.1 through a conductive or non-conductive bonding substance 6, the chip 7. Both the front side and the first metal layer 4 on the front side of the pin 2 and between the chip 7 and the chip 7 are connected with a metal wire 8, in the peripheral area of the pin 2, between the pin 2 and the first base island 1.1 The area between the first base island 1.1 and the second base island 1.2, the area between the second base island 1.2 and pin 2, and the area between pin 2 and pin 2 are embedded with filler-free molding compound 3. The filler-free molding compound 3 connects the periphery of the lower part of the pin, the lower part of the pin 2 and the first base island 1.1, the lower part of the first base island 1.1 and the second base island 1.2, the second base island 1.2 and the lower part of the pin 2, and Pin 2 is integrally connected with the lower part of pin 2, said pin 2 has a single turn.

实施例10:基岛露出型及埋入型基岛单圈引脚Embodiment 10: base island exposed type and embedded type base island single-turn pin

参见图28~30,图28(A)~图28(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例10各工序示意图。图29为本发明双面图形芯片正装单颗封装结构实施例10结构示意图。图30为图29的俯视图。由图28~30可以看出,实施例10与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第三基岛1.3,在所述第一基岛1.1第三基岛1.3和引脚2的正面设置第一金属层4,在所述第一基岛1.1和引脚2的背面设置第二金属层5,芯片7正面与引脚2正面第一金属层4之间以及芯片7与芯片7之间均用金属线8连接,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第三基岛1.3背面、第三基岛1.3与第一基岛1.1之间的区域、第三基岛1.3与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第一基岛1.1下部、第三基岛1.3背面、第三基岛1.3背面与第一基岛1.1下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有单圈。Referring to Figures 28-30, Figures 28(A)-28(R) are schematic diagrams of each process in Embodiment 10 of the double-sided graphics chip packaging method of the present invention. Fig. 29 is a structural schematic diagram of Embodiment 10 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 30 is a top view of FIG. 29 . It can be seen from Figures 28 to 30 that the difference between Embodiment 10 and Embodiment 1 is that: the base island 1 has two groups or multiple groups of base islands, one group is the first base island 1.1, and the other group is the first base island 1.1. For the third base island 1.3, the first metal layer 4 is arranged on the front of the first base island 1.1, the third base island 1.3 and the pin 2, and the second metal layer 4 is arranged on the back of the first base island 1.1 and the pin 2. The metal layer 5, the front of the chip 7 and the first metal layer 4 on the front of the pin 2 and between the chip 7 and the chip 7 are all connected with a metal wire 8. In the area around the pin 2, the pin 2 and the first Area between base island 1.1, back of third base island 1.3, area between third base island 1.3 and first base island 1.1, area between third base island 1.3 and pin 2, and pin to pin Filler-free molding compound 3 is embedded in the area between, and the filler-free molding compound 3 connects the lower periphery of the pin, the pin 2 and the lower part of the first base island 1.1, the back of the third base island 1.3, and the back of the third base island 1.3 and The lower part of the first base island 1.1, the back of the third base island 1.3 and the lower part of the pin 2 and the lower part of the pin 2 are connected as a whole, and the pin 2 is provided with a single loop.

实施例11:基岛露出型及多凸点基岛露出型单圈引脚Embodiment 11: base island exposed type and multi-bump base island exposed type single-turn pin

参见图31~33,图31(A)~图31(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例11各工序示意图。图32为本发明双面图形芯片正装单颗封装结构实施例11结构示意图。图33为图32的俯视图。由图31~33可以看出,实施例11与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第四基岛1.4,所述第四基岛1.4正面设置成多凸点状结构,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第一基岛1.1与第四基岛1.4之间的区域、第四基岛1.4与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料的塑封料(环氧树脂)3将引脚下部外围、引脚2与第一基岛1.1下部、第一基岛1.1与第四基岛1.4下部、第四基岛1.4与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有单圈。Referring to Figures 31-33, Figures 31(A)-31(R) are schematic diagrams of each process in Embodiment 11 of the packaging method for double-sided graphics chips of the present invention. Fig. 32 is a structural schematic diagram of Embodiment 11 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 33 is a top view of FIG. 32 . It can be seen from Figures 31 to 33 that the difference between Embodiment 11 and Embodiment 1 is that: the base island 1 has two groups or multiple groups of base islands, one group is the first base island 1.1, and the other group is the first base island 1.1. It is the fourth base island 1.4, the front side of the fourth base island 1.4 is arranged in a multi-bump structure, in the area around the pin 2, the area between the pin 2 and the first base island 1.1, the first base island 1.1 The area between the island 1.1 and the fourth base island 1.4, the area between the fourth base island 1.4 and the pin 2, and the area between the pin 2 and the pin 2 are embedded with filler-free molding compound 3, the filler-free The plastic encapsulant (epoxy resin) 3 connects the lower periphery of the pin, the lower part of the pin 2 and the first base island 1.1, the lower part of the first base island 1.1 and the fourth base island 1.4, the fourth base island 1.4 and the lower part of the pin 2, and The pin 2 is integrally connected with the lower part of the pin 2, and the pin 2 is provided with a single circle.

实施例12:下沉基岛露出型及埋入型基岛露出型单圈引脚Embodiment 12: Sunken base island exposed type and buried base island exposed type single-turn pin

参见图34~36,图34(A)~图34(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例12各工序示意图。图35为本发明双面图形芯片正装单颗封装结构实施例12结构示意图。图36为图35的俯视图。由图34~36可以看出,实施例12与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第二基岛1.2,另一组为第三基岛1.3,所述第二基岛1.2正面中央区域下沉,在第二基岛1.2正面中央下沉区域和第三基岛1.3正面通过导电或不导电粘结物质6设置芯片7,在所述引脚2外围的区域、引脚2与第二基岛1.2之间的区域、第三基岛1.3背面、第二基岛背面1.2与第二基岛1.2之间的区域、第三基岛1.3背面与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第二基岛1.2下部、第三基岛1.3、第三基岛1.3与第二基岛1.2下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 34 to 36, Figures 34(A) to 34(R) are schematic diagrams of each process in Embodiment 12 of the double-sided graphics chip packaging method of the present invention. Fig. 35 is a structural schematic diagram of Embodiment 12 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 36 is a top view of FIG. 35 . It can be seen from Figures 34 to 36 that the difference between Embodiment 12 and Embodiment 1 is that: the base island 1 has two groups or multiple groups of base islands, one group is the second base island 1.2, and the other group is the second base island 1.2. For the third base island 1.3, the central area of the front of the second base island 1.2 is sunken, and the chip 7 is arranged on the central sunken area of the front of the second base island 1.2 and the front of the third base island 1.3 through a conductive or non-conductive bonding substance 6 , in the peripheral area of the pin 2, the area between the pin 2 and the second base island 1.2, the back side of the third base island 1.3, the area between the back side of the second base island 1.2 and the second base island 1.2, the area between the second base island 1.2, The area between the back of the three-base island 1.3 and the pin 2 and the area between the pins are embedded with no filler molding compound 3, and the filler-free molding compound 3 connects the lower periphery of the pin, the pin 2 and the second pin. The lower part of the base island 1.2, the third base island 1.3, the third base island 1.3 and the lower part of the second base island 1.2, the back of the third base island 1.3 and the lower part of the pin 2 and the lower part of the pin 2 and the pin 2 are connected into one body, said Pin 2 is provided with a circle.

实施例13:下沉基岛露出型及多凸点基岛露出型单圈引脚Embodiment 13: Sunken base island exposed type and multi-bump base island exposed type single-turn pin

参见图37~39,图37(A)~图37(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例13各工序示意图。图38为本发明双面图形芯片正装单颗封装结构实施例13结构示意图。图39为图38的俯视图。由图37~39可以看出,实施例13与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第二基岛1.2,另一组为第四基岛1.4,所述第二基岛1.2正面中央区域下沉,第四基岛1.4正面设置成多凸点状结构,在所述第四基岛1.4和引脚2的正面设置第一金属层4,在所述第二基岛1.2、第四基岛1.4和引脚2的背面设置第二金属层5,在所述第二基岛1.2正面中央下沉区域和第四基岛1.4正面通过导电或不导电粘结物质6设置芯片7,在所述引脚2外围的区域、引脚2与第二基岛1.2之间的区域、第二基岛1.2与第四基岛1.4之间的区域、第四基岛1.4与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料的塑封料(环氧树脂)3将引脚下部外围、引脚2与第二基岛1.2下部、第二基岛1.2与第四基岛1.4下部、第四基岛1.4与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 37 to 39, Figures 37(A) to 37(R) are schematic diagrams of each process in Embodiment 13 of the double-sided graphics chip packaging method of the present invention, first plated and then engraved. Fig. 38 is a structural schematic diagram of Embodiment 13 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 39 is a top view of FIG. 38 . It can be seen from Figures 37 to 39 that the difference between Embodiment 13 and Embodiment 1 is that: the base island 1 has two groups or multiple groups of base islands, one group is the second base island 1.2, and the other group is the second base island 1.2. For the fourth base island 1.4, the central area of the front of the second base island 1.2 sinks, the front of the fourth base island 1.4 is arranged in a multi-convex structure, and the fourth base island 1.4 and the front of the pin 2 are provided with a A metal layer 4, a second metal layer 5 is provided on the back of the second base island 1.2, the fourth base island 1.4 and the pin 2, and the central sinking area and the fourth base island on the front of the second base island 1.2 1.4 The front side is provided with a chip 7 through a conductive or non-conductive adhesive substance 6, in the peripheral area of the pin 2, the area between the pin 2 and the second base island 1.2, the second base island 1.2 and the fourth base island 1.4 The area between, the area between the fourth base island 1.4 and the pin 2, and the area between the pin 2 and the pin 2 are embedded with a filler-free molding compound 3, and the filler-free molding compound (epoxy resin) 3 Connect the lower periphery of the pin, pin 2 and the lower part of the second base island 1.2, the second base island 1.2 and the lower part of the fourth base island 1.4, the fourth base island 1.4 and the lower part of the pin 2, and the lower part of the pin 2 and the pin 2 Connected as one, the pin 2 is provided with a circle.

实施例14:埋入型基岛及多凸点基岛露出型单圈引脚Embodiment 14: Embedded base island and multi-bump base island exposed single-turn pin

参见图40~42,图40(A)~图40(R)为本发明双面图形芯片正装先镀后刻单颗封装方法实施例14各工序示意图。41为本发明双面图形芯片正装单颗封装结构实施例14结构示意图。图42为41的俯视图。由图40~42可以看出,实施例14与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第三基岛1.3,另一组为第四基岛1.4,所述第四基岛1.4正面设置成多凸点状结构,在所述第三基岛1.3、第四基岛1.4和引脚2的正面设置第一金属层4,在所述第四基岛1.4和引脚2的背面设置第二金属层5,在所述引脚2外围的区域、引脚2与第四基岛1.4之间的区域、第三基岛1.3背面、第二基岛1.2与第四基岛1.4之间的区域、第三基岛1.3与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第四基岛1.4下部、第三基岛1.3背面、第三基岛1.3背面与第四基岛1.4下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 40-42, Figures 40(A)-40(R) are schematic diagrams of each process in Embodiment 14 of the double-sided graphics chip packaging method of the present invention. 41 is a structural schematic diagram of Embodiment 14 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 42 is a top view of 41 . It can be seen from Figures 40 to 42 that the difference between Embodiment 14 and Embodiment 1 is that: the base island 1 has two groups or multiple groups of base islands, one group is the third base island 1.3, and the other group is the third base island 1.3. It is the fourth base island 1.4, the front of the fourth base island 1.4 is arranged in a multi-bump structure, and the first metal layer 4 is arranged on the front of the third base island 1.3, the fourth base island 1.4 and the pin 2, The second metal layer 5 is arranged on the back of the fourth base island 1.4 and the pin 2, in the peripheral area of the pin 2, the area between the pin 2 and the fourth base island 1.4, the third base island 1.3 The backside, the area between the second base island 1.2 and the fourth base island 1.4, the area between the third base island 1.3 and the pin 2, and the area between the pins are embedded with no filler molding compound 3, so The filler-free molding compound 3 connects the lower periphery of the pin, the lower part of the pin 2 and the fourth base island 1.4, the back of the third base island 1.3, the back of the third base island 1.3 and the lower part of the fourth base island 1.4, and the back of the third base island 1.3 The lower part of the pin 2 and the lower part of the pin 2 are integrally connected, and the pin 2 is provided with a circle.

Claims (12)

1. a two-sided graphic chips formal dress plates earlier and afterwards carves single method for packing, and it is characterized in that: said method comprises following processing step:
Step 1, get metal substrate
Get the suitable metal substrate of a slice thickness,
Step 2, metal substrate front and back side lining photoresistance glued membrane
Utilization by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up electroplated metal layer process operation,
The positive photoresistance glued membrane of step 3, metal substrate needs the exposure of plated metal layer region/develop and windows
The metal substrate front that utilizes exposure imaging equipment that step 2 is accomplished photoresistance glued membrane lining operation is carried out exposure imaging and is removed part photoresistance glued membrane, carries out the zone of electroplated metal layer to expose the positive follow-up needs of metal substrate,
The zone of having windowed in step 4, metal substrate front is carried out metal level and is electroplated lining
The first metal layer plating lining is carried out in zone to having windowed in metal substrate front in the step 3, and this first metal layer places the front of Ji Dao and pin,
Photoresistance glued membrane striping is carried out at step 5, metal substrate front and the back side
The positive remaining photoresistance glued membrane of metal substrate and the photoresistance glued membrane at the metal substrate back side are all removed,
Step 6, metal substrate front and back side lining photoresistance glued membrane
Utilization by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up etch process operation,
The photoresistance glued membrane at step 7, the metal substrate back side needs the exposure of etching area/develop and windows
Exposure imaging removal part photoresistance glued membrane is carried out at the metal substrate back side that utilizes exposure imaging equipment that step 6 is accomplished photoresistance glued membrane lining operation, prepares against the metal substrate back etched operation that follow-up needs carry out to expose the localized metallic substrate,
Step 8, metal substrate carry out the back etched operation
After the exposure/development and windowing task of completing steps seven, promptly carry out the etching operation of each figure, etch the back side of Ji Dao and pin, simultaneously the pin front is extended to next door, basic island as much as possible at the back side of metal substrate,
Photoresistance glued membrane striping is carried out at step 9, metal substrate front and the back side
The photoresistance glued membrane that the metal substrate front and back is remaining all removes,
Step 10, seal packless plastic packaging material
Packless plastic packaging material operation is sealed at the metal substrate back side of completing steps nine said striping operations; And carry out the curing operation after plastic packaging material is sealed; Make zone and the zone between pin and the pin between Ji Dao and pin peripheral zone, pin and the basic island all set packless plastic packaging material; This packless plastic packaging material is peripheral with Ji Dao and pin bottom, pin bottom and Ji Dao bottom and pin bottom and pin bottom link into an integrated entity
Step 11, lining photoresistance glued membrane
Utilization by coating equipment in the front that will accomplish the metal substrate of sealing the operation of no filler plastic packaging material and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up etch process operation,
Step 12, the front of having accomplished the metal substrate of sealing the operation of no filler plastic packaging material need the exposure of etching area/develop and window
Exposure imaging removal part photoresistance glued membrane is carried out in the metal substrate front of sealing the operation of no filler plastic packaging material of accomplishing that utilizes exposure imaging equipment that step 11 is accomplished photoresistance glued membrane lining operation, carries out the operation of metal substrate front-side etch in order to follow-up needs,
Step 13, the operation of metal substrate front-side etch
After the exposure/development and windowing task of completing steps 12; Promptly carry out the etching operation of each figure in the metal substrate front that the operation of no filler plastic packaging material is sealed in completion; Etch the front of Ji Dao and pin; And make the positive size of the back side size of said Ji Dao and pin, form up big and down small Ji Dao and pin configuration less than Ji Dao and pin
Photoresistance glued membrane striping is carried out at step 14, metal substrate front and the back side
The positive remaining photoresistance glued membrane of the metal substrate of completing steps 13 etching operations and the photoresistance glued membrane at the metal substrate back side are all removed, process lead frame,
Step 15, load
On the first metal layer of front, basic island, carry out the implantation of chip through conduction or non-conductive bonding material,
Step 10 six, break metal wire
The semi-finished product of accomplishing chip implantation operation are carried out playing the metal wire operation between chip front side and the pin front the first metal layer,
Step 10 seven, be encapsulated with the filler plastic packaging material
The semi-finished product front that routing is accomplished is carried out local unit and is encapsulated with the operation of filler plastic packaging material; The positive local unit of pin zone is exposed the filler plastic packaging material is arranged; And carry out the curing operation after plastic packaging material is sealed; Make top and chip and the metal wire of Ji Dao and pin all had the filler plastic packaging material to seal outward
The back side of step 10 eight, Ji Dao and pin and the front of pin are carried out metal level and are electroplated lining
Completing steps 17 is encapsulated with the said positive local unit of the pin zones that the filler plastic packaging material is arranged of exposing of the back side and the step 10 seven of said Ji Dao and pin of filler plastic packaging material operation and carries out second metal level and the first metal layer respectively and electroplate the operation that is covered,
Step 10 nine, cutting finished product
The semi-finished product of ten eight the second metal levels of completing steps being electroplated lining carry out cutting operation, make originally more than of chips that connect together with array formula aggregate mode independent, make single encapsulating structure finished product of two-sided graphic chips formal dress.
2. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing, it is characterized in that Ji Dao (1) back side exposes said packless plastic packaging material (3).
3. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing, it is characterized in that Ji Dao (1) front middle section sinks.
4. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing, it is characterized in that Ji Dao (1) back side imbeds in the said packless plastic packaging material (3).
5. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing, it is characterized in that said Ji Dao (1) front is arranged to multi-convex point shape structure.
6. plate earlier according to one of them described a kind of two-sided graphic chips formal dress of claim 2~5 and afterwards carve single method for packing, it is a plurality of to it is characterized in that said Ji Dao (1) has, and pin (2) has individual pen.
7. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing; It is characterized in that said Ji Dao (1) has two groups; One group is first Ji Dao (1.1); Another group is second Ji Dao (1.2); Said second Ji Dao (1.2) front middle section sinks; Front at said first Ji Dao (1.1) and pin (2) is provided with the first metal layer (4); The back side at said first Ji Dao (1.1), second Ji Dao (1.2) and pin (2) is provided with second metal level (5); Be provided with chip (7) in positive central sunken regions of second Ji Dao (1.2) and first Ji Dao (1.1) front through conduction or non-conductive bonding material (6); Chip (7) positive with pin (2) front the first metal layer (4) between and all use metal wire (8) to be connected between chip (7) and the chip (7); Nos filler plastic packaging material (3) is set in zone between zone, second Ji Dao (1.2) and pin (2) between zone, first Ji Dao (1.1) and second Ji Dao (1.2) between peripheral zone, pin (2) and first Ji Dao (1.1) of said pin (2) and the zone between pin (2) and the pin (2), and said no filler plastic packaging material (3) links into an integrated entity periphery, pin bottom, pin (2) and first Ji Dao (1.1) bottom, first Ji Dao (1.1) and second Ji Dao (1.2) bottom, second Ji Dao (1.2) and pin (2) bottom and pin (2) and pin (2) bottom, and said pin (2) is provided with individual pen.
8. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing; It is characterized in that said Ji Dao (1) has two groups; One group is first Ji Dao (1.1); Another group is the 3rd Ji Dao (1.3); Front at said first Ji Dao (1.1) the 3rd Ji Dao (1.3) and pin (2) is provided with the first metal layer (4); The back side at said first Ji Dao (1.1) and pin (2) is provided with second metal level (5); Be provided with chip (7) in Ji Dao (1) front through conduction or non-conductive bonding material (6); Chip (7) positive with pin (2) front the first metal layer (4) between and all use metal wire (8) to be connected between chip (7) and the chip (7); Outside the top of said Ji Dao (1) and pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9); No filler plastic packaging material (3) is set in zone and the zone between pin and the pin between zone, the 3rd Ji Dao (1.3) and pin (2) between zone, the 3rd Ji Dao (1.3) back side, second Ji Dao (1.2) and first Ji Dao (1.1) between zone, pin (2) and first Ji Dao (1.1) of said pin (2) periphery, and said no filler plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with first Ji Dao (1.1) bottom, the 3rd Ji Dao (1.3) back side, the 3rd Ji Dao (1.3) back side and first Ji Dao (1.1) bottom, the 3rd Ji Dao (1.3) back side and pin (2) bottom and pin (2), and said pin (2) is provided with individual pen.
9. the method for packing of single encapsulating structure of a kind of two-sided graphic chips formal dress according to claim 1; It is characterized in that said Ji Dao (1) has two groups; One group is first Ji Dao (1.1); Another group is the 4th Ji Dao (1.4); Said the 4th Ji Dao (1.4) is arranged to multi-convex point shape structure in the front; No filler plastic packaging material (3) is set in zone between zone, the 4th Ji Dao (1.4) and pin (2) between zone, first Ji Dao (1.1) and the 4th Ji Dao (1.4) between zone, pin (2) and first Ji Dao (1.1) of said pin (2) periphery and the zone between pin (2) and the pin (2); Said packless plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with pin (2) bottom and pin (2) with the 4th Ji Dao (1.4) bottom, the 4th Ji Dao (1.4) with first Ji Dao (1.1) bottom, first Ji Dao (1.1), and said pin (2) is provided with individual pen.
10. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing; It is characterized in that said Ji Dao (1) has two groups also can be many group Ji Dao; One group is second Ji Dao (1.2); Another group is the 3rd Ji Dao (1.3); Said second Ji Dao (1.2) front middle section sinks; Be provided with chip (7) in positive central sunken regions of second Ji Dao (1.2) and the 3rd Ji Dao (1.3) front through conduction or non-conductive bonding material (6); No filler plastic packaging material (3) is set in zone and the zone between pin and the pin between zone, the 3rd Ji Dao (1.3) back side and pin (2) between zone, the 3rd Ji Dao (1.3) back side, the second Ji Dao back side (1.2) and second Ji Dao (1.2) between zone, pin (2) and second Ji Dao (1.2) of said pin (2) periphery; Said no filler plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with second Ji Dao (1.2) bottom, the 3rd Ji Dao (1.3) back side and pin (2) bottom and pin (2) with second Ji Dao (1.2) bottom, the 3rd Ji Dao (1.3), the 3rd Ji Dao (1.3), and said pin (2) is provided with individual pen.
11. plating earlier, a kind of two-sided graphic chips formal dress according to claim 1 afterwards carves single method for packing; It is characterized in that said Ji Dao (1) has two groups; One group is second Ji Dao (1.2); Another group is the 4th Ji Dao (1.4); Said second Ji Dao (1.2) front middle section sinks; The 4th Ji Dao (1.4) is arranged to multi-convex point shape structure in the front; Front at said the 4th Ji Dao (1.4) and pin (2) is provided with the first metal layer (4); The back side at said second Ji Dao (1.2), the 4th Ji Dao (1.4) and pin (2) is provided with second metal level (5), is provided with chip (7) in positive central sunken regions of said second Ji Dao (1.2) and the 4th Ji Dao (1.4) front through conduction or non-conductive bonding material (6), and no filler plastic packaging material (3) is set in zone between zone, the 4th Ji Dao (1.4) and pin (2) between zone, second Ji Dao (1.2) and the 4th Ji Dao (1.4) between zone, pin (2) and second Ji Dao (1.2) of said pin (2) periphery and the zone between pin (2) and the pin (2); Said packless plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with pin (2) bottom and pin (2) with the 4th Ji Dao (1.4) bottom, the 4th Ji Dao (1.4) with second Ji Dao (1.2) bottom, second Ji Dao (1.2), and said pin (2) is provided with individual pen.
12. plating earlier, a kind of two-sided graphic chips formal dress according to claim 1 afterwards carves single method for packing; It is characterized in that said Ji Dao (1) has two groups; One group is the 3rd Ji Dao (1.3); Another group is the 4th Ji Dao (1.4); Said the 4th Ji Dao (1.4) is arranged to multi-convex point shape structure in the front; Front at said the 3rd Ji Dao (1.3), the 4th Ji Dao (1.4) and pin (2) is provided with the first metal layer (4); The back side at said the 4th Ji Dao (1.4) and pin (2) is provided with second metal level (5); No filler plastic packaging material (3) is set in zone and the zone between pin and the pin between zone, the 3rd Ji Dao (1.3) and pin (2) between zone, the 3rd Ji Dao (1.3) back side, second Ji Dao (1.2) and the 4th Ji Dao (1.4) between zone, pin (2) and the 4th Ji Dao (1.4) of said pin (2) periphery, and said no filler plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with the 4th Ji Dao (1.4) bottom, the 3rd Ji Dao (1.3) back side, the 3rd Ji Dao (1.3) back side and the 4th Ji Dao (1.4) bottom, the 3rd Ji Dao (1.3) back side and pin (2) bottom and pin (2), and said pin (2) is provided with individual pen.
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CN102324413B (en) * 2011-09-13 2013-03-06 江苏长电科技股份有限公司 Sequentially etched and plated lead frame structure with island prepacked plastic sealed material and producing method thereof
CN102683315B (en) * 2011-11-30 2015-04-29 江苏长电科技股份有限公司 Barrel-plating four-side pinless packaging structure and manufacturing method thereof
CN102376672B (en) * 2011-11-30 2014-10-29 江苏长电科技股份有限公司 Foundation island-free ball grid array packaging structure and manufacturing method thereof
JP6489615B2 (en) * 2015-07-31 2019-03-27 大口マテリアル株式会社 Semiconductor element mounting substrate, semiconductor device and manufacturing method thereof
JP6460407B2 (en) * 2015-07-31 2019-01-30 大口マテリアル株式会社 Semiconductor element mounting substrate, semiconductor device and manufacturing method thereof
CN109427698B (en) * 2017-09-04 2023-08-29 恩智浦美国有限公司 Method for assembling QFP type semiconductor device
CN113192900A (en) * 2021-04-02 2021-07-30 江阴苏阳电子股份有限公司 Packaging process of packaging structure with etched back first

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101131982A (en) * 2007-09-13 2008-02-27 江苏长电科技股份有限公司 Footless packaging structure and packaging technology of semiconductor devices
WO2010036051A2 (en) * 2008-09-25 2010-04-01 Lg Innotek Co., Ltd. Structure and manufacture method for multi-row lead frame and semiconductor package
CN101770999A (en) * 2010-01-29 2010-07-07 江苏长电科技股份有限公司 External connection heat radiation cap encapsulation structure of positive installation lock hole heat radiation block projected post of base island embedded chip

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100784497B1 (en) * 2004-10-06 2007-12-11 삼성전자주식회사 Film package for semiconductor package and manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101131982A (en) * 2007-09-13 2008-02-27 江苏长电科技股份有限公司 Footless packaging structure and packaging technology of semiconductor devices
WO2010036051A2 (en) * 2008-09-25 2010-04-01 Lg Innotek Co., Ltd. Structure and manufacture method for multi-row lead frame and semiconductor package
CN101770999A (en) * 2010-01-29 2010-07-07 江苏长电科技股份有限公司 External connection heat radiation cap encapsulation structure of positive installation lock hole heat radiation block projected post of base island embedded chip

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