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CN101958305B - Double-sided graphics chip front-mount module packaging structure and packaging method - Google Patents

Double-sided graphics chip front-mount module packaging structure and packaging method Download PDF

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CN101958305B
CN101958305B CN2010102730299A CN201010273029A CN101958305B CN 101958305 B CN101958305 B CN 101958305B CN 2010102730299 A CN2010102730299 A CN 2010102730299A CN 201010273029 A CN201010273029 A CN 201010273029A CN 101958305 B CN101958305 B CN 101958305B
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packaging material
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CN101958305A (en
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王新潮
梁志忠
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

The invention relates to a double-side graph chip forward module package structure and a package method thereof. The structure comprises base islands (1), pins (2), unpacked molding compounds (epoxy resins) (3), conductive or non-conductive bonding materials (6), a chip (7), metal wires (8) and packed molding compounds (epoxy resins) (9), wherein the front sides of the pins (2) extend to draw near the base islands (1); and the unpacked molding compounds (3) connect the base islands (1) with the lower periphery of the pins, the lower parts of the pins (2) with the lower parts of the base islands (1), and the lower parts of the pins (2) into a whole and ensure the back size of the base islands and the pins to be less than the front size of the base islands and the pins to form a big end up base island and pin structure. The package structure is characterized in that columns (10) are arranged at the back of the pins (2) and the roots of the columns (10) are embedded in the unpacked molding compounds (3). The package structure can bear superhigh temperature during loading and can not undergo lead frame distorsion due to different physical properties of different substances, can avoid the problem of pin falling and can shorten the length of the metal wires.

Description

双面图形芯片正装模组封装结构及其封装方法Double-sided graphics chip front-mount module packaging structure and packaging method

(一)技术领域(1) Technical field

本发明涉及一种双面图形芯片正装模组封装结构及其封装方法。属于半导体封装技术领域。The invention relates to a package structure and a package method of a front-loading module for a double-sided graphics chip. It belongs to the technical field of semiconductor packaging.

(二)背景技术(2) Background technology

传统的芯片封装结构的制作方式是:采用金属基板的正面进行化学蚀刻及表面电镀层后,即完成引线框的制作(如图85所示)。而引线框的背面则在封装过程中再进行蚀刻。该法存在以下不足:The traditional manufacturing method of the chip packaging structure is: after chemical etching and surface electroplating are performed on the front side of the metal substrate, the production of the lead frame is completed (as shown in FIG. 85 ). The backside of the leadframe is etched during the packaging process. This law has the following shortcomings:

因为塑封前只在金属基板正面进行了半蚀刻工作,而在塑封过程中塑封料只有包裹住引脚半只脚的高度,所以塑封体与引脚的束缚能力就变小了,如果塑封体贴片到PCB板上不是很好时,再进行返工重贴,就容易产生掉脚的问题(如图86所示)。尤其塑封料的种类是采用有填料时候,因为材料在生产过程的环境与后续表面贴装的应力变化关系,会造成金属与塑封料产生垂直型的裂缝,其特性是填料比例越高则越硬越脆越容易产生裂缝。Because only half-etching work is done on the front of the metal substrate before plastic sealing, and the plastic sealing material is only half a foot high to cover the pins during the plastic sealing process, so the binding ability between the plastic package and the pins becomes smaller. If the plastic package is considerate When the chip is not well attached to the PCB board, rework and re-attachment will easily cause the problem of foot drop (as shown in Figure 86). Especially when the type of molding compound is filled, because the relationship between the environment of the material in the production process and the stress change of the subsequent surface mount will cause vertical cracks between the metal and the molding compound, the characteristic is that the higher the filler ratio, the harder it is The more brittle the easier it is to crack.

另外,由于芯片与引脚之间的距离较远,金属线的长度较长,如图87~88所示,金属线成本较高(尤其是昂贵的纯金质的金属线);同样由于金属线的长度较长,使得芯片的信号输出速度较慢(尤其是存储类的产品以及需要大量数据的计算,更为突出);也同样由于金属线的长度较长,所以在金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也较高;再由于芯片与引脚之间的距离较远,使得封装的体积与面积较大,材料成本较高,废弃物较多。In addition, due to the long distance between the chip and the pins, the length of the metal wire is relatively long, as shown in Figures 87-88, the cost of the metal wire is relatively high (especially the expensive pure gold metal wire); The length of the wire is longer, which makes the signal output speed of the chip slower (especially for storage products and calculations that require a large amount of data); The interference of parasitic resistance/capacitance and parasitic poles on the signal is also high; and because the distance between the chip and the pins is long, the volume and area of the package are large, the cost of materials is high, and there is more waste.

为此,本申请人在先申请了一件名称为《有基岛引线框结构及其生产方法》的发明专利,其申请号为:201010165896.0。其主要技术特征是:采用金属基板的背面先进行半蚀刻,在金属基板的背面形成凹陷的半蚀刻区域,同时相对形成基岛和引脚的背面,再在所述半蚀刻区域,填涂上无填料的软性填缝剂,并同时进行烘烤,使无填料的软性填缝剂固化成无填料的塑封料(环氧树脂),以包裹住引脚的背面。然后再在金属基板的正面进行半蚀刻,同时相对形成基岛和引脚的正面。其有益效果主要有:For this reason, the applicant previously applied for an invention patent titled "Based Island Lead Frame Structure and Its Production Method", and its application number is: 201010165896.0. Its main technical features are: use the back of the metal substrate to half-etch first, form a recessed half-etched area on the back of the metal substrate, and at the same time form the base island and the back of the pin relatively, and then fill and coat the half-etched area. Filler-free soft sealant, and bake at the same time, so that the filler-free soft sealant cures into a filler-free molding compound (epoxy resin) to wrap the backside of the pin. Then half etch is performed on the front side of the metal substrate, and at the same time, the base island and the front side of the pin are relatively formed. Its beneficial effects mainly include:

1)由于在所述金属基板的背面引脚与引脚间的区域嵌置有无填料的软性填缝剂,该无填料的软性填缝剂与在塑封过程中的金属基板正面的常规有填料塑封料(环氧树脂)一起包裹住整个引脚的高度,所以塑封体与引脚的束缚能力就变大了,不会再有产生掉脚的问题,如图89。1) Since the area between the pins and the pins on the back of the metal substrate is embedded with a soft sealant without filler, the soft sealant without filler is different from the conventional sealant on the front side of the metal substrate in the plastic sealing process. There is a filler plastic compound (epoxy resin) that covers the entire height of the pins together, so the binding capacity between the plastic package and the pins becomes larger, and there will be no problem of falling feet, as shown in Figure 89.

2)由于采用了引线框正面与背面分开蚀刻作业的方法,所以在蚀刻作业中可形成背面引脚的尺寸稍小而正面引脚尺寸稍大的结构,而同个引脚的上下大小不同尺寸在被无填料的塑封料(环氧树脂)所包裹的更紧更不容易产生滑动而掉脚。2) Due to the method of separate etching operations on the front and back of the lead frame, a structure in which the size of the back pins is slightly smaller and the size of the front pins is slightly larger can be formed during the etching operation, while the upper and lower sizes of the same pin are different It is tighter and less likely to slip and fall when it is wrapped by a filler-free molding compound (epoxy resin).

3)由于应用了引线框背面与正面分开蚀刻的技术,所以能够将引线框正面的引脚尽可能的延伸到基岛的旁边,促使芯片与引脚距离大幅的缩短,如图89~90,如此金属线所使用的成本也可以大幅的降低(尤其是昂贵的纯金质的金属线)。3) Due to the application of the technology of separately etching the back and front of the lead frame, the pins on the front of the lead frame can be extended to the side of the base island as much as possible, which greatly shortens the distance between the chip and the pins, as shown in Figures 89-90. The cost of such metal wires can also be greatly reduced (especially expensive pure gold metal wires).

4)也因为金属线的缩短使得芯片的信号输出速度也大幅的增速(尤其存储类的产品以及需要大量数据的计算,更为突出),由于金属线的长度变短了,所以金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也大幅度的降低。4) Also because of the shortening of the metal wire, the signal output speed of the chip is also greatly increased (especially for storage products and calculations that require a large amount of data), and because the length of the metal wire is shortened, the metal wire The interference of the existing parasitic resistance/capacitance and parasitic poles to the signal is also greatly reduced.

5)因运用了引脚的延伸技术,所以可以容易的制作出高脚数与高密度的脚之间的距离,使得封装的体积与面积可以大幅度的缩小。5) Due to the use of pin extension technology, the distance between high pin count and high density pins can be easily produced, so that the volume and area of the package can be greatly reduced.

6)因为将封装后的体积大幅度的缩小,更直接的体现出材料成本大幅度的下降与因为材料用量的减少也大幅度的减少废弃物环保的困扰。6) Because the volume after packaging is greatly reduced, it more directly reflects the substantial reduction of material costs and the reduction of material consumption also greatly reduces the environmental problems of waste and environmental protection.

但是,还是存在有以下的不足:由于封装前先进行引线框背面无填料塑封料的包裹引脚作业,再进行引线框正面的高温装片和打线作业时,因引线框和无填料塑封料两种材料的物理性能不同,两种材料的膨胀系数也不同,在高温下受热形变不同,导致后续装片时引线框产生扭曲。因此该种封装结构在装片时不能够耐超高温(200℃以上)。而以往是通过把封装体体积做得很大来达到耐高温的要求,但现在要求封装体的体积越来越小而功率是越来越大的情况下就耐不了超高温了。However, there are still following deficiencies: before encapsulation, the wrapping pin operation of the backside of the lead frame without filler molding compound is carried out, and when the high-temperature chip loading and wiring operations on the front of the lead frame are carried out, the lead frame and the filler-free plastic sealant The physical properties of the two materials are different, the coefficients of expansion of the two materials are also different, and the thermal deformation at high temperature is different, which leads to distortion of the lead frame during subsequent chip mounting. Therefore, this kind of packaging structure cannot withstand ultra-high temperature (above 200° C.) during chip loading. In the past, the requirement of high temperature resistance was achieved by making the volume of the package body large, but now the volume of the package body is required to be smaller and the power is larger and larger, and it cannot withstand ultra-high temperature.

(三)发明内容(3) Contents of the invention

本发明的目的在于克服上述不足,提供一种装片时可承受超高温且不会因不同物质的不同物理性质而产生引线框扭曲,也不会再有产生掉脚的问题和能使金属线的长度缩短的双面图形芯片正装模组封装结构及其封装方法。The purpose of the present invention is to overcome the above disadvantages, to provide a lead frame that can withstand ultra-high temperature during chip loading and will not cause distortion of the lead frame due to different physical properties of different substances, and will not cause the problem of falling feet and can make the metal wire The packaging structure and packaging method of the double-sided graphics chip front-loading module with shortened length.

本发明的目的是这样实现的:一种双面图形芯片正装模组封装结构,包括基岛、引脚、无填料的塑封料(环氧树脂)、导电或不导电粘结物质、芯片、金属线和有填料塑封料(环氧树脂),所述引脚正面延伸到基岛旁边,在所述基岛和引脚的正面设置有第一金属层,在所述基岛和引脚的背面设置有第二金属层,在所述基岛正面第一金属层上通过导电或不导电粘结物质设置有芯片,芯片正面与引脚正面第一金属层之间用金属线连接,在所述基岛和引脚的上部以及芯片和金属线外包封有填料塑封料(环氧树脂),在所述基岛和引脚外围的区域、引脚与基岛之间的区域以及引脚与引脚之间的区域嵌置有无填料的塑封料(环氧树脂),所述无填料的塑封料(环氧树脂)将基岛和引脚下部外围、引脚下部与基岛下部以及引脚下部与引脚下部连接成一体,且使所述基岛和引脚背面尺寸小于基岛和引脚正面尺寸,形成上大下小的基岛和引脚结构,其特征在于:在所述引脚背面设置有柱子,柱子根部埋入所述无填料的塑封料(环氧树脂)内。The object of the present invention is achieved like this: a kind of double-sided graphics chip front-loading module package structure, comprises base island, pin, no filler molding compound (epoxy resin), conductive or non-conductive bonding material, chip, metal wire and filled molding compound (epoxy resin), the front side of the pin extends to the side of the base island, the first metal layer is arranged on the front side of the base island and the pin, and the back side of the base island and the pin A second metal layer is provided, and a chip is provided on the first metal layer on the front side of the base island through a conductive or non-conductive adhesive substance, and the front side of the chip is connected with the first metal layer on the front side of the pin by a metal wire. The upper part of the base island and the pin, as well as the chip and the metal wire are encapsulated with filler molding compound (epoxy resin), and the area around the base island and the pin, the area between the pin and the base island, and the pin and the lead The area between the pins is embedded with an unfilled molding compound (epoxy) that connects the base island to the lower periphery of the pin, the lower portion of the pin to the lower portion of the base island, and the pin The lower part is integrated with the lower part of the pin, and the size of the base island and the back side of the pin is smaller than the size of the base island and the front side of the pin, forming a base island and pin structure with a large upper part and a smaller bottom part, which is characterized in that: in the lead A pillar is arranged on the back of the foot, and the root of the pillar is embedded in the plastic sealing compound (epoxy resin) without filler.

本发明双面图形芯片正装模组封装结构的封装方法,所述方法包括以下工艺步骤:The packaging method of the double-sided graphics chip front-mounted module packaging structure of the present invention, the method comprises the following process steps:

步骤一、取金属基板Step 1. Take the metal substrate

取一片厚度合适的金属基板,Take a piece of metal substrate with appropriate thickness,

步骤二、金属基板正面及背面被覆光阻胶膜Step 2. The front and back of the metal substrate are coated with photoresist film

利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜,Use coating equipment to cover the front and back of the metal substrate with a photoresist film that can be exposed and developed,

步骤三、金属基板正面的光阻胶膜进行需要电镀金属层区域的曝光/显影以及开窗Step 3: Expose/develop the photoresist film on the front of the metal substrate and open the window where the metal layer needs to be plated

利用曝光显影设备将步骤二完成光阻胶膜被覆作业的金属基板正面进行曝光显影去除部分光阻胶膜,以露出金属基板正面后续需要进行电镀金属层的区域,Use exposure and development equipment to expose and develop the front of the metal substrate that has completed the photoresist film coating operation in step 2 to remove part of the photoresist film to expose the area that needs to be electroplated on the front of the metal substrate.

步骤四、金属基板正面已开窗的区域进行金属层电镀被覆Step 4. Electroplating and coating the metal layer on the windowed area on the front of the metal substrate

对步骤三中金属基板正面已开窗的区域进行第一金属层电镀被覆,该第一金属层置于所述基岛与引脚的正面,The first metal layer is electroplated on the area where the window has been opened on the front of the metal substrate in step 3, and the first metal layer is placed on the front of the base island and the pin,

步骤五、金属基板正面及背面进行光阻胶膜去膜Step 5. Remove the photoresist film on the front and back of the metal substrate

将金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除,Remove the remaining photoresist film on the front of the metal substrate and the photoresist film on the back of the metal substrate.

步骤六、金属基板正面及背面被覆光阻胶膜Step 6. Cover the front and back of the metal substrate with photoresist film

利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜,以保护后续的蚀刻工艺作业,Use the coating equipment to cover the front and back of the metal substrate with a photoresist film that can be exposed and developed to protect the subsequent etching process.

步骤七、金属基板的光阻胶膜进行需要双面蚀刻区域的曝光/显影以及开窗Step 7. The photoresist film of the metal substrate is exposed/developed and opened in the area that needs to be etched on both sides

利用曝光显影设备将步骤六完成光阻胶膜被覆作业的金属基板正面及背面进行曝光显影去除部分光阻胶膜,以露出局部金属基板以备后续需要进行的金属基板双面蚀刻作业,Use the exposure and development equipment to expose and develop the front and back of the metal substrate that has completed the photoresist film coating operation in step 6 to remove part of the photoresist film, so as to expose a part of the metal substrate for the subsequent double-sided etching of the metal substrate.

步骤八、金属基板进行双面蚀刻作业Step 8. Metal substrate for double-sided etching

完成步骤七的曝光/显影以及开窗作业后,即在金属基板的正面及背面进行各图形的蚀刻作业,蚀刻出基岛和引脚的正面和背面,同时将引脚正面尽可能的延伸到基岛旁边,且使所述基岛和引脚的背面尺寸小于基岛和引脚的正面尺寸,形成上大下小的基岛和引脚结构;以及在引脚背面形成柱子,并在基岛与引脚之间以及引脚与引脚之间留有连筋,After completing the exposure/development and window opening operations in step 7, the etching operation of each pattern is carried out on the front and back of the metal substrate to etch the front and back of the base island and the pins, and at the same time extend the front of the pins as much as possible to the Next to the base island, and make the size of the back side of the base island and the pin smaller than the front size of the base island and the pin, forming a base island and pin structure with a large top and a small bottom; and forming a pillar on the back of the pin, and There are ribs between the island and the pin and between the pin and the pin,

步骤九、金属基板正面及背面进行光阻胶膜去膜Step 9. Remove the photoresist film on the front and back of the metal substrate

将金属基板正面和背面余下的光阻胶膜全部揭除,制成引线框,Remove all the remaining photoresist film on the front and back of the metal substrate to make a lead frame,

步骤十、装片Step ten, loading film

在步骤九制成的引线框的基岛正面第一金属层上通过导电或不导电粘结物质进行芯片的植入,On the first metal layer on the front side of the base island of the lead frame made in step 9, the chip is implanted through a conductive or non-conductive adhesive substance,

步骤十一、打金属线Step 11, hit the metal wire

将已完成芯片植入作业的半成品进行芯片正面与引脚正面第一金属层之间打金属线作业,The semi-finished product that has completed the chip implantation operation is put into the metal line operation between the front side of the chip and the first metal layer on the front side of the pin,

步骤十二、包封有填料塑封料(环氧树脂)Step 12. Encapsulate with filler molding compound (epoxy resin)

将已打线完成的半成品正面进行包封有填料塑封料(环氧树脂)9作业,并进行塑封料包封后的固化作业,使基岛和引脚的上部以及芯片和金属线外均被有填料塑封料(环氧树脂)包封,Encapsulate the front side of the semi-finished product that has been wired with filler molding compound (epoxy resin) 9, and perform curing operations after the molding compound is encapsulated, so that the base island and the upper part of the pin, as well as the outside of the chip and the metal wire are covered. Encapsulated with filler molding compound (epoxy resin),

步骤十三、被覆光阻胶膜Step 13: Coating photoresist film

利用被覆设备在将已完成包封有填料塑封料(环氧树脂)作业的半成品的正面及背面分别被覆可进行曝光显影的光阻胶膜和,以保护后续的蚀刻工艺作业,Use the coating equipment to cover the front and back of the semi-finished product that has been encapsulated with filler molding compound (epoxy resin) with a photoresist film that can be exposed and developed to protect the subsequent etching process.

步骤十四、已完成包封有填料塑封料(环氧树脂)作业的半成品的背面进行需要蚀刻区域的曝光/显影以及开窗Step 14. Expose/develop and open windows on the back of the semi-finished product that has been encapsulated with filler molding compound (epoxy resin)

利用曝光显影设备将步骤十三完成光阻胶膜被覆作业的已完成包封有填料塑封料作业的半成品背面进行曝光显影去除部分光阻胶膜,以露出步骤八金属基板双面蚀刻作业后留有的连筋以及在引脚背面形成的柱子,以备后续需要进行柱子根部和连筋蚀刻作业,Use exposure and development equipment to expose and develop the back of the semi-finished product that has completed the process of covering the photoresist film in step 13 and has completed the operation of encapsulating the filler plastic compound to remove part of the photoresist film to expose the metal substrate left after the double-sided etching operation in step 8. Some connecting ribs and pillars formed on the back of the pins are used for subsequent etching of the root of the pillars and connecting ribs,

步骤十五、第二次蚀刻作业Step fifteen, the second etching operation

完成步骤十四的曝光/显影以及开窗作业后,即在完成包封有填料塑封料(环氧树脂)作业的半成品背面进行各图形的蚀刻作业,将步骤八金属基板双面蚀刻作业后留有的连筋全部蚀刻掉,在这个过程中所述柱子的根部也会同时的蚀刻掉相对的厚度,使柱子根部不露出包封后的封装结构背面,After completing the exposure/development and window opening operations in step 14, the etching operation of each pattern is performed on the back of the semi-finished product that is encapsulated with filler molding compound (epoxy resin), and the metal substrate in step 8 is left after the double-sided etching operation. Some even ribs are all etched away, and in this process, the roots of the pillars will also be etched away to a relative thickness at the same time, so that the roots of the pillars do not expose the back of the encapsulated package structure.

步骤十六、半成品正面及背面进行光阻胶膜去膜Step 16. Remove the photoresist film on the front and back of the semi-finished product

将完成步骤十五蚀刻作业的半成品背面余下的光阻胶膜以及半成品正面的光阻胶膜全部揭除,Remove the remaining photoresist film on the back of the semi-finished product and the photoresist film on the front of the semi-finished product after completing the etching operation in step 15,

步骤十七、包封无填料的塑封料(环氧树脂)Step seventeen, encapsulating the plastic compound (epoxy resin) without filler

将已完成步骤十六所述去膜作业的半成品背面进行包封无填料的塑封料(环氧树脂)作业,并进行塑封料包封后的固化作业,使基岛和引脚外围的区域、引脚与基岛之间的区域以及引脚与引脚之间的区域均嵌置无填料的塑封料(环氧树脂),该无填料的塑封料(环氧树脂)将基岛和引脚下部外围、引脚下部与基岛下部以及引脚下部与引脚下部连接成一体,且使所述柱子根部埋入该无填料的塑封料(环氧树脂)内,Carry out the operation of encapsulating the plastic compound (epoxy resin) without filler on the back of the semi-finished product that has completed the film removal operation described in step 16, and perform the curing operation after the plastic compound encapsulation, so that the area around the base island and the pin, The area between the lead and the base island and the area between the lead and the lead are embedded with a filler-free molding compound (epoxy resin), and the filler-free molding compound (epoxy resin) connects the base island and the lead The periphery of the lower part, the lower part of the pin and the lower part of the base island, and the lower part of the pin and the lower part of the pin are connected into one body, and the root of the column is embedded in the plastic sealing compound (epoxy resin) without filler,

步骤十八、基岛和引脚的背面进行金属层电镀被覆Step 18, the base island and the back of the pin are electroplated with a metal layer

对已完成步骤十七包封无填料塑封料作业的所述基岛和引脚的背面进行第二金属层电镀被覆作业,Carrying out the second metal layer electroplating coating operation on the back of the base island and pins that have completed the operation of encapsulating the plastic compound without filler in step seventeen,

步骤十九、切割成品Step nineteen, cut the finished product

将已完成步骤十八第二金属层电镀被覆的半成品进行切割作业,使原本以列阵式集合体方式连在一起的芯片一颗颗独立开来,制得双面图形芯片正装模组封装结构成品。Cutting the semi-finished product that has completed the electroplating and coating of the second metal layer in step 18, so that the chips that were originally connected together in the form of an array assembly are separated one by one, and a double-sided graphics chip front-loading module package structure is obtained. finished product.

本发明的有益效果是:The beneficial effects of the present invention are:

1、引线框耐超高温(200℃以上)1. The lead frame is ultra-high temperature resistant (above 200°C)

由于采用了双面图形蚀刻引线框技术,一次完成引线框的正、背两面双面蚀刻,同时封装时先进行引线框正面的高温装片打线再进行引线框背面的引脚包裹作业,使装片打线时只有引线框一种材料,在使用超高温的制程过程中因没有多种材料膨胀系数不同所带来的冲击,确保了引线框的耐超高温(一般是200℃以下)性能。Due to the use of double-sided graphic etching lead frame technology, the front and back double-sided etching of the lead frame is completed at one time. At the same time, when packaging, the high-temperature chip mounting and wiring on the front of the lead frame is performed first, and then the pin wrapping operation on the back of the lead frame is performed. There is only one material of the lead frame for chip loading and wiring. In the ultra-high temperature process, there is no impact caused by the different expansion coefficients of various materials, which ensures the ultra-high temperature resistance (generally below 200°C) of the lead frame. .

2、能确保引线框装片强度2. It can ensure the strength of the lead frame

因为不先做预包封,引线框装片时承受的压力大,打线时会使引线框产生振动,引线框会出现下陷现象。本发明通过在引线框背面留有柱子的设计,以增加打线时引线框的强度。Because the pre-encapsulation is not done first, the pressure on the lead frame is high when the chip is loaded, and the lead frame will vibrate when the wire is bonded, and the lead frame will sag. The invention adopts the design of leaving pillars on the back of the lead frame to increase the strength of the lead frame when wiring.

3、确保不会再有产生掉脚的问题3. Make sure that there will be no more problems with feet falling

由于采用了双面蚀刻的工艺技术,所以可以轻松的规划设计与制造出上大下小的引脚结构,可以使上下层塑封料紧密的将上大下小的引脚结构一起包裹住,所以塑封体与引脚的束缚能力就变大了,不会再有产生掉脚的问题。Due to the use of double-sided etching technology, it is easy to plan, design and manufacture pin structures with upper and lower pins, and the upper and lower plastic molding compounds can tightly wrap the upper and lower pin structures together, so The binding ability between the plastic package and the pins becomes larger, and there will be no more problems of falling feet.

4、确保金属线的长度缩短4. Make sure the length of the metal wire is shortened

1)由于应用了引线框背面与正面同时且分开蚀刻的技术,所以能够将引线框正面的引脚尽可能的延伸到后续需装芯片的区域旁边,促使芯片与引脚距离大幅的缩短,如图89~图90,如此金属线的长度也缩短了,金属线的成本也可以大幅的降低(尤其是昂贵的纯金质的金属线);1) Due to the application of the technology of simultaneous and separate etching on the back and front of the lead frame, the pins on the front of the lead frame can be extended as far as possible to the side of the area where the chip needs to be installed later, which greatly shortens the distance between the chip and the pin, such as As shown in Fig. 89-90, the length of the metal wire is also shortened, and the cost of the metal wire can be greatly reduced (especially the expensive pure gold metal wire);

2)也因为金属线的长度缩短使得芯片的信号输出速度也大幅的增速(尤其存储类的产品以及需要大量数据的计算,更为突出),由于金属线的长度变短了,所以金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也大幅度的降低。2) Also because the length of the metal wire is shortened, the signal output speed of the chip is also greatly increased (especially for storage products and calculations that require a large amount of data). The interference of the existing parasitic resistance/capacitance and parasitic poles to the signal is also greatly reduced.

5、使封装的体积与面积可以大幅度的缩小5. The volume and area of the package can be greatly reduced

因运用了引脚的延伸技术,所以可以容易的制作出高脚数与高密度的脚与脚之间的距离,使得封装的体积与面积可以大幅度的缩小。Due to the use of pin extension technology, it is easy to produce a high number of pins and a high-density pin-to-pin distance, so that the volume and area of the package can be greatly reduced.

6、材料成本和材料用量减少6. Reduced material cost and material consumption

因为将封装后的体积大幅度的缩小,更直接的体现出材料成本大幅度的下降与因为材料用量的减少也大幅度的减少废弃物环保的困扰。Because the volume after packaging is greatly reduced, it more directly reflects the substantial reduction in material costs and the reduction in the amount of materials used also greatly reduces the problem of waste and environmental protection.

(四)附图说明(4) Description of drawings

图1(A)~图1(R)为本发明双面图形芯片正装模组封装方法实施例1各工序示意图。FIG. 1(A) to FIG. 1(R) are schematic diagrams of each process in Embodiment 1 of the front-mount module packaging method for double-sided graphics chips of the present invention.

图2为本发明双面图形芯片正装模组封装结构实施例1结构示意图。FIG. 2 is a structural schematic diagram of Embodiment 1 of the packaging structure of a double-sided graphics chip front-mount module of the present invention.

图3为图2的俯视图。FIG. 3 is a top view of FIG. 2 .

图4(A)~图4(R)为本发明双面图形芯片正装模组封装方法实施例2各工序示意图。4(A) to 4(R) are schematic diagrams of each process in Embodiment 2 of the front-mount module packaging method for double-sided graphics chips of the present invention.

图5为本发明双面图形芯片正装模组封装结构实施例2结构示意图。FIG. 5 is a structural schematic diagram of Embodiment 2 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图6为图5的俯视图。FIG. 6 is a top view of FIG. 5 .

图7(A)~图7(R)为本发明双面图形芯片正装模组封装方法实施例3各工序示意图。7(A) to 7(R) are schematic diagrams of each process in Embodiment 3 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图8为本发明双面图形芯片正装模组封装结构实施例3结构示意图。FIG. 8 is a structural schematic diagram of Embodiment 3 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.

图9为图8的俯视图。FIG. 9 is a top view of FIG. 8 .

图10(A)~图10(R)为本发明双面图形芯片正装模组封装方法实施例4各工序示意图。10(A) to 10(R) are schematic diagrams of each process in Embodiment 4 of the front-mount module packaging method for double-sided graphics chips of the present invention.

图11为本发明双面图形芯片正装模组封装结构实施例4结构示意图。FIG. 11 is a structural schematic diagram of Embodiment 4 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图12为图11的俯视图。FIG. 12 is a top view of FIG. 11 .

图13(A)~图13(R)为本发明双面图形芯片正装模组封装方法实施例5各工序示意图。13(A) to 13(R) are schematic diagrams of each process in Embodiment 5 of the packaging method of a double-sided graphic chip front-mount module of the present invention.

图14为本发明双面图形芯片正装模组封装结构实施例5结构示意图。FIG. 14 is a structural schematic diagram of Embodiment 5 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.

图15为图14的俯视图。FIG. 15 is a top view of FIG. 14 .

图16(A)~图16(R)为本发明双面图形芯片正装模组封装方法实施例6各工序示意图。16(A) to 16(R) are schematic diagrams of each process in Embodiment 6 of the front-mount module packaging method for double-sided graphics chips of the present invention.

图17为本发明双面图形芯片正装模组封装结构实施例6结构示意图。FIG. 17 is a structural schematic diagram of Embodiment 6 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图18为图17的俯视图。FIG. 18 is a top view of FIG. 17 .

图19(A)~图19(R)为本发明双面图形芯片正装模组封装方法实施例7各工序示意图。19(A) to 19(R) are schematic diagrams of each process in Embodiment 7 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图20为本发明双面图形芯片正装模组封装结构实施例7结构示意图。FIG. 20 is a structural schematic diagram of Embodiment 7 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.

图21为图20的俯视图。FIG. 21 is a top view of FIG. 20 .

图22(A)~图22(R)为本发明双面图形芯片正装模组封装方法实施例8各工序示意图。22(A) to 22(R) are schematic diagrams of each process in Embodiment 8 of the packaging method for a double-sided graphic chip front-mount module of the present invention.

图23为本发明双面图形芯片正装模组封装结构实施例8结构示意图。Fig. 23 is a structural schematic diagram of Embodiment 8 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图24为图23的俯视图。FIG. 24 is a top view of FIG. 23 .

图25(A)~图25(R)为本发明双面图形芯片正装模组封装方法实施例9各工序示意图。25(A) to 25(R) are schematic diagrams of each process in Embodiment 9 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图26为本发明双面图形芯片正装模组封装结构实施例9结构示意图。Fig. 26 is a structural schematic diagram of Embodiment 9 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图27为图26的俯视图。FIG. 27 is a top view of FIG. 26 .

图28(A)~图28(R)为本发明双面图形芯片正装模组封装方法实施例10各工序示意图。28(A) to 28(R) are schematic diagrams of each process in Embodiment 10 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图29为本发明双面图形芯片正装模组封装结构实施例10结构示意图。Fig. 29 is a structural schematic diagram of Embodiment 10 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.

图30为图29的俯视图。FIG. 30 is a top view of FIG. 29 .

图31(A)~图31(R)为本发明双面图形芯片正装模组封装方法实施例11各工序示意图。31(A) to 31(R) are schematic diagrams of each process in Embodiment 11 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图32为本发明双面图形芯片正装模组封装结构实施例11结构示意图。FIG. 32 is a structural schematic diagram of Embodiment 11 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图33为图32的俯视图。FIG. 33 is a top view of FIG. 32 .

图34(A)~图34(R)为本发明双面图形芯片正装模组封装方法实施例12各工序示意图。34(A) to 34(R) are schematic diagrams of each process in Embodiment 12 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图35为本发明双面图形芯片正装模组封装结构实施例12结构示意图。Fig. 35 is a structural schematic diagram of Embodiment 12 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.

图36为图35的俯视图。FIG. 36 is a top view of FIG. 35 .

图37(A)~图37(R)为本发明双面图形芯片正装模组封装方法实施例13各工序示意图。37(A) to 37(R) are schematic diagrams of each process in Embodiment 13 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图38为本发明双面图形芯片正装模组封装结构实施例13结构示意图。Fig. 38 is a structural schematic diagram of Embodiment 13 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.

图39为图38的俯视图。FIG. 39 is a top view of FIG. 38 .

图40(A)~图40(R)为本发明双面图形芯片正装模组封装方法实施例14各工序示意图。40(A) to 40(R) are schematic diagrams of each process in Embodiment 14 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图41为本发明双面图形芯片正装模组封装结构实施例14结构示意图。Fig. 41 is a structural schematic diagram of Embodiment 14 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.

图42为图41的俯视图。FIG. 42 is a top view of FIG. 41 .

图43(A)~图43(R)为本发明双面图形芯片正装模组封装方法实施例15各工序示意图。43(A) to 43(R) are schematic diagrams of each process in Embodiment 15 of the packaging method of a double-sided graphic chip front-mount module of the present invention.

图44为本发明双面图形芯片正装模组封装结构实施例15结构示意图。Fig. 44 is a structural schematic diagram of Embodiment 15 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图45为图44的俯视图。FIG. 45 is a top view of FIG. 44 .

图46(A)~图46(R)为本发明双面图形芯片正装模组封装方法实施例16各工序示意图。46(A) to 46(R) are schematic diagrams of each process in Embodiment 16 of the front-mount module packaging method for double-sided graphics chips of the present invention.

图47为本发明双面图形芯片正装模组封装结构实施例16结构示意图。Fig. 47 is a structural schematic diagram of Embodiment 16 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图48为图47的俯视图。FIG. 48 is a top view of FIG. 47 .

图49(A)~图49(R)为本发明双面图形芯片正装模组封装方法实施例17各工序示意图。49(A) to 49(R) are schematic diagrams of each process in Embodiment 17 of the method for packaging a front-mount module for a double-sided graphic chip according to the present invention.

图50为本发明双面图形芯片正装模组封装结构实施例17结构示意图。Fig. 50 is a structural schematic diagram of Embodiment 17 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图51为图50的俯视图。FIG. 51 is a top view of FIG. 50 .

图52(A)~图52(R)为本发明双面图形芯片正装模组封装方法实施例18各工序示意图。52(A) to 52(R) are schematic diagrams of each process in Embodiment 18 of the front-mount module packaging method for double-sided graphics chips of the present invention.

图53为本发明双面图形芯片正装模组封装结构实施例18结构示意图。Fig. 53 is a structural schematic diagram of Embodiment 18 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图54为图53的俯视图。FIG. 54 is a top view of FIG. 53 .

图55(A)~图55(R)为本发明双面图形芯片正装模组封装方法实施例19各工序示意图。55(A) to 55(R) are schematic diagrams of each process in Embodiment 19 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图56为本发明双面图形芯片正装模组封装结构实施例19结构示意图。Fig. 56 is a structural schematic diagram of Embodiment 19 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.

图57为图56的俯视图。FIG. 57 is a top view of FIG. 56 .

图58(A)~图58(R)为本发明双面图形芯片正装模组封装方法实施例20各工序示意图。58(A) to 58(R) are schematic diagrams of each process in Embodiment 20 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图59为本发明双面图形芯片正装模组封装结构实施例20结构示意图。Fig. 59 is a structural schematic diagram of Embodiment 20 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图60为图59的俯视图。FIG. 60 is a top view of FIG. 59 .

图61(A)~图61(R)为本发明双面图形芯片正装模组封装方法实施例21各工序示意图。61(A) to 61(R) are schematic diagrams of each process in Embodiment 21 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图62为本发明双面图形芯片正装模组封装结构实施例21结构示意图。Fig. 62 is a structural schematic diagram of Embodiment 21 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图63为图62的俯视图。FIG. 63 is a top view of FIG. 62 .

图64(A)~图64(R)为本发明双面图形芯片正装模组封装方法实施例22各工序示意图。64(A) to 64(R) are schematic diagrams of each process in Embodiment 22 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图65为本发明双面图形芯片正装模组封装结构实施例22结构示意图。Fig. 65 is a structural schematic diagram of Embodiment 22 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图66为图65的俯视图。FIG. 66 is a top view of FIG. 65 .

图67(A)~图67(R)为本发明双面图形芯片正装模组封装方法实施例23各工序示意图。67(A) to 67(R) are schematic diagrams of each process in Embodiment 23 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图68为本发明双面图形芯片正装模组封装结构实施例23结构示意图。Fig. 68 is a structural schematic diagram of Embodiment 23 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图69为图68的俯视图。FIG. 69 is a top view of FIG. 68 .

图70(A)~图70(R)为本发明双面图形芯片正装模组封装方法实施例24各工序示意图。70(A) to 70(R) are schematic diagrams of each process in Embodiment 24 of the front-mount module packaging method for double-sided graphic chips of the present invention.

图71为本发明双面图形芯片正装模组封装结构实施例24结构示意图。Fig. 71 is a structural schematic diagram of Embodiment 24 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.

图72为图71的俯视图。FIG. 72 is a top view of FIG. 71 .

图73(A)~图73(R)为本发明双面图形芯片正装模组封装方法实施例25各工序示意图。73(A) to 73(R) are schematic diagrams of each process in Embodiment 25 of the packaging method for a double-sided graphic chip front-mount module of the present invention.

图74为本发明双面图形芯片正装模组封装结构实施例25结构示意图。Fig. 74 is a structural schematic diagram of Embodiment 25 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图75为图74的俯视图。FIG. 75 is a top view of FIG. 74 .

图76(A)~图76(R)为本发明双面图形芯片正装模组封装方法实施例26各工序示意图。76(A) to 76(R) are schematic diagrams of each process of the twenty-sixth embodiment of the front-mount module packaging method for double-sided graphics chips of the present invention.

图77为本发明双面图形芯片正装模组封装结构实施例26结构示意图。Fig. 77 is a structural schematic diagram of Embodiment 26 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.

图78为图77的俯视图。FIG. 78 is a top view of FIG. 77 .

图79(A)~图79(R)为本发明双面图形芯片正装模组封装方法实施例27各工序示意图。79(A) to 79(R) are schematic diagrams of each process in Embodiment 27 of the front-mount module packaging method for double-sided graphics chips of the present invention.

图80为本发明双面图形芯片正装模组封装结构实施例27结构示意图。Fig. 80 is a structural schematic diagram of Embodiment 27 of the package structure of a double-sided graphic chip front-mount module of the present invention.

图81为图80的俯视图。FIG. 81 is a top view of FIG. 80 .

图82(A)~图82(R)为本发明双面图形芯片正装模组封装方法实施例28各工序示意图。82(A) to 82(R) are schematic diagrams of each process in Embodiment 28 of the front-mount module packaging method for double-sided graphics chips of the present invention.

图83为本发明双面图形芯片正装模组封装结构实施例28结构示意图。Fig. 83 is a structural schematic diagram of Embodiment 28 of the package structure of the double-sided graphic chip front-mount module of the present invention.

图84为图83的俯视图。FIG. 84 is a top view of FIG. 83 .

图85为以往采用金属基板的正面进行化学蚀刻及表面电镀层作业图。Fig. 85 is a working diagram of chemical etching and surface electroplating on the front side of a metal substrate in the past.

图86为以往形成的掉脚图。Fig. 86 is a diagram of a footfall formed in the past.

图87为以往的封装结构一示意图。Fig. 87 is a schematic diagram of a conventional package structure.

图88为87的俯视图。Figure 88 is a top view of 87.

图89为以往的封装结构二示意图。FIG. 89 is a schematic diagram of a second conventional package structure.

图90为89的俯视图。Figure 90 is a top view of 89.

图中附图标记:Reference signs in the figure:

基岛1、引脚2、无填料的塑封料(环氧树脂)3、第一金属层4、第二金属层5、导电或不导电粘结物质6、芯片7、金属线8、有填料塑封料(环氧树脂)9、柱子10、金属基板11、光阻胶膜12、光阻胶膜13、光阻胶膜14、光阻胶膜15、连筋16、光阻胶膜17、光阻胶膜18;第三基岛1.1、第三基岛1.2、第三基岛1.3、第四基岛1.4。Base island 1, pins 2, molding compound without filler (epoxy resin) 3, first metal layer 4, second metal layer 5, conductive or non-conductive bonding substance 6, chip 7, metal wire 8, with filler Molding compound (epoxy resin) 9, pillar 10, metal substrate 11, photoresist film 12, photoresist film 13, photoresist film 14, photoresist film 15, ribs 16, photoresist film 17, Photoresist film 18; third base island 1.1, third base island 1.2, third base island 1.3, fourth base island 1.4.

(五)具体实施方式(5) Specific implementation methods

本发明双面图形芯片正装模组封装结构及其封装方法如下:The packaging structure and packaging method of the double-sided graphics chip front-loading module of the present invention are as follows:

实施例1:单基岛单圈引脚Example 1: Single base island single turn pin

参见图2和图3,图2为本发明双面图形芯片正装模组封装结构实施例1结构示意图。图3为图2的俯视图。由图2和图3可以看出,本发明双面图形芯片正装模组封装结构,包括基岛1、引脚2、无填料的塑封料(环氧树脂)3、导电或不导电粘结物质6、芯片7、金属线8和有填料塑封料(环氧树脂)9,所述引脚2正面延伸到基岛1旁边,在所述基岛1和引脚2的正面设置有第一金属层4,在所述基岛1和引脚2的背面设置有第二金属层5,在所述基岛1正面第一金属层4上通过导电或不导电粘结物质6设置有芯片7,芯片7正面与引脚2正面第一金属层4之间用金属线8连接,在所述基岛1和引脚2的上部以及芯片7和金属线8外包封有填料塑封料(环氧树脂)9,在所述基岛1和引脚2外围的区域、引脚2与基岛1之间的区域以及引脚2与引脚2之间的区域嵌置有无填料的塑封料(环氧树脂)3,所述无填料的塑封料(环氧树脂)3将基岛1和引脚下部外围、引脚2下部与基岛1下部以及引脚2下部与引脚2下部连接成一体,且使所述基岛和引脚背面尺寸小于基岛和引脚正面尺寸,形成上大下小的基岛和引脚结构,在所述引脚2背面设置有柱子10,柱子10根部埋入所述无填料的塑封料(环氧树脂)3内。Referring to FIG. 2 and FIG. 3 , FIG. 2 is a structural schematic diagram of Embodiment 1 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 3 is a top view of FIG. 2 . As can be seen from Fig. 2 and Fig. 3, the double-sided graphics chip front-loading module packaging structure of the present invention includes a base island 1, pins 2, plastic encapsulant (epoxy resin) 3 without filler, conductive or non-conductive bonding substance 6. Chip 7, metal wire 8 and filler molding compound (epoxy resin) 9, the front side of the pin 2 extends to the side of the base island 1, and the front side of the base island 1 and the pin 2 is provided with a first metal layer 4, a second metal layer 5 is provided on the back of the base island 1 and pins 2, and a chip 7 is provided on the first metal layer 4 on the front of the base island 1 through a conductive or non-conductive adhesive substance 6, The front of the chip 7 is connected with the first metal layer 4 on the front of the pin 2 with a metal wire 8, and the top of the base island 1 and the pin 2, as well as the chip 7 and the metal wire 8 are encapsulated with a filler molding compound (epoxy resin ) 9, the area between the base island 1 and the pin 2 periphery, the area between the pin 2 and the base island 1, and the area between the pin 2 and the pin 2 are embedded with a filler-free molding compound (ring Oxygen resin) 3, the filler-free molding compound (epoxy resin) 3 connects the base island 1 and the periphery of the lower part of the pin, the lower part of the pin 2 and the lower part of the base island 1, and the lower part of the pin 2 and the lower part of the pin 2 into one , and make the size of the base island and the back of the pin smaller than the size of the base island and the front of the pin to form a base island and pin structure with a large top and a small bottom. A pillar 10 is arranged on the back of the pin 2, and the roots of the pillar 10 are buried Put it into the molding compound (epoxy resin) 3 without filler.

其封装方法如下:Its packaging method is as follows:

步骤一、取金属基板Step 1. Take the metal substrate

参见图1(A),取一片厚度合适的金属基板11。金属基板的材质可以依据芯片的功能与特性进行变换,例如:铜、铝、铁、铜合金或镍铁合金等。Referring to FIG. 1(A), take a metal substrate 11 with a suitable thickness. The material of the metal substrate can be changed according to the functions and characteristics of the chip, for example: copper, aluminum, iron, copper alloy or nickel-iron alloy.

步骤二、金属基板正面及背面被覆光阻胶膜Step 2. The front and back of the metal substrate are coated with photoresist film

参见图1(B),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜12和13,以保护后续的电镀金属层工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(B), the front and back sides of the metal substrate are covered with photoresist films 12 and 13 that can be exposed and developed by coating equipment to protect the subsequent electroplating metal layer process. The photoresist film can be a dry photoresist thin film or a wet photoresist film.

步骤三、金属基板正面的光阻胶膜进行需要电镀金属层区域的曝光/显影以及开窗Step 3: Expose/develop the photoresist film on the front of the metal substrate and open the window where the metal layer needs to be plated

参见图1(C),利用曝光显影设备将步骤二完成光阻胶膜被覆作业的金属基板正面进行曝光显影去除部分光阻胶膜,以露出金属基板正面后续需要进行电镀金属层的区域。Referring to FIG. 1(C), use exposure and development equipment to expose and develop the front of the metal substrate that has completed the photoresist film coating operation in step 2 to remove part of the photoresist film to expose the area on the front of the metal substrate that needs to be subsequently electroplated with a metal layer.

步骤四、金属基板正面已开窗的区域进行金属层电镀被覆Step 4. Electroplating and coating the metal layer on the windowed area on the front of the metal substrate

参见图1(D),对步骤三中金属基板正面已开窗的区域进行第一金属层4电镀被覆,该第一金属层4置于所述基岛1与引脚2的正面。Referring to FIG. 1(D), the first metal layer 4 is electroplated on the area where the window has been opened on the front side of the metal substrate in step 3, and the first metal layer 4 is placed on the front side of the base island 1 and the pin 2 .

步骤五、金属基板正面及背面进行光阻胶膜去膜Step 5. Remove the photoresist film on the front and back of the metal substrate

参见图1(E),将金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除。Referring to FIG. 1(E), remove the remaining photoresist film on the front side of the metal substrate and the photoresist film on the back side of the metal substrate.

步骤六、金属基板正面及背面被覆光阻胶膜Step 6. Cover the front and back of the metal substrate with photoresist film

参见图1(F),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜14和15,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(F), the front and back sides of the metal substrate are coated with photoresist films 14 and 15 that can be exposed and developed by coating equipment to protect the subsequent etching process. The photoresist film can be a dry photoresist thin film or a wet photoresist film.

步骤七、金属基板的光阻胶膜进行需要双面蚀刻区域的曝光/显影以及开窗Step 7. The photoresist film of the metal substrate is exposed/developed and opened in the area that needs to be etched on both sides

参见图1(G),利用曝光显影设备将步骤六完成光阻胶膜被覆作业的金属基板正面及背面进行曝光显影去除部分光阻胶膜,以露出局部金属基板以备后续需要进行的金属基板双面蚀刻作业。Referring to Figure 1(G), use the exposure and development equipment to expose and develop the front and back of the metal substrate that has completed the photoresist film coating operation in step 6 to remove part of the photoresist film to expose a part of the metal substrate for subsequent metal substrates Double-sided etching work.

步骤八、金属基板进行双面蚀刻作业Step 8. Metal substrate for double-sided etching

参见图1(H),完成步骤七的曝光/显影以及开窗作业后,即在金属基板的正面及背面进行各图形的蚀刻作业,蚀刻出基岛1和引脚2的正面和背面,同时将引脚正面尽可能的延伸到基岛旁边,且使所述基岛1和引脚2的背面尺寸小于基岛1和引脚2的正面尺寸,形成上大下小的基岛1和引脚2结构;以及在引脚2背面形成柱子10,并在基岛1与引脚2之间和引脚2与引脚2之间留有连筋16。Referring to Fig. 1(H), after completing the exposure/development and window opening operation in step 7, the etching operation of each pattern is carried out on the front and back of the metal substrate, and the front and back of the base island 1 and pin 2 are etched, and at the same time Extend the front of the pins to the side of the base island as much as possible, and make the size of the back of the base island 1 and the pin 2 smaller than the front size of the base island 1 and the pin 2, forming a base island 1 and a lead with a large top and a small bottom. The pin 2 structure; and a column 10 is formed on the back of the pin 2, and a rib 16 is left between the base island 1 and the pin 2 and between the pin 2 and the pin 2.

步骤九、金属基板正面及背面进行光阻胶膜去膜Step 9. Remove the photoresist film on the front and back of the metal substrate

参见图1(I),将金属基板正面和背面余下的光阻胶膜全部揭除,制成引线框,Referring to Figure 1 (I), the remaining photoresist films on the front and back of the metal substrate are all removed to form a lead frame.

步骤十、装片Step ten, loading film

参见图1(J),在基岛1正面第一金属层4上通过导电或不导电粘结物质6进行芯片7的植入。Referring to FIG. 1(J), the chip 7 is implanted on the first metal layer 4 on the front side of the base island 1 through a conductive or non-conductive adhesive substance 6 .

步骤十一、打金属线Step 11, hit the metal wire

参见图1(K),将已完成芯片植入作业的半成品进行芯片正面与引脚正面第一金属层之间打金属线8作业。Referring to FIG. 1(K), the semi-finished product that has completed the chip implantation operation is subjected to the metal wire 8 operation between the front side of the chip and the first metal layer on the front side of the pin.

步骤十二、包封有填料塑封料(环氧树脂)Step 12. Encapsulate with filler molding compound (epoxy resin)

参见图1(L),将已打线完成的半成品正面进行包封有填料塑封料(环氧树脂)9作业,并进行塑封料包封后的固化作业,使基岛和引脚的上部以及芯片和金属线外均被有填料塑封料(环氧树脂)包封。Referring to Figure 1(L), the front side of the semi-finished product that has been wired is encapsulated with filler molding compound (epoxy resin) 9, and the curing operation is performed after the molding compound is encapsulated, so that the base island and the upper part of the pin and Both the chip and the metal wire are encapsulated by a filler plastic compound (epoxy resin).

步骤十三、被覆光阻胶膜Step 13: Coating photoresist film

参见图1(M),利用被覆设备在将已完成包封有填料塑封料(环氧树脂)作业的半成品的正面及背面分别被覆可进行曝光显影的光阻胶膜17和18,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(M), the front and back of the semi-finished product that has been encapsulated with filler molding compound (epoxy resin) are coated with photoresist films 17 and 18 that can be exposed and developed by coating equipment to protect subsequent etching process work. The photoresist film can be a dry photoresist thin film or a wet photoresist film.

步骤十四、已完成包封有填料塑封料(环氧树脂)作业的半成品的背面进行需要蚀刻区域的曝光/显影以及开窗Step 14. Expose/develop and open windows on the back of the semi-finished product that has been encapsulated with filler molding compound (epoxy resin)

参见图1(N),利用曝光显影设备将步骤十三完成光阻胶膜被覆作业的已完成包封有填料塑封料(环氧树脂)作业的半成品背面进行曝光显影去除部分光阻胶膜,以露出步骤八金属基板双面蚀刻作业后留有的连筋16以及在引脚2背面形成的柱子10,以备后续需要进行柱子根部和连筋蚀刻作业。Referring to Fig. 1(N), use the exposure and development equipment to expose and develop the back of the semi-finished product that has completed the coating operation of the photoresist film in step 13 and has completed the operation of encapsulating the filler molding compound (epoxy resin) to remove part of the photoresist film. In order to expose the connecting ribs 16 left after the double-sided etching of the metal substrate in step 8 and the pillars 10 formed on the back of the pins 2, in preparation for subsequent etching operations on the root of the pillars and the connecting ribs.

步骤十五、第二次蚀刻作业Step fifteen, the second etching operation

参见图1(O),完成步骤十四的曝光/显影以及开窗作业后,即在完成包封有填料塑封料(环氧树脂)作业的半成品背面进行各图形的蚀刻作业,将步骤八金属基板双面蚀刻作业后留有的连筋16全部蚀刻掉,在这个过程中所述柱子10的根部也会同时的蚀刻掉相对的厚度,使柱子根部不露出包封后的封装结构背面,避免产生断路。Referring to Figure 1(O), after completing the exposure/development and window opening operations in step fourteen, the etching operation of each pattern is performed on the back of the semi-finished product that is encapsulated with filler molding compound (epoxy resin), and the step eight metal The ribs 16 left after the double-sided etching of the substrate are all etched away. During this process, the roots of the pillars 10 will also be etched away to a relative thickness at the same time, so that the roots of the pillars do not expose the back of the encapsulated package structure, avoiding A circuit break occurs.

步骤十六、半成品正面及背面进行光阻胶膜去膜Step 16. Remove the photoresist film on the front and back of the semi-finished product

参见图1(P),将完成步骤十五蚀刻作业的半成品背面余下的光阻胶膜以及半成品正面的光阻胶膜全部揭除。Referring to FIG. 1(P), the remaining photoresist film on the back of the semi-finished product and the photoresist film on the front of the semi-finished product after the etching operation in step 15 are all removed.

步骤十七、包封无填料的塑封料(环氧树脂)Step seventeen, encapsulating the plastic compound (epoxy resin) without filler

参见图1(Q),将已完成步骤十六所述去膜作业的半成品背面进行包封无填料的塑封料(环氧树脂)作业,并进行塑封料包封后的固化作业,使基岛1和引脚2外围的区域、引脚2与基岛1之间的区域以及引脚2与引脚2之间的区域均嵌置无填料的塑封料(环氧树脂)3,该无填料的塑封料(环氧树脂)3将基岛1和引脚下部外围、引脚2下部与基岛1下部以及引脚2下部与引脚2下部连接成一体,且使所述柱子10根部埋入该无填料的塑封料(环氧树脂)3内。Referring to Figure 1(Q), the back of the semi-finished product that has completed the film removal operation described in step 16 is encapsulated with a filler-free molding compound (epoxy resin), and the curing operation is performed after the molding compound is encapsulated, so that the base island 1 and the peripheral area of pin 2, the area between pin 2 and base island 1, and the area between pin 2 and pin 2 are all embedded with no filler molding compound (epoxy resin) 3, the filler-free The molding compound (epoxy resin) 3 connects the base island 1 and the periphery of the lower part of the pin, the lower part of the pin 2 and the lower part of the base island 1, and the lower part of the pin 2 and the lower part of the pin 2, and makes the 10 roots of the pillars buried Put it into the molding compound (epoxy resin) 3 without filler.

特别说明:但也因为多了所述柱子10在封装体内,反而在封装体内的结构更为强壮了(好比混泥土中增加了钢筋又有强度又有韧性)Special note: but also because there are many pillars 10 in the package, the structure in the package is stronger (like adding steel bars to concrete, which has both strength and toughness)

步骤十八、基岛和引脚的背面进行金属层电镀被覆Step 18, the base island and the back of the pin are electroplated with a metal layer

参见图1(R),对已完成步骤十七包封无填料塑封料作业的所述基岛和引脚的背面进行第二金属层5电镀被覆作业,而电镀的材料可以是锡、镍金、镍钯金....等金属材质。Referring to Fig. 1 (R), the second metal layer 5 electroplating coating operation is carried out on the back side of the base island and pins that have completed the operation of encapsulating the no-filler molding compound in step 17, and the electroplating material can be tin, nickel gold , nickel palladium gold.... and other metal materials.

步骤十九、切割成品Step nineteen, cut the finished product

参见图2和图3,将已完成步骤十八第二金属层电镀被覆的半成品进行切割作业,使原本以列阵式集合体方式连在一起的芯片一颗颗独立开来,制得双面图形芯片正装模组封装结构成品。Referring to Figure 2 and Figure 3, the semi-finished product that has completed the electroplating and coating of the second metal layer in step 18 is cut, so that the chips that were originally connected together in the form of an array assembly are separated one by one to obtain a double-sided The finished product of the graphics chip front-mounted module package structure.

实施例2:下沉基岛露出型单圈引脚Embodiment 2: sunken base island exposed type single-turn pin

参见图4~6,图4(A)~图4(R)为本发明双面图形芯片正装模组封装方法实施例2各工序示意图。图5为本发明双面图形芯片正装模组封装结构实施例2结构示意图。图6为图5的俯视图。由图4、图5和图6可以看出,实施例2与实施例1的不同之处仅在于:所述基岛1为下沉型基岛,即基岛1正面中央区域下沉。Referring to Figures 4-6, Figures 4(A)-4(R) are schematic diagrams of each process in Embodiment 2 of the packaging method for a double-sided graphic chip front-mount module of the present invention. FIG. 5 is a structural schematic diagram of Embodiment 2 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 6 is a top view of FIG. 5 . It can be seen from FIG. 4 , FIG. 5 and FIG. 6 that the only difference between Embodiment 2 and Embodiment 1 is that the base island 1 is a sunken base island, that is, the central area of the front of the base island 1 is sunken.

实施例3:埋入型基岛单圈引脚Embodiment 3: Embedded base island single-turn pin

参见图7~9,图7(A)~图7(R)为本发明双面图形芯片正装模组封装方法实施例3各工序示意图。图8为本发明双面图形芯片正装模组封装结构实施例3结构示意图。图9为图8的俯视图。由图7、图8和图9可以看出,实施例3与实施例1的不同之处仅在于:所述基岛1为埋入型基岛,即基岛1背面埋入所述无填料的塑封料(环氧树脂)3内。Referring to FIGS. 7 to 9, FIGS. 7(A) to 7(R) are schematic diagrams of each process in Embodiment 3 of the packaging method for a double-sided graphic chip front-mount module of the present invention. FIG. 8 is a structural schematic diagram of Embodiment 3 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 9 is a top view of FIG. 8 . It can be seen from Fig. 7, Fig. 8 and Fig. 9 that the only difference between Embodiment 3 and Embodiment 1 is that the base island 1 is an embedded type base island, that is, the back of the base island 1 is embedded with the non-filler The molding compound (epoxy resin) 3 inside.

实施例4:多凸点基岛露出型单圈引脚Embodiment 4: Multi-bump base island exposed single-turn pin

参见图10~12,图10(A)~图10(R)为本发明双面图形芯片正装模组封装方法实施例4各工序示意图。图11为本发明双面图形芯片正装模组封装结构实施例4结构示意图。图12为图11的俯视图。由图10、图11和图12可以看出,实施例4与实施例1的不同之处仅在于:所述基岛1为多凸点基岛,即基岛1表面设置有多个凸点。Referring to Figures 10-12, Figures 10(A)-10(R) are schematic diagrams of each process in Embodiment 4 of the front-mount module packaging method for double-sided graphic chips of the present invention. FIG. 11 is a structural schematic diagram of Embodiment 4 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 12 is a top view of FIG. 11 . It can be seen from Figure 10, Figure 11 and Figure 12 that the difference between Embodiment 4 and Embodiment 1 is that the base island 1 is a multi-bump base island, that is, the surface of the base island 1 is provided with multiple bumps .

实施例5:基岛露出型多圈引脚Embodiment 5: Base island exposed multi-turn pin

参见图13~15,图13(A)~图13(R)为本发明双面图形芯片正装模组封装方法实施例5各工序示意图。图14为本发明双面图形芯片正装模组封装结构实施例5结构示意图。图15为图14的俯视图。由图13~15可以看出,实施例5与实施例1的不同之处在于:所述引脚2有多圈。Referring to Figures 13-15, Figures 13(A)-13(R) are schematic diagrams of each process in Embodiment 5 of the front-mount module packaging method for double-sided graphic chips of the present invention. FIG. 14 is a structural schematic diagram of Embodiment 5 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 15 is a top view of FIG. 14 . It can be seen from FIGS. 13-15 that the difference between Embodiment 5 and Embodiment 1 lies in that the pin 2 has multiple turns.

实施例6:下沉基岛露出型多圈引脚Embodiment 6: sunken base island exposed multi-turn pin

参见图16~18,图16(A)~图16(R)为本发明双面图形芯片正装模组封装方法实施例6各工序示意图。图17为本发明双面图形芯片正装模组封装结构实施例6结构示意图。图18为图17的俯视图。由图16~18可以看出,实施例6与实施例2的不同之处在于:所述引脚2有多圈。Referring to Figures 16-18, Figures 16(A)-16(R) are schematic diagrams of each process in Embodiment 6 of the front-mount module packaging method for double-sided graphic chips of the present invention. FIG. 17 is a structural schematic diagram of Embodiment 6 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 18 is a top view of FIG. 17 . It can be seen from FIGS. 16-18 that the difference between Embodiment 6 and Embodiment 2 lies in that the pin 2 has multiple turns.

实施例7:埋入型基岛多圈引脚Embodiment 7: Embedded base island multi-turn pin

参见图19~21,图19(A)~图19(R)为本发明双面图形芯片正装模组封装方法实施例7各工序示意图。图20为本发明双面图形芯片正装模组封装结构实施例7结构示意图。图21为图20的俯视图。由图19~21可以看出,实施例7与实施例3的不同之处在于:所述引脚2有多圈。Referring to Figures 19-21, Figures 19(A)-19(R) are schematic diagrams of each process in Embodiment 7 of the packaging method of a double-sided graphic chip front-mount module of the present invention. FIG. 20 is a structural schematic diagram of Embodiment 7 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 21 is a top view of FIG. 20 . It can be seen from FIGS. 19-21 that the difference between Embodiment 7 and Embodiment 3 lies in that the pin 2 has multiple turns.

实施例8:多凸点基岛露出型多圈引脚Embodiment 8: multi-bump base island exposed multi-turn pin

参见图22~24,图22(A)~图22(R)为本发明双面图形芯片正装模组封装方法实施例8各工序示意图。图23为本发明双面图形芯片正装模组封装结构实施例8结构示意图。图24为图23的俯视图。由图22~24可以看出,实施例8与实施例4的不同之处在于:所述引脚2有多圈。Referring to Figures 22-24, Figures 22(A)-22(R) are schematic diagrams of each process in Embodiment 8 of the front-mount module packaging method for double-sided graphic chips of the present invention. Fig. 23 is a structural schematic diagram of Embodiment 8 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 24 is a top view of FIG. 23 . It can be seen from FIGS. 22 to 24 that the difference between Embodiment 8 and Embodiment 4 lies in that the pin 2 has multiple turns.

实施例9:多个基岛露出型单圈引脚Embodiment 9: Multiple base island exposed single-turn pins

参见图25~27,图25(A)~图25(R)为本发明双面图形芯片正装模组封装方法实施例9各工序示意图。图26为本发明双面图形芯片正装模组封装结构实施例9结构示意图。图27为图26的俯视图。由图25~27可以看出,实施例9与实施例1的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 25-27, Figures 25(A)-25(R) are schematic diagrams of each process in Embodiment 9 of the front-mount module packaging method for double-sided graphic chips of the present invention. Fig. 26 is a structural schematic diagram of Embodiment 9 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 27 is a top view of FIG. 26 . It can be seen from FIGS. 25 to 27 that the difference between Embodiment 9 and Embodiment 1 lies in that: there are multiple base islands 1 , and the pin 2 has a single turn.

实施例10:多个下沉基岛露出型单圈引脚Embodiment 10: Multiple sunken base island exposed single-turn pins

参见图28~30,图28(A)~图28(R)为本发明双面图形芯片正装模组封装方法实施例10各工序示意图。图29为本发明双面图形芯片正装模组封装结构实施例10结构示意图。图30为图29的俯视图。由图28~30可以看出,实施例10与实施例2的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 28-30, Figures 28(A)-28(R) are schematic diagrams of each process in Embodiment 10 of the front-mount module packaging method for double-sided graphics chips of the present invention. Fig. 29 is a structural schematic diagram of Embodiment 10 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 30 is a top view of FIG. 29 . It can be seen from FIGS. 28 to 30 that the difference between Embodiment 10 and Embodiment 2 lies in that: there are multiple base islands 1 , and the pin 2 has a single turn.

实施例11:多个埋入型基岛单圈引脚Example 11: Multiple Buried Base Island Single Turn Pins

参见图31~33,图31(A)~图31(R)为本发明双面图形芯片正装模组封装方法实施例11各工序示意图。图32为本发明双面图形芯片正装模组封装结构实施例11结构示意图。图33为图32的俯视图。由图31~33可以看出,实施例11与实施例3的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 31-33, Figures 31(A)-31(R) are schematic diagrams of each process in Embodiment 11 of the packaging method of a double-sided graphic chip front-mount module of the present invention. FIG. 32 is a structural schematic diagram of Embodiment 11 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 33 is a top view of FIG. 32 . It can be seen from FIGS. 31 to 33 that the difference between Embodiment 11 and Embodiment 3 lies in that: there are multiple base islands 1 , and the pin 2 has a single turn.

实施例12:多个多凸点基岛露出型单圈引脚Embodiment 12: Multiple multi-bump base island exposed single-turn pins

参见图34~36,图34(A)~图34(R)为本发明双面图形芯片正装模组封装方法实施例12各工序示意图。图35为本发明双面图形芯片正装模组封装结构实施例12结构示意图。图36为图35的俯视图。由图34~36可以看出,实施例12与实施例4的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 34 to 36, Figures 34(A) to 34(R) are schematic diagrams of each process in Embodiment 12 of the method for packaging a double-sided graphic chip front-mount module according to the present invention. Fig. 35 is a structural schematic diagram of Embodiment 12 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 36 is a top view of FIG. 35 . It can be seen from FIGS. 34 to 36 that the difference between Embodiment 12 and Embodiment 4 lies in that: there are multiple base islands 1 , and the pin 2 has a single turn.

实施例13:多个基岛露出型多圈引脚Embodiment 13: Multiple base island exposed multi-turn pins

参见图37~39,图37(A)~图37(R)为本发明双面图形芯片正装模组封装方法实施例13各工序示意图。图38为本发明双面图形芯片正装模组封装结构实施例13结构示意图。图39为图38的俯视图。由图37~39可以看出,实施例13与实施例1的不同之处在于:所述基岛1有多个,引脚2有多圈。Referring to Figures 37 to 39, Figures 37(A) to 37(R) are schematic diagrams of each process in Embodiment 13 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 38 is a structural schematic diagram of Embodiment 13 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 39 is a top view of FIG. 38 . It can be seen from FIGS. 37 to 39 that the difference between Embodiment 13 and Embodiment 1 is that there are multiple base islands 1 and pins 2 have multiple turns.

实施例14:多个下沉基岛露出型多圈引脚Embodiment 14: Exposed multi-turn pins with multiple sinking base islands

参见图40~42,图40(A)~图40(R)为本发明双面图形芯片正装模组封装方法实施例14各工序示意图。图41为本发明双面图形芯片正装模组封装结构实施例14结构示意图。图42为图41的俯视图。由图40~42可以看出,实施例14与实施例2的不同之处在于:所述基岛1有多个,引脚2有多圈。Referring to Figures 40-42, Figures 40(A)-40(R) are schematic diagrams of each process in Embodiment 14 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 41 is a structural schematic diagram of Embodiment 14 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 42 is a top view of FIG. 41 . It can be seen from FIGS. 40 to 42 that the difference between Embodiment 14 and Embodiment 2 lies in that there are multiple base islands 1 and pins 2 have multiple turns.

实施例15:多个埋入型基岛多圈引脚Example 15: Multiple Buried Base Island Multiturn Pins

参见图43~45,图43(A)~图43(R)为本发明双面图形芯片正装模组封装方法实施例15各工序示意图。图44为本发明双面图形芯片正装模组封装结构实施例15结构示意图。图45为图44的俯视图。由图43~45可以看出,实施例15与实施例3的不同之处在于:所述基岛1有多个,引脚2有多圈。Referring to Figures 43-45, Figures 43(A)-43(R) are schematic diagrams of each process in Embodiment 15 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 44 is a structural schematic diagram of Embodiment 15 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 45 is a top view of FIG. 44 . It can be seen from FIGS. 43 to 45 that the difference between Embodiment 15 and Embodiment 3 lies in that there are multiple base islands 1 and pins 2 have multiple turns.

实施例16:多个多凸点基岛露出型多圈引脚Embodiment 16: Multiple multi-bump base island exposed multi-turn pins

参见图46~48,图46(A)~图46(R)为本发明双面图形芯片正装模组封装方法实施例16各工序示意图。图47为本发明双面图形芯片正装模组封装结构实施例16结构示意图。图48为图47的俯视图。由图46~48可以看出,实施例16与实施例4的不同之处在于:所述基岛1有多个,引脚2有多圈。Referring to Figures 46-48, Figures 46(A)-46(R) are schematic diagrams of each process in Embodiment 16 of the front-mount module packaging method for double-sided graphics chips of the present invention. Fig. 47 is a structural schematic diagram of Embodiment 16 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 48 is a top view of FIG. 47 . It can be seen from FIGS. 46 to 48 that the difference between Embodiment 16 and Embodiment 4 lies in that: there are multiple base islands 1 , and the pins 2 have multiple turns.

实施例17:基岛露出型及下沉基岛露出型单圈引脚Embodiment 17: base island exposed type and sunken base island exposed type single-turn pin

参见图49~51,图49(A)~图49(R)为本发明双面图形芯片正装模组封装方法实施例17各工序示意图。图50为本发明双面图形芯片正装模组封装结构实施例17结构示意图。图51为图50的俯视图。由图49~51可以看出,实施例17与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第二基岛1.2,所述第二基岛1.2正面中央区域下沉,在所述第一基岛1.1和引脚2的正面设置第一金属层4,在所述第一基岛1.1、第二基岛1.2和引脚2的背面设置第二金属层5,在第二基岛1.2正面中央下沉区域和第一基岛1.1正面通过导电或不导电粘结物质6设置芯片7,芯片7正面与引脚2正面第一金属层4之间以及芯片7与芯片7之间均用金属线8连接,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第一基岛1.1与第二基岛1.2之间的区域、第二基岛1.2与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第一基岛1.1下部、第一基岛1.1与第二基岛1.2下部、第二基岛1.2与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2有单圈。Referring to Figures 49-51, Figures 49(A)-49(R) are schematic diagrams of each process in Embodiment 17 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 50 is a structural schematic diagram of Embodiment 17 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 51 is a top view of FIG. 50 . It can be seen from Figures 49 to 51 that the difference between Embodiment 17 and Embodiment 1 is that: the base island 1 has two groups or multiple groups of base islands, one group is the first base island 1.1, and the other group is the first base island 1.1. For the second base island 1.2, the central area of the front of the second base island 1.2 sinks, and the first metal layer 4 is set on the front of the first base island 1.1 and the pin 2, and on the first base island 1.1, The second metal layer 5 is arranged on the back of the second base island 1.2 and the pin 2, and the chip 7 is arranged on the central sunken area of the front of the second base island 1.2 and the front of the first base island 1.1 through a conductive or non-conductive bonding substance 6, the chip 7. Both the front side and the first metal layer 4 on the front side of the pin 2 and between the chip 7 and the chip 7 are connected with a metal wire 8, in the peripheral area of the pin 2, between the pin 2 and the first base island 1.1 The area between the first base island 1.1 and the second base island 1.2, the area between the second base island 1.2 and pin 2, and the area between pin 2 and pin 2 are embedded with filler-free molding compound 3. The filler-free molding compound 3 connects the periphery of the lower part of the pin, the lower part of the pin 2 and the first base island 1.1, the lower part of the first base island 1.1 and the second base island 1.2, the second base island 1.2 and the lower part of the pin 2, and Pin 2 is integrally connected with the lower part of pin 2, said pin 2 has a single turn.

实施例18:基岛露出型及下沉基岛露出型多圈引脚Embodiment 18: Multi-turn pins with exposed base island and sunken base island exposed type

参见图52~54,图52(A)~图52(R)为本发明双面图形芯片正装模组封装方法实施例18各工序示意图。图53为本发明双面图形芯片正装模组封装结构实施例18结构示意图。图54为图53的俯视图。由图52~54可以看出,实施例18与实施例17的不同之处在于:所述引脚2有多圈。Referring to Figures 52-54, Figures 52(A)-52(R) are schematic diagrams of each process in Embodiment 18 of the front-mount module packaging method for double-sided graphic chips of the present invention. Fig. 53 is a structural schematic diagram of Embodiment 18 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 54 is a top view of FIG. 53 . It can be seen from FIGS. 52-54 that the difference between Embodiment 18 and Embodiment 17 lies in that the pin 2 has multiple turns.

实施例19:基岛露出型及埋入型基岛单圈引脚Embodiment 19: base island exposed type and embedded type base island single-turn pin

参见图55~57,图55(A)~图55(R)为本发明双面图形芯片正装模组封装方法实施例19各工序示意图。图56为本发明双面图形芯片正装模组封装结构实施例19结构示意图。图57为图56的俯视图。由图55~57可以看出,实施例19与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第三基岛1.3,在所述第一基岛1.1第三基岛1.3和引脚2的正面设置第一金属层4,在所述第一基岛1.1和引脚2的背面设置第二金属层5,芯片7正面与引脚2正面第一金属层4之间以及芯片7与芯片7之间均用金属线8连接,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第三基岛1.3背面、第三基岛1.3与第一基岛1.1之间的区域、第三基岛1.3与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第一基岛1.1下部、第三基岛1.3背面、第三基岛1.3背面与第一基岛1.1下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有单圈。Referring to Figures 55-57, Figures 55(A)-55(R) are schematic diagrams of each process in Embodiment 19 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 56 is a structural schematic diagram of Embodiment 19 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 57 is a top view of FIG. 56 . It can be seen from Figures 55 to 57 that the difference between Embodiment 19 and Embodiment 1 is that: the base island 1 has two or more groups of base islands, one group is the first base island 1.1, and the other group is the first base island 1.1. For the third base island 1.3, the first metal layer 4 is arranged on the front of the first base island 1.1, the third base island 1.3 and the pin 2, and the second metal layer 4 is arranged on the back of the first base island 1.1 and the pin 2. The metal layer 5, the front of the chip 7 and the first metal layer 4 on the front of the pin 2 and between the chip 7 and the chip 7 are all connected with a metal wire 8. In the area around the pin 2, the pin 2 and the first Area between base island 1.1, back of third base island 1.3, area between third base island 1.3 and first base island 1.1, area between third base island 1.3 and pin 2, and pin to pin Filler-free molding compound 3 is embedded in the area between, and the filler-free molding compound 3 connects the lower periphery of the pin, the pin 2 and the lower part of the first base island 1.1, the back of the third base island 1.3, and the back of the third base island 1.3 and The lower part of the first base island 1.1, the back of the third base island 1.3 and the lower part of the pin 2 and the lower part of the pin 2 are connected as a whole, and the pin 2 is provided with a single loop.

实施例20:基岛露出型及埋入型基岛多圈引脚Embodiment 20: base island exposed type and embedded type base island multi-turn pin

参见图58~60,图58(A)~图58(R)为本发明双面图形芯片正装模组封装方法实施例20各工序示意图。图59为本发明双面图形芯片正装模组封装结构实施例20结构示意图。图60为图59的俯视图。由图58~60可以看出,实施例20与实施例19的不同之处在于:所述引脚(2)有多圈。Referring to Figures 58-60, Figures 58(A)-58(R) are schematic diagrams of each process in Embodiment 20 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 59 is a structural schematic diagram of Embodiment 20 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 60 is a top view of FIG. 59 . It can be seen from Figures 58-60 that the difference between Embodiment 20 and Embodiment 19 lies in that the pin (2) has multiple turns.

实施例21:基岛露出型及多凸点基岛露出型单圈引脚Embodiment 21: Exposed base island type and multi-bump base island exposed type single-turn pin

参见图61~63,图61(A)~图61(R)为本发明双面图形芯片正装模组封装方法实施例21各工序示意图。图62为本发明双面图形芯片正装模组封装结构实施例21结构示意图。图63为图62的俯视图。由图61~63可以看出,实施例21与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第四基岛1.4,所述第四基岛1.4正面设置成多凸点状结构,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第一基岛1.1与第四基岛1.4之间的区域、第四基岛1.4与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料的塑封料(环氧树脂)3将引脚下部外围、引脚2与第一基岛1.1下部、第一基岛1.1与第四基岛1.4下部、第四基岛1.4与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有单圈。Referring to Figures 61-63, Figures 61(A)-61(R) are schematic diagrams of each process in Embodiment 21 of the front-mount module packaging method for double-sided graphic chips of the present invention. Fig. 62 is a structural schematic diagram of Embodiment 21 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 63 is a top view of FIG. 62 . It can be seen from Figures 61 to 63 that the difference between Embodiment 21 and Embodiment 1 is that: the base island 1 has two or more groups of base islands, one group is the first base island 1.1, and the other group is the first base island 1.1. It is the fourth base island 1.4, the front side of the fourth base island 1.4 is arranged in a multi-bump structure, in the area around the pin 2, the area between the pin 2 and the first base island 1.1, the first base island 1.1 The area between the island 1.1 and the fourth base island 1.4, the area between the fourth base island 1.4 and the pin 2, and the area between the pin 2 and the pin 2 are embedded with filler-free molding compound 3, the filler-free The plastic encapsulant (epoxy resin) 3 connects the lower periphery of the pin, the lower part of the pin 2 and the first base island 1.1, the lower part of the first base island 1.1 and the fourth base island 1.4, the fourth base island 1.4 and the lower part of the pin 2, and The pin 2 is integrally connected with the lower part of the pin 2, and the pin 2 is provided with a single circle.

实施例22:基岛露出型及多凸点基岛露出型多圈引脚Embodiment 22: Base island exposed type and multi-bump base island exposed multi-turn pin

参见图64~66,图64(A)~图64(R)为本发明双面图形芯片正装模组封装方法实施例22各工序示意图。图65为本发明双面图形芯片正装模组封装结构实施例22结构示意图。图66为图65的俯视图。由图64~66可以看出,实施例22与实施例21的不同之处在于:所述引脚2有多圈。Referring to Figures 64-66, Figures 64(A)-64(R) are schematic diagrams of each process in Embodiment 22 of the front-mount module packaging method for double-sided graphics chips of the present invention. Fig. 65 is a structural schematic diagram of Embodiment 22 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 66 is a top view of FIG. 65 . It can be seen from FIGS. 64 to 66 that the difference between Embodiment 22 and Embodiment 21 lies in that the pin 2 has multiple turns.

实施例23:下沉基岛露出型及埋入型基岛露出型单圈引脚Embodiment 23: sunken base island exposed type and buried base island exposed type single-turn pin

参见图67~69,图67(A)~图67(R)为本发明双面图形芯片正装模组封装方法实施例23各工序示意图。图68为本发明双面图形芯片正装模组封装结构实施例23结构示意图。图69为图68的俯视图。由图67~69可以看出,实施例23与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第二基岛1.2,另一组为第三基岛1.3,所述第二基岛1.2正面中央区域下沉,在第二基岛1.2正面中央下沉区域和第三基岛1.3正面通过导电或不导电粘结物质6设置芯片7,在所述引脚2外围的区域、引脚2与第二基岛1.2之间的区域、第三基岛1.3背面、第二基岛背面1.2与第二基岛1.2之间的区域、第三基岛1.3背面与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第二基岛1.2下部、第三基岛1.3、第三基岛1.3与第二基岛1.2下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 67-69, Figures 67(A)-67(R) are schematic diagrams of each process in Embodiment 23 of the front-mount module packaging method for double-sided graphics chips of the present invention. Fig. 68 is a structural schematic diagram of Embodiment 23 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 69 is a top view of FIG. 68 . It can be seen from Figures 67 to 69 that the difference between Embodiment 23 and Embodiment 1 is that: the base island 1 has two groups or multiple groups of base islands, one group is the second base island 1.2, and the other group is the second base island 1.2. For the third base island 1.3, the central area of the front of the second base island 1.2 is sunken, and the chip 7 is arranged on the central sunken area of the front of the second base island 1.2 and the front of the third base island 1.3 through a conductive or non-conductive bonding substance 6 , in the peripheral area of the pin 2, the area between the pin 2 and the second base island 1.2, the back side of the third base island 1.3, the area between the back side of the second base island 1.2 and the second base island 1.2, the area between the second base island 1.2, The area between the back of the three-base island 1.3 and the pin 2 and the area between the pins are embedded with no filler molding compound 3, and the filler-free molding compound 3 connects the lower periphery of the pin, the pin 2 and the second pin. The lower part of the base island 1.2, the third base island 1.3, the third base island 1.3 and the lower part of the second base island 1.2, the back of the third base island 1.3 and the lower part of the pin 2 and the lower part of the pin 2 and the pin 2 are connected into one body, said Pin 2 is provided with a circle.

实施例24:下沉基岛露出型及埋入型基岛露出型多圈引脚Embodiment 24: sunken base island exposed type and buried base island exposed multi-turn pin

参见图70~72,图70(A)~图70(R)为本发明双面图形芯片正装模组封装方法实施例24各工序示意图。图71为本发明双面图形芯片正装模组封装结构实施例24结构示意图。图72为图71的俯视图。由图70~72可以看出,实施例24与实施例23的不同之处在于:所述引脚2有多圈。Referring to Figures 70-72, Figures 70(A)-70(R) are schematic diagrams of each process in Embodiment 24 of the front-mount module packaging method for double-sided graphics chips of the present invention. Fig. 71 is a structural schematic diagram of Embodiment 24 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 72 is a top view of FIG. 71 . It can be seen from FIGS. 70-72 that the difference between Embodiment 24 and Embodiment 23 lies in that the pin 2 has multiple turns.

实施例25:下沉基岛露出型及多凸点基岛露出型单圈引脚Embodiment 25: Sunken base island exposed type and multi-bump base island exposed single-turn pin

参见图73~75,图73(A)~图73(R)为本发明双面图形芯片正装模组封装方法实施例25各工序示意图。图74为本发明双面图形芯片正装模组封装结构实施例25结构示意图。图75为图74的俯视图。由图73~75可以看出,实施例25与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第二基岛1.2,另一组为第四基岛1.4,所述第二基岛1.2正面中央区域下沉,第四基岛1.4正面设置成多凸点状结构,在所述第四基岛1.4和引脚2的正面设置第一金属层4,在所述第二基岛1.2、第四基岛1.4和引脚2的背面设置第二金属层5,在所述第二基岛1.2正面中央下沉区域和第四基岛1.4正面通过导电或不导电粘结物质6设置芯片7,在所述引脚2外围的区域、引脚2与第二基岛1.2之间的区域、第二基岛1.2与第四基岛1.4之间的区域、第四基岛1.4与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料的塑封料(环氧树脂)3将引脚下部外围、引脚2与第二基岛1.2下部、第二基岛1.2与第四基岛1.4下部、第四基岛1.4与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 73 to 75, Figures 73(A) to 73(R) are schematic diagrams of each process in Embodiment 25 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 74 is a structural schematic diagram of Embodiment 25 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 75 is a top view of FIG. 74 . It can be seen from Figures 73 to 75 that the difference between Embodiment 25 and Embodiment 1 is that: the base island 1 has two groups or multiple groups of base islands, one group is the second base island 1.2, and the other group is the second base island 1.2. For the fourth base island 1.4, the central area of the front of the second base island 1.2 sinks, the front of the fourth base island 1.4 is arranged in a multi-convex structure, and the fourth base island 1.4 and the front of the pin 2 are provided with a A metal layer 4, a second metal layer 5 is provided on the back of the second base island 1.2, the fourth base island 1.4 and the pin 2, and the central sinking area and the fourth base island on the front of the second base island 1.2 1.4 The front side is provided with a chip 7 through a conductive or non-conductive adhesive substance 6, in the peripheral area of the pin 2, the area between the pin 2 and the second base island 1.2, the second base island 1.2 and the fourth base island 1.4 The area between, the area between the fourth base island 1.4 and the pin 2, and the area between the pin 2 and the pin 2 are embedded with a filler-free molding compound 3, and the filler-free molding compound (epoxy resin) 3 Connect the lower periphery of the pin, pin 2 and the lower part of the second base island 1.2, the second base island 1.2 and the lower part of the fourth base island 1.4, the fourth base island 1.4 and the lower part of the pin 2, and the lower part of the pin 2 and the pin 2 Connected as one, the pin 2 is provided with a circle.

实施例26:下沉基岛露出型及多凸点基岛露出型多圈引脚Embodiment 26: sunken base island exposed type and multi-bump base island exposed multi-turn pin

参见图76~78,图76(A)~图76(R)为本发明双面图形芯片正装模组封装方法实施例26各工序示意图。图77为本发明双面图形芯片正装模组封装结构实施例26结构示意图。图78为图77的俯视图。由图76~78可以看出,实施例26与实施例25的不同之处在于:所述引脚2有多圈。Referring to Figures 76-78, Figures 76(A)-76(R) are schematic diagrams of each process in Embodiment 26 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 77 is a structural schematic diagram of Embodiment 26 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 78 is a top view of FIG. 77 . It can be seen from FIGS. 76 to 78 that the difference between Embodiment 26 and Embodiment 25 lies in that the pin 2 has multiple turns.

实施例27:埋入型基岛及多凸点基岛露出型单圈引脚Embodiment 27: Embedded base island and multi-bump base island exposed single-turn pin

参见图79~81,图79(A)~图79(R)为本发明双面图形芯片正装模组封装方法实施例27各工序示意图。图80为本发明双面图形芯片正装模组封装结构实施例27结构示意图。图81为图80的俯视图。由图79~81可以看出,实施例27与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第三基岛1.3,另一组为第四基岛1.4,所述第四基岛1.4正面设置成多凸点状结构,在所述第三基岛1.3、第四基岛1.4和引脚2的正面设置第一金属层4,在所述第四基岛1.4和引脚2的背面设置第二金属层5,在所述引脚2外围的区域、引脚2与第四基岛1.4之间的区域、第三基岛1.3背面、第二基岛1.2与第四基岛1.4之间的区域、第三基岛1.3与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第四基岛1.4下部、第三基岛1.3背面、第三基岛1.3背面与第四基岛1.4下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 79-81, Figures 79(A)-79(R) are schematic diagrams of each process in Embodiment 27 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 80 is a structural schematic diagram of Embodiment 27 of the package structure of a double-sided graphic chip front-mount module of the present invention. FIG. 81 is a top view of FIG. 80 . It can be seen from Figures 79 to 81 that the difference between Embodiment 27 and Embodiment 1 is that: the base island 1 has two groups or multiple groups of base islands, one group is the third base island 1.3, and the other group is the third base island 1.3. It is the fourth base island 1.4, the front of the fourth base island 1.4 is arranged in a multi-bump structure, and the first metal layer 4 is arranged on the front of the third base island 1.3, the fourth base island 1.4 and the pin 2, The second metal layer 5 is arranged on the back of the fourth base island 1.4 and the pin 2, in the peripheral area of the pin 2, the area between the pin 2 and the fourth base island 1.4, the third base island 1.3 The backside, the area between the second base island 1.2 and the fourth base island 1.4, the area between the third base island 1.3 and the pin 2, and the area between the pins are embedded with no filler molding compound 3, so The filler-free molding compound 3 connects the lower periphery of the pin, the lower part of the pin 2 and the fourth base island 1.4, the back of the third base island 1.3, the back of the third base island 1.3 and the lower part of the fourth base island 1.4, and the back of the third base island 1.3 The lower part of the pin 2 and the lower part of the pin 2 are integrally connected, and the pin 2 is provided with a circle.

实施例28:埋入型基岛及多凸点基岛露出型多圈引脚Embodiment 28: Embedded base island and multi-bump base island exposed multi-turn pin

参见图82~84,图82(A)~图82(R)为本发明双面图形芯片正装模组封装方法实施例28各工序示意图。图83为本发明双面图形芯片正装模组封装结构实施例28结构示意图。图84为图83的俯视图。由图82~84可以看出,实施例28与实施例27的不同之处在于:所述引脚2有多圈。Referring to Figures 82 to 84, Figures 82(A) to 82(R) are schematic diagrams of each process in Embodiment 28 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 83 is a structural schematic diagram of Embodiment 28 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 84 is a top view of FIG. 83 . It can be seen from FIGS. 82 to 84 that the difference between Embodiment 28 and Embodiment 27 lies in that the pin 2 has multiple turns.

Claims (15)

1. two-sided graphic chips formal dress module package structure; Comprise Ji Dao (1), pin (2), packless plastic packaging material (3), conduction or non-conductive bonding material (6), chip (7), metal wire (8) and filler plastic packaging material (9) is arranged; Said pin (2) front extends to Ji Dao (1) next door; Front at said Ji Dao (1) and pin (2) is provided with the first metal layer (4); The back side at said Ji Dao (1) and pin (2) is provided with second metal level (5); Upward be provided with chip (7) at said Ji Dao (1) front the first metal layer (4) through conduction or non-conductive bonding material (6); Chip (7) positive with pin (2) front the first metal layer (4) between be connected with metal wire (8); Outside the top of said Ji Dao (1) and pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9), zone between peripheral zone, pin (2) and the Ji Dao (1) of said Ji Dao (1) and pin (2) and the zone between pin (2) and the pin (2) are equipped with packless plastic packaging material (3), and said packless plastic packaging material (3) links into an integrated entity Ji Dao (1) and periphery, pin bottom, pin (2) bottom and Ji Dao (1) bottom and pin (2) bottom and pin (2) bottom; And make said Ji Dao and pin back side size less than Ji Dao and the positive size of pin; Form up big and down small Ji Dao and pin configuration, it is characterized in that: be provided with pillar (10) at said pin (2) back side, pillar (10) root is imbedded in the said packless plastic packaging material (3).
2. the method for packing of a two-sided according to claim 1 graphic chips formal dress module package structure is characterized in that said method comprises following processing step:
Step 1, get metal substrate
Get the suitable metal substrate of a slice thickness,
Step 2, metal substrate front and back side lining photoresistance glued membrane
Utilization by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging,
The positive photoresistance glued membrane of step 3, metal substrate needs the exposure of plated metal layer region/develop and windows
The metal substrate front that utilizes exposure imaging equipment that step 2 is accomplished photoresistance glued membrane lining operation is carried out exposure imaging and is removed part photoresistance glued membrane, carries out the zone of electroplated metal layer to expose the positive follow-up needs of metal substrate,
The zone of having windowed in step 4, metal substrate front is carried out metal level and is electroplated lining
The first metal layer plating lining is carried out in zone to having windowed in metal substrate front in the step 3, and this first metal layer places the front of said Ji Dao and pin,
Photoresistance glued membrane striping is carried out at step 5, metal substrate front and the back side
The positive remaining photoresistance glued membrane of metal substrate and the photoresistance glued membrane at the metal substrate back side are all removed,
Step 6, metal substrate front and back side lining photoresistance glued membrane
Utilization by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up etch process operation,
The photoresistance glued membrane of step 7, metal substrate needs the exposure of two-sided etching area/develop and windows
Exposure imaging removal part photoresistance glued membrane is carried out at the metal substrate front and the back side that utilize exposure imaging equipment that step 6 is accomplished photoresistance glued membrane lining operation, prepares against the two-sided etching operation of metal substrate that follow-up needs carry out to expose the localized metallic substrate,
Step 8, metal substrate carry out two-sided etching operation
After the exposure/development and windowing task of completing steps seven; The etching operation of promptly carrying out each figure at the front and the back side of metal substrate; Etch the front and back of Ji Dao and pin; Simultaneously the pin front is extended to next door, basic island as much as possible, and make the positive size of the back side size of said Ji Dao and pin, form up big and down small Ji Dao and pin configuration less than Ji Dao and pin; And form pillar at the pin back side, and at the company's of leaving muscle between Ji Dao and the pin and between pin and the pin,
Photoresistance glued membrane striping is carried out at step 9, metal substrate front and the back side
The photoresistance glued membrane that the metal substrate front and back is remaining all removes, and processes lead frame,
Step 10, load
On front, the basic island the first metal layer of the lead frame that step 9 is processed, carry out the implantation of chip through conduction or non-conductive bonding material,
Step 11, break metal wire
The semi-finished product of accomplishing chip implantation operation are carried out playing the metal wire operation between chip front side and the pin front the first metal layer,
Step 12, be encapsulated with the filler plastic packaging material
The semi-finished product front that routing is accomplished is encapsulated with the operation of filler plastic packaging material, and carries out the curing operation after plastic packaging material is sealed, and makes top and the chip of Ji Dao and pin and metal wire all had the filler plastic packaging material to seal outward,
Step 13, lining photoresistance glued membrane
Utilization by coating equipment will accomplish the half-finished front that is encapsulated with the operation of filler plastic packaging material and the back side be covered respectively the photoresistance glued membrane that can carry out exposure imaging with, protecting follow-up etch process operation,
Step 14, accomplish the exposure that the half-finished back side that is encapsulated with the operation of filler plastic packaging material needs etching area/develop and windowing
Exposure imaging removal part photoresistance glued membrane is carried out at the semi-finished product back side that is encapsulated with the operation of filler plastic packaging material of accomplishing that utilizes exposure imaging equipment that step 13 is accomplished photoresistance glued membrane lining operation; To expose company's muscle that leaves after the two-sided etching operation of step 8 metal substrate and the pillar that forms at the pin back side; Carry out the pillar root and connect muscle etching operation in order to follow-up needs
Step 15, the operation of etching for the second time
After the exposure/development and windowing task of completing steps 14; Promptly carry out the etching operation of each figure at the semi-finished product back side that completion is encapsulated with the operation of filler plastic packaging material; The company's muscle that leaves after the two-sided etching operation of step 8 metal substrate is all etched away; Root at pillar described in this process also can etch away relative thickness simultaneously, makes the pillar root not expose the encapsulating structure back side after sealing
Photoresistance glued membrane striping is carried out at step 10 six, semi-finished product front and the back side
Photoresistance glued membrane that the semi-finished product back side of completing steps 15 etching operations is remaining and the positive photoresistance glued membrane of semi-finished product all remove,
Step 10 seven, seal packless plastic packaging material
Packless plastic packaging material operation is sealed at the semi-finished product back side of completing steps 16 said striping operations; And carry out the curing operation after plastic packaging material is sealed; Make the peripheral zone of Ji Dao and pin; Packless plastic packaging material is all set in zone between pin and the basic island and the zone between pin and the pin; This packless plastic packaging material is peripheral with Ji Dao and pin bottom; Pin bottom and Ji Dao bottom and pin bottom and pin bottom link into an integrated entity; And said pillar root is imbedded in this packless plastic packaging material
The back side of step 10 eight, Ji Dao and pin is carried out metal level and is electroplated lining
The back side that completing steps 17 is sealed said Ji Dao and the pin of the operation of no filler plastic packaging material is carried out second metal level and is electroplated the lining operation,
Step 10 nine, cutting finished product
The semi-finished product of ten eight the second metal levels of completing steps being electroplated lining carry out cutting operation, make originally more than of chips that connect together with array formula aggregate mode independent, make two-sided graphic chips formal dress module package structure finished product.
3. the method for packing of a kind of two-sided graphic chips formal dress module package structure according to claim 2 is characterized in that Ji Dao (1) back side exposes said packless plastic packaging material (3).
4. the method for packing of a kind of two-sided graphic chips formal dress module package structure according to claim 2 is characterized in that Ji Dao (1) front middle section sinks.
5. the method for packing of a kind of two-sided graphic chips formal dress module package structure according to claim 2 is characterized in that Ji Dao (1) back side imbeds in the said packless plastic packaging material (3).
6. the method for packing of a kind of two-sided graphic chips formal dress module package structure according to claim 2 is characterized in that said Ji Dao (1) front is arranged to multi-convex point shape structure.
7. according to the method for packing of one of them described a kind of two-sided graphic chips formal dress module package structure of claim 2~6, it is single to it is characterized in that said Ji Dao (1) has, and pin (2) has many circles.
8. according to the method for packing of one of them described a kind of two-sided graphic chips formal dress module package structure of claim 2~6, it is a plurality of to it is characterized in that said Ji Dao (1) has, and pin (2) has individual pen.
9. according to the method for packing of one of them described a kind of two-sided graphic chips formal dress module package structure of claim 2~6, it is a plurality of to it is characterized in that said Ji Dao (1) has, and pin (2) has many circles.
10. the method for packing of a kind of two-sided graphic chips formal dress module package structure according to claim 2; It is characterized in that said Ji Dao (1) has two groups; One group is first Ji Dao (1.1); Another group is second Ji Dao (1.2); Said second Ji Dao (1.2) front middle section sinks; Front at said first Ji Dao (1.1) and pin (2) is provided with the first metal layer (4); The back side at said first Ji Dao (1.1), second Ji Dao (1.2) and pin (2) is provided with second metal level (5); Be provided with chip (7) in positive central sunken regions of second Ji Dao (1.2) and first Ji Dao (1.1) front through conduction or non-conductive bonding material (6); Chip (7) positive with pin (2) front the first metal layer (4) between and all use metal wire (8) to be connected between chip (7) and the chip (7); Nos filler plastic packaging material (3) is set in zone between zone, second Ji Dao (1.2) and pin (2) between zone, first Ji Dao (1.1) and second Ji Dao (1.2) between peripheral zone, pin (2) and first Ji Dao (1.1) of said pin (2) and the zone between pin (2) and the pin (2), and said no filler plastic packaging material (3) is peripheral with the pin bottom, pin (2) and first Ji Dao (1.1) bottom, first Ji Dao (1.1) and second Ji Dao (1.2) bottom, second Ji Dao (1.2) and pin (2) bottom and pin (2) and pin (2) bottom link into an integrated entity, and said pin (2) is provided with individual pen or encloses more.
11. the method for packing of a kind of two-sided graphic chips formal dress module package structure according to claim 2; It is characterized in that said Ji Dao (1) has two groups; One group is first Ji Dao (1.1); Another group is the 3rd Ji Dao (1.3); Front at said first Ji Dao (1.1) the 3rd Ji Dao (1.3) and pin (2) is provided with the first metal layer (4); The back side at said first Ji Dao (1.1) and pin (2) is provided with second metal level (5); Be provided with chip (7) in Ji Dao (1) front through conduction or non-conductive bonding material (6); Chip (7) positive with pin (2) front the first metal layer (4) between and all use metal wire (8) to be connected between chip (7) and the chip (7); Outside the top of said Ji Dao (1) and pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9); No filler plastic packaging material (3) is set in zone and the zone between pin and the pin between zone, the 3rd Ji Dao (1.3) and pin (2) between zone, the 3rd Ji Dao (1.3) back side, second Ji Dao (1.2) and first Ji Dao (1.1) between zone, pin (2) and first Ji Dao (1.1) of said pin (2) periphery, and said no filler plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with first Ji Dao (1.1) bottom, the 3rd Ji Dao (1.3) back side, the 3rd Ji Dao (1.3) back side and first Ji Dao (1.1) bottom, the 3rd Ji Dao (1.3) back side and pin (2) bottom and pin (2), and said pin (2) is provided with individual pen or enclose more.
12. the method for packing of a kind of two-sided graphic chips formal dress module package structure according to claim 2; It is characterized in that said Ji Dao (1) has two groups; One group is first Ji Dao (1.1); Another group is the 4th Ji Dao (1.4); Said the 4th Ji Dao (1.4) is arranged to multi-convex point shape structure in the front; No filler plastic packaging material (3) is set in zone between zone, the 4th Ji Dao (1.4) and pin (2) between zone, first Ji Dao (1.1) and the 4th Ji Dao (1.4) between zone, pin (2) and first Ji Dao (1.1) of said pin (2) periphery and the zone between pin (2) and the pin (2); Said packless plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with pin (2) bottom and pin (2) with the 4th Ji Dao (1.4) bottom, the 4th Ji Dao (1.4) with first Ji Dao (1.1) bottom, first Ji Dao (1.1), and said pin (2) is provided with individual pen or many circles.
13. the method for packing of a kind of two-sided graphic chips formal dress module package structure according to claim 2; It is characterized in that said Ji Dao (1) has two groups or organize Ji Dao more; One group is second Ji Dao (1.2); Another group is the 3rd Ji Dao (1.3); Said second Ji Dao (1.2) front middle section sinks; Be provided with chip (7) in positive central sunken regions of second Ji Dao (1.2) and the 3rd Ji Dao (1.3) front through conduction or non-conductive bonding material (6); No filler plastic packaging material (3) is set in zone and the zone between pin and the pin between zone, the 3rd Ji Dao (1.3) back side and pin (2) between zone, the 3rd Ji Dao (1.3) back side, the second Ji Dao back side (1.2) and second Ji Dao (1.2) between zone, pin (2) and second Ji Dao (1.2) of said pin (2) periphery; Said no filler plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with second Ji Dao (1.2) bottom, the 3rd Ji Dao (1.3) back side and pin (2) bottom and pin (2) with second Ji Dao (1.2) bottom, the 3rd Ji Dao (1.3), the 3rd Ji Dao (1.3), and said pin (2) is provided with individual pen.
14. the method for packing of a kind of two-sided graphic chips formal dress module package structure according to claim 2; It is characterized in that said Ji Dao (1) has two groups; One group is second Ji Dao (1.2); Another group is the 4th Ji Dao (1.4); Said second Ji Dao (1.2) front middle section sinks; The 4th Ji Dao (1.4) is arranged to multi-convex point shape structure in the front; Front at said the 4th Ji Dao (1.4) and pin (2) is provided with the first metal layer (4); The back side at said second Ji Dao (1.2), the 4th Ji Dao (1.4) and pin (2) is provided with second metal level (5), is provided with chip (7) in positive central sunken regions of said second Ji Dao (1.2) and the 4th Ji Dao (1.4) front through conduction or non-conductive bonding material (6), and no filler plastic packaging material (3) is set in zone between zone, the 4th Ji Dao (1.4) and pin (2) between zone, second Ji Dao (1.2) and the 4th Ji Dao (1.4) between zone, pin (2) and second Ji Dao (1.2) of said pin (2) periphery and the zone between pin (2) and the pin (2); Said packless plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with pin (2) bottom and pin (2) with the 4th Ji Dao (1.4) bottom, the 4th Ji Dao (1.4) with second Ji Dao (1.2) bottom, second Ji Dao (1.2), and said pin (2) is provided with individual pen or many circles.
15. the method for packing of a kind of two-sided graphic chips formal dress module package structure according to claim 2; It is characterized in that said Ji Dao (1) has two groups; One group is the 3rd Ji Dao (1.3); Another group is the 4th Ji Dao (1.4); Said the 4th Ji Dao (1.4) is arranged to multi-convex point shape structure in the front; Front at said the 3rd Ji Dao (1.3), the 4th Ji Dao (1.4) and pin (2) is provided with the first metal layer (4); The back side at said the 4th Ji Dao (1.4) and pin (2) is provided with second metal level (5); No filler plastic packaging material (3) is set in zone and the zone between pin and the pin between zone, the 3rd Ji Dao (1.3) and pin (2) between zone, the 3rd Ji Dao (1.3) back side, second Ji Dao (1.2) and the 4th Ji Dao (1.4) between zone, pin (2) and the 4th Ji Dao (1.4) of said pin (2) periphery; Said no filler plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with the 4th Ji Dao (1.4) bottom, the 3rd Ji Dao (1.3) back side, the 3rd Ji Dao (1.3) back side and the 4th Ji Dao (1.4) bottom, the 3rd Ji Dao (1.3) back side and pin (2) bottom and pin (2), and said pin (2) is provided with individual pen or many circles.
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