CN101958305B - Double-sided graphics chip front-mount module packaging structure and packaging method - Google Patents
Double-sided graphics chip front-mount module packaging structure and packaging method Download PDFInfo
- Publication number
- CN101958305B CN101958305B CN2010102730299A CN201010273029A CN101958305B CN 101958305 B CN101958305 B CN 101958305B CN 2010102730299 A CN2010102730299 A CN 2010102730299A CN 201010273029 A CN201010273029 A CN 201010273029A CN 101958305 B CN101958305 B CN 101958305B
- Authority
- CN
- China
- Prior art keywords
- pin
- dao
- back side
- zone
- packaging material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 149
- 238000004806 packaging method and process Methods 0.000 title description 93
- 229910052751 metal Inorganic materials 0.000 claims abstract description 187
- 239000002184 metal Substances 0.000 claims abstract description 187
- 239000000463 material Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims description 82
- 239000000945 filler Substances 0.000 claims description 60
- 239000004033 plastic Substances 0.000 claims description 57
- 238000005530 etching Methods 0.000 claims description 41
- 239000011265 semifinished product Substances 0.000 claims description 31
- 239000011248 coating agent Substances 0.000 claims description 15
- 238000000576 coating method Methods 0.000 claims description 15
- 230000002093 peripheral effect Effects 0.000 claims description 15
- 239000000047 product Substances 0.000 claims description 9
- 238000007789 sealing Methods 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 3
- -1 Step 8 Substances 0.000 claims description 2
- 239000005022 packaging material Substances 0.000 claims 36
- 239000012528 membrane Substances 0.000 claims 22
- 238000012856 packing Methods 0.000 claims 14
- 238000003384 imaging method Methods 0.000 claims 9
- 210000003205 muscle Anatomy 0.000 claims 4
- 238000011112 process operation Methods 0.000 claims 2
- 238000007747 plating Methods 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 abstract description 55
- 238000000465 moulding Methods 0.000 abstract description 54
- 239000003822 epoxy resin Substances 0.000 abstract description 42
- 229920000647 polyepoxide Polymers 0.000 abstract description 42
- 239000000126 substance Substances 0.000 abstract description 11
- 230000000704 physical effect Effects 0.000 abstract description 3
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 115
- 229920002120 photoresistant polymer Polymers 0.000 description 59
- 239000010408 film Substances 0.000 description 56
- 229940126214 compound 3 Drugs 0.000 description 10
- 238000009713 electroplating Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 6
- 239000000565 sealant Substances 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000007888 film coating Substances 0.000 description 4
- 238000009501 film coating Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000002699 waste material Substances 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 206010034701 Peroneal nerve palsy Diseases 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Packaging Frangible Articles (AREA)
Abstract
Description
(一)技术领域(1) Technical field
本发明涉及一种双面图形芯片正装模组封装结构及其封装方法。属于半导体封装技术领域。The invention relates to a package structure and a package method of a front-loading module for a double-sided graphics chip. It belongs to the technical field of semiconductor packaging.
(二)背景技术(2) Background technology
传统的芯片封装结构的制作方式是:采用金属基板的正面进行化学蚀刻及表面电镀层后,即完成引线框的制作(如图85所示)。而引线框的背面则在封装过程中再进行蚀刻。该法存在以下不足:The traditional manufacturing method of the chip packaging structure is: after chemical etching and surface electroplating are performed on the front side of the metal substrate, the production of the lead frame is completed (as shown in FIG. 85 ). The backside of the leadframe is etched during the packaging process. This law has the following shortcomings:
因为塑封前只在金属基板正面进行了半蚀刻工作,而在塑封过程中塑封料只有包裹住引脚半只脚的高度,所以塑封体与引脚的束缚能力就变小了,如果塑封体贴片到PCB板上不是很好时,再进行返工重贴,就容易产生掉脚的问题(如图86所示)。尤其塑封料的种类是采用有填料时候,因为材料在生产过程的环境与后续表面贴装的应力变化关系,会造成金属与塑封料产生垂直型的裂缝,其特性是填料比例越高则越硬越脆越容易产生裂缝。Because only half-etching work is done on the front of the metal substrate before plastic sealing, and the plastic sealing material is only half a foot high to cover the pins during the plastic sealing process, so the binding ability between the plastic package and the pins becomes smaller. If the plastic package is considerate When the chip is not well attached to the PCB board, rework and re-attachment will easily cause the problem of foot drop (as shown in Figure 86). Especially when the type of molding compound is filled, because the relationship between the environment of the material in the production process and the stress change of the subsequent surface mount will cause vertical cracks between the metal and the molding compound, the characteristic is that the higher the filler ratio, the harder it is The more brittle the easier it is to crack.
另外,由于芯片与引脚之间的距离较远,金属线的长度较长,如图87~88所示,金属线成本较高(尤其是昂贵的纯金质的金属线);同样由于金属线的长度较长,使得芯片的信号输出速度较慢(尤其是存储类的产品以及需要大量数据的计算,更为突出);也同样由于金属线的长度较长,所以在金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也较高;再由于芯片与引脚之间的距离较远,使得封装的体积与面积较大,材料成本较高,废弃物较多。In addition, due to the long distance between the chip and the pins, the length of the metal wire is relatively long, as shown in Figures 87-88, the cost of the metal wire is relatively high (especially the expensive pure gold metal wire); The length of the wire is longer, which makes the signal output speed of the chip slower (especially for storage products and calculations that require a large amount of data); The interference of parasitic resistance/capacitance and parasitic poles on the signal is also high; and because the distance between the chip and the pins is long, the volume and area of the package are large, the cost of materials is high, and there is more waste.
为此,本申请人在先申请了一件名称为《有基岛引线框结构及其生产方法》的发明专利,其申请号为:201010165896.0。其主要技术特征是:采用金属基板的背面先进行半蚀刻,在金属基板的背面形成凹陷的半蚀刻区域,同时相对形成基岛和引脚的背面,再在所述半蚀刻区域,填涂上无填料的软性填缝剂,并同时进行烘烤,使无填料的软性填缝剂固化成无填料的塑封料(环氧树脂),以包裹住引脚的背面。然后再在金属基板的正面进行半蚀刻,同时相对形成基岛和引脚的正面。其有益效果主要有:For this reason, the applicant previously applied for an invention patent titled "Based Island Lead Frame Structure and Its Production Method", and its application number is: 201010165896.0. Its main technical features are: use the back of the metal substrate to half-etch first, form a recessed half-etched area on the back of the metal substrate, and at the same time form the base island and the back of the pin relatively, and then fill and coat the half-etched area. Filler-free soft sealant, and bake at the same time, so that the filler-free soft sealant cures into a filler-free molding compound (epoxy resin) to wrap the backside of the pin. Then half etch is performed on the front side of the metal substrate, and at the same time, the base island and the front side of the pin are relatively formed. Its beneficial effects mainly include:
1)由于在所述金属基板的背面引脚与引脚间的区域嵌置有无填料的软性填缝剂,该无填料的软性填缝剂与在塑封过程中的金属基板正面的常规有填料塑封料(环氧树脂)一起包裹住整个引脚的高度,所以塑封体与引脚的束缚能力就变大了,不会再有产生掉脚的问题,如图89。1) Since the area between the pins and the pins on the back of the metal substrate is embedded with a soft sealant without filler, the soft sealant without filler is different from the conventional sealant on the front side of the metal substrate in the plastic sealing process. There is a filler plastic compound (epoxy resin) that covers the entire height of the pins together, so the binding capacity between the plastic package and the pins becomes larger, and there will be no problem of falling feet, as shown in Figure 89.
2)由于采用了引线框正面与背面分开蚀刻作业的方法,所以在蚀刻作业中可形成背面引脚的尺寸稍小而正面引脚尺寸稍大的结构,而同个引脚的上下大小不同尺寸在被无填料的塑封料(环氧树脂)所包裹的更紧更不容易产生滑动而掉脚。2) Due to the method of separate etching operations on the front and back of the lead frame, a structure in which the size of the back pins is slightly smaller and the size of the front pins is slightly larger can be formed during the etching operation, while the upper and lower sizes of the same pin are different It is tighter and less likely to slip and fall when it is wrapped by a filler-free molding compound (epoxy resin).
3)由于应用了引线框背面与正面分开蚀刻的技术,所以能够将引线框正面的引脚尽可能的延伸到基岛的旁边,促使芯片与引脚距离大幅的缩短,如图89~90,如此金属线所使用的成本也可以大幅的降低(尤其是昂贵的纯金质的金属线)。3) Due to the application of the technology of separately etching the back and front of the lead frame, the pins on the front of the lead frame can be extended to the side of the base island as much as possible, which greatly shortens the distance between the chip and the pins, as shown in Figures 89-90. The cost of such metal wires can also be greatly reduced (especially expensive pure gold metal wires).
4)也因为金属线的缩短使得芯片的信号输出速度也大幅的增速(尤其存储类的产品以及需要大量数据的计算,更为突出),由于金属线的长度变短了,所以金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也大幅度的降低。4) Also because of the shortening of the metal wire, the signal output speed of the chip is also greatly increased (especially for storage products and calculations that require a large amount of data), and because the length of the metal wire is shortened, the metal wire The interference of the existing parasitic resistance/capacitance and parasitic poles to the signal is also greatly reduced.
5)因运用了引脚的延伸技术,所以可以容易的制作出高脚数与高密度的脚之间的距离,使得封装的体积与面积可以大幅度的缩小。5) Due to the use of pin extension technology, the distance between high pin count and high density pins can be easily produced, so that the volume and area of the package can be greatly reduced.
6)因为将封装后的体积大幅度的缩小,更直接的体现出材料成本大幅度的下降与因为材料用量的减少也大幅度的减少废弃物环保的困扰。6) Because the volume after packaging is greatly reduced, it more directly reflects the substantial reduction of material costs and the reduction of material consumption also greatly reduces the environmental problems of waste and environmental protection.
但是,还是存在有以下的不足:由于封装前先进行引线框背面无填料塑封料的包裹引脚作业,再进行引线框正面的高温装片和打线作业时,因引线框和无填料塑封料两种材料的物理性能不同,两种材料的膨胀系数也不同,在高温下受热形变不同,导致后续装片时引线框产生扭曲。因此该种封装结构在装片时不能够耐超高温(200℃以上)。而以往是通过把封装体体积做得很大来达到耐高温的要求,但现在要求封装体的体积越来越小而功率是越来越大的情况下就耐不了超高温了。However, there are still following deficiencies: before encapsulation, the wrapping pin operation of the backside of the lead frame without filler molding compound is carried out, and when the high-temperature chip loading and wiring operations on the front of the lead frame are carried out, the lead frame and the filler-free plastic sealant The physical properties of the two materials are different, the coefficients of expansion of the two materials are also different, and the thermal deformation at high temperature is different, which leads to distortion of the lead frame during subsequent chip mounting. Therefore, this kind of packaging structure cannot withstand ultra-high temperature (above 200° C.) during chip loading. In the past, the requirement of high temperature resistance was achieved by making the volume of the package body large, but now the volume of the package body is required to be smaller and the power is larger and larger, and it cannot withstand ultra-high temperature.
(三)发明内容(3) Contents of the invention
本发明的目的在于克服上述不足,提供一种装片时可承受超高温且不会因不同物质的不同物理性质而产生引线框扭曲,也不会再有产生掉脚的问题和能使金属线的长度缩短的双面图形芯片正装模组封装结构及其封装方法。The purpose of the present invention is to overcome the above disadvantages, to provide a lead frame that can withstand ultra-high temperature during chip loading and will not cause distortion of the lead frame due to different physical properties of different substances, and will not cause the problem of falling feet and can make the metal wire The packaging structure and packaging method of the double-sided graphics chip front-loading module with shortened length.
本发明的目的是这样实现的:一种双面图形芯片正装模组封装结构,包括基岛、引脚、无填料的塑封料(环氧树脂)、导电或不导电粘结物质、芯片、金属线和有填料塑封料(环氧树脂),所述引脚正面延伸到基岛旁边,在所述基岛和引脚的正面设置有第一金属层,在所述基岛和引脚的背面设置有第二金属层,在所述基岛正面第一金属层上通过导电或不导电粘结物质设置有芯片,芯片正面与引脚正面第一金属层之间用金属线连接,在所述基岛和引脚的上部以及芯片和金属线外包封有填料塑封料(环氧树脂),在所述基岛和引脚外围的区域、引脚与基岛之间的区域以及引脚与引脚之间的区域嵌置有无填料的塑封料(环氧树脂),所述无填料的塑封料(环氧树脂)将基岛和引脚下部外围、引脚下部与基岛下部以及引脚下部与引脚下部连接成一体,且使所述基岛和引脚背面尺寸小于基岛和引脚正面尺寸,形成上大下小的基岛和引脚结构,其特征在于:在所述引脚背面设置有柱子,柱子根部埋入所述无填料的塑封料(环氧树脂)内。The object of the present invention is achieved like this: a kind of double-sided graphics chip front-loading module package structure, comprises base island, pin, no filler molding compound (epoxy resin), conductive or non-conductive bonding material, chip, metal wire and filled molding compound (epoxy resin), the front side of the pin extends to the side of the base island, the first metal layer is arranged on the front side of the base island and the pin, and the back side of the base island and the pin A second metal layer is provided, and a chip is provided on the first metal layer on the front side of the base island through a conductive or non-conductive adhesive substance, and the front side of the chip is connected with the first metal layer on the front side of the pin by a metal wire. The upper part of the base island and the pin, as well as the chip and the metal wire are encapsulated with filler molding compound (epoxy resin), and the area around the base island and the pin, the area between the pin and the base island, and the pin and the lead The area between the pins is embedded with an unfilled molding compound (epoxy) that connects the base island to the lower periphery of the pin, the lower portion of the pin to the lower portion of the base island, and the pin The lower part is integrated with the lower part of the pin, and the size of the base island and the back side of the pin is smaller than the size of the base island and the front side of the pin, forming a base island and pin structure with a large upper part and a smaller bottom part, which is characterized in that: in the lead A pillar is arranged on the back of the foot, and the root of the pillar is embedded in the plastic sealing compound (epoxy resin) without filler.
本发明双面图形芯片正装模组封装结构的封装方法,所述方法包括以下工艺步骤:The packaging method of the double-sided graphics chip front-mounted module packaging structure of the present invention, the method comprises the following process steps:
步骤一、取金属基板
取一片厚度合适的金属基板,Take a piece of metal substrate with appropriate thickness,
步骤二、金属基板正面及背面被覆光阻胶膜
利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜,Use coating equipment to cover the front and back of the metal substrate with a photoresist film that can be exposed and developed,
步骤三、金属基板正面的光阻胶膜进行需要电镀金属层区域的曝光/显影以及开窗Step 3: Expose/develop the photoresist film on the front of the metal substrate and open the window where the metal layer needs to be plated
利用曝光显影设备将步骤二完成光阻胶膜被覆作业的金属基板正面进行曝光显影去除部分光阻胶膜,以露出金属基板正面后续需要进行电镀金属层的区域,Use exposure and development equipment to expose and develop the front of the metal substrate that has completed the photoresist film coating operation in
步骤四、金属基板正面已开窗的区域进行金属层电镀被覆
对步骤三中金属基板正面已开窗的区域进行第一金属层电镀被覆,该第一金属层置于所述基岛与引脚的正面,The first metal layer is electroplated on the area where the window has been opened on the front of the metal substrate in
步骤五、金属基板正面及背面进行光阻胶膜去膜
将金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除,Remove the remaining photoresist film on the front of the metal substrate and the photoresist film on the back of the metal substrate.
步骤六、金属基板正面及背面被覆光阻胶膜
利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜,以保护后续的蚀刻工艺作业,Use the coating equipment to cover the front and back of the metal substrate with a photoresist film that can be exposed and developed to protect the subsequent etching process.
步骤七、金属基板的光阻胶膜进行需要双面蚀刻区域的曝光/显影以及开窗
利用曝光显影设备将步骤六完成光阻胶膜被覆作业的金属基板正面及背面进行曝光显影去除部分光阻胶膜,以露出局部金属基板以备后续需要进行的金属基板双面蚀刻作业,Use the exposure and development equipment to expose and develop the front and back of the metal substrate that has completed the photoresist film coating operation in
步骤八、金属基板进行双面蚀刻作业
完成步骤七的曝光/显影以及开窗作业后,即在金属基板的正面及背面进行各图形的蚀刻作业,蚀刻出基岛和引脚的正面和背面,同时将引脚正面尽可能的延伸到基岛旁边,且使所述基岛和引脚的背面尺寸小于基岛和引脚的正面尺寸,形成上大下小的基岛和引脚结构;以及在引脚背面形成柱子,并在基岛与引脚之间以及引脚与引脚之间留有连筋,After completing the exposure/development and window opening operations in
步骤九、金属基板正面及背面进行光阻胶膜去膜
将金属基板正面和背面余下的光阻胶膜全部揭除,制成引线框,Remove all the remaining photoresist film on the front and back of the metal substrate to make a lead frame,
步骤十、装片Step ten, loading film
在步骤九制成的引线框的基岛正面第一金属层上通过导电或不导电粘结物质进行芯片的植入,On the first metal layer on the front side of the base island of the lead frame made in
步骤十一、打金属线Step 11, hit the metal wire
将已完成芯片植入作业的半成品进行芯片正面与引脚正面第一金属层之间打金属线作业,The semi-finished product that has completed the chip implantation operation is put into the metal line operation between the front side of the chip and the first metal layer on the front side of the pin,
步骤十二、包封有填料塑封料(环氧树脂)
将已打线完成的半成品正面进行包封有填料塑封料(环氧树脂)9作业,并进行塑封料包封后的固化作业,使基岛和引脚的上部以及芯片和金属线外均被有填料塑封料(环氧树脂)包封,Encapsulate the front side of the semi-finished product that has been wired with filler molding compound (epoxy resin) 9, and perform curing operations after the molding compound is encapsulated, so that the base island and the upper part of the pin, as well as the outside of the chip and the metal wire are covered. Encapsulated with filler molding compound (epoxy resin),
步骤十三、被覆光阻胶膜Step 13: Coating photoresist film
利用被覆设备在将已完成包封有填料塑封料(环氧树脂)作业的半成品的正面及背面分别被覆可进行曝光显影的光阻胶膜和,以保护后续的蚀刻工艺作业,Use the coating equipment to cover the front and back of the semi-finished product that has been encapsulated with filler molding compound (epoxy resin) with a photoresist film that can be exposed and developed to protect the subsequent etching process.
步骤十四、已完成包封有填料塑封料(环氧树脂)作业的半成品的背面进行需要蚀刻区域的曝光/显影以及开窗
利用曝光显影设备将步骤十三完成光阻胶膜被覆作业的已完成包封有填料塑封料作业的半成品背面进行曝光显影去除部分光阻胶膜,以露出步骤八金属基板双面蚀刻作业后留有的连筋以及在引脚背面形成的柱子,以备后续需要进行柱子根部和连筋蚀刻作业,Use exposure and development equipment to expose and develop the back of the semi-finished product that has completed the process of covering the photoresist film in
步骤十五、第二次蚀刻作业Step fifteen, the second etching operation
完成步骤十四的曝光/显影以及开窗作业后,即在完成包封有填料塑封料(环氧树脂)作业的半成品背面进行各图形的蚀刻作业,将步骤八金属基板双面蚀刻作业后留有的连筋全部蚀刻掉,在这个过程中所述柱子的根部也会同时的蚀刻掉相对的厚度,使柱子根部不露出包封后的封装结构背面,After completing the exposure/development and window opening operations in
步骤十六、半成品正面及背面进行光阻胶膜去膜
将完成步骤十五蚀刻作业的半成品背面余下的光阻胶膜以及半成品正面的光阻胶膜全部揭除,Remove the remaining photoresist film on the back of the semi-finished product and the photoresist film on the front of the semi-finished product after completing the etching operation in
步骤十七、包封无填料的塑封料(环氧树脂)Step seventeen, encapsulating the plastic compound (epoxy resin) without filler
将已完成步骤十六所述去膜作业的半成品背面进行包封无填料的塑封料(环氧树脂)作业,并进行塑封料包封后的固化作业,使基岛和引脚外围的区域、引脚与基岛之间的区域以及引脚与引脚之间的区域均嵌置无填料的塑封料(环氧树脂),该无填料的塑封料(环氧树脂)将基岛和引脚下部外围、引脚下部与基岛下部以及引脚下部与引脚下部连接成一体,且使所述柱子根部埋入该无填料的塑封料(环氧树脂)内,Carry out the operation of encapsulating the plastic compound (epoxy resin) without filler on the back of the semi-finished product that has completed the film removal operation described in
步骤十八、基岛和引脚的背面进行金属层电镀被覆
对已完成步骤十七包封无填料塑封料作业的所述基岛和引脚的背面进行第二金属层电镀被覆作业,Carrying out the second metal layer electroplating coating operation on the back of the base island and pins that have completed the operation of encapsulating the plastic compound without filler in step seventeen,
步骤十九、切割成品Step nineteen, cut the finished product
将已完成步骤十八第二金属层电镀被覆的半成品进行切割作业,使原本以列阵式集合体方式连在一起的芯片一颗颗独立开来,制得双面图形芯片正装模组封装结构成品。Cutting the semi-finished product that has completed the electroplating and coating of the second metal layer in
本发明的有益效果是:The beneficial effects of the present invention are:
1、引线框耐超高温(200℃以上)1. The lead frame is ultra-high temperature resistant (above 200°C)
由于采用了双面图形蚀刻引线框技术,一次完成引线框的正、背两面双面蚀刻,同时封装时先进行引线框正面的高温装片打线再进行引线框背面的引脚包裹作业,使装片打线时只有引线框一种材料,在使用超高温的制程过程中因没有多种材料膨胀系数不同所带来的冲击,确保了引线框的耐超高温(一般是200℃以下)性能。Due to the use of double-sided graphic etching lead frame technology, the front and back double-sided etching of the lead frame is completed at one time. At the same time, when packaging, the high-temperature chip mounting and wiring on the front of the lead frame is performed first, and then the pin wrapping operation on the back of the lead frame is performed. There is only one material of the lead frame for chip loading and wiring. In the ultra-high temperature process, there is no impact caused by the different expansion coefficients of various materials, which ensures the ultra-high temperature resistance (generally below 200°C) of the lead frame. .
2、能确保引线框装片强度2. It can ensure the strength of the lead frame
因为不先做预包封,引线框装片时承受的压力大,打线时会使引线框产生振动,引线框会出现下陷现象。本发明通过在引线框背面留有柱子的设计,以增加打线时引线框的强度。Because the pre-encapsulation is not done first, the pressure on the lead frame is high when the chip is loaded, and the lead frame will vibrate when the wire is bonded, and the lead frame will sag. The invention adopts the design of leaving pillars on the back of the lead frame to increase the strength of the lead frame when wiring.
3、确保不会再有产生掉脚的问题3. Make sure that there will be no more problems with feet falling
由于采用了双面蚀刻的工艺技术,所以可以轻松的规划设计与制造出上大下小的引脚结构,可以使上下层塑封料紧密的将上大下小的引脚结构一起包裹住,所以塑封体与引脚的束缚能力就变大了,不会再有产生掉脚的问题。Due to the use of double-sided etching technology, it is easy to plan, design and manufacture pin structures with upper and lower pins, and the upper and lower plastic molding compounds can tightly wrap the upper and lower pin structures together, so The binding ability between the plastic package and the pins becomes larger, and there will be no more problems of falling feet.
4、确保金属线的长度缩短4. Make sure the length of the metal wire is shortened
1)由于应用了引线框背面与正面同时且分开蚀刻的技术,所以能够将引线框正面的引脚尽可能的延伸到后续需装芯片的区域旁边,促使芯片与引脚距离大幅的缩短,如图89~图90,如此金属线的长度也缩短了,金属线的成本也可以大幅的降低(尤其是昂贵的纯金质的金属线);1) Due to the application of the technology of simultaneous and separate etching on the back and front of the lead frame, the pins on the front of the lead frame can be extended as far as possible to the side of the area where the chip needs to be installed later, which greatly shortens the distance between the chip and the pin, such as As shown in Fig. 89-90, the length of the metal wire is also shortened, and the cost of the metal wire can be greatly reduced (especially the expensive pure gold metal wire);
2)也因为金属线的长度缩短使得芯片的信号输出速度也大幅的增速(尤其存储类的产品以及需要大量数据的计算,更为突出),由于金属线的长度变短了,所以金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也大幅度的降低。2) Also because the length of the metal wire is shortened, the signal output speed of the chip is also greatly increased (especially for storage products and calculations that require a large amount of data). The interference of the existing parasitic resistance/capacitance and parasitic poles to the signal is also greatly reduced.
5、使封装的体积与面积可以大幅度的缩小5. The volume and area of the package can be greatly reduced
因运用了引脚的延伸技术,所以可以容易的制作出高脚数与高密度的脚与脚之间的距离,使得封装的体积与面积可以大幅度的缩小。Due to the use of pin extension technology, it is easy to produce a high number of pins and a high-density pin-to-pin distance, so that the volume and area of the package can be greatly reduced.
6、材料成本和材料用量减少6. Reduced material cost and material consumption
因为将封装后的体积大幅度的缩小,更直接的体现出材料成本大幅度的下降与因为材料用量的减少也大幅度的减少废弃物环保的困扰。Because the volume after packaging is greatly reduced, it more directly reflects the substantial reduction in material costs and the reduction in the amount of materials used also greatly reduces the problem of waste and environmental protection.
(四)附图说明(4) Description of drawings
图1(A)~图1(R)为本发明双面图形芯片正装模组封装方法实施例1各工序示意图。FIG. 1(A) to FIG. 1(R) are schematic diagrams of each process in
图2为本发明双面图形芯片正装模组封装结构实施例1结构示意图。FIG. 2 is a structural schematic diagram of
图3为图2的俯视图。FIG. 3 is a top view of FIG. 2 .
图4(A)~图4(R)为本发明双面图形芯片正装模组封装方法实施例2各工序示意图。4(A) to 4(R) are schematic diagrams of each process in
图5为本发明双面图形芯片正装模组封装结构实施例2结构示意图。FIG. 5 is a structural schematic diagram of
图6为图5的俯视图。FIG. 6 is a top view of FIG. 5 .
图7(A)~图7(R)为本发明双面图形芯片正装模组封装方法实施例3各工序示意图。7(A) to 7(R) are schematic diagrams of each process in
图8为本发明双面图形芯片正装模组封装结构实施例3结构示意图。FIG. 8 is a structural schematic diagram of
图9为图8的俯视图。FIG. 9 is a top view of FIG. 8 .
图10(A)~图10(R)为本发明双面图形芯片正装模组封装方法实施例4各工序示意图。10(A) to 10(R) are schematic diagrams of each process in
图11为本发明双面图形芯片正装模组封装结构实施例4结构示意图。FIG. 11 is a structural schematic diagram of
图12为图11的俯视图。FIG. 12 is a top view of FIG. 11 .
图13(A)~图13(R)为本发明双面图形芯片正装模组封装方法实施例5各工序示意图。13(A) to 13(R) are schematic diagrams of each process in
图14为本发明双面图形芯片正装模组封装结构实施例5结构示意图。FIG. 14 is a structural schematic diagram of
图15为图14的俯视图。FIG. 15 is a top view of FIG. 14 .
图16(A)~图16(R)为本发明双面图形芯片正装模组封装方法实施例6各工序示意图。16(A) to 16(R) are schematic diagrams of each process in
图17为本发明双面图形芯片正装模组封装结构实施例6结构示意图。FIG. 17 is a structural schematic diagram of
图18为图17的俯视图。FIG. 18 is a top view of FIG. 17 .
图19(A)~图19(R)为本发明双面图形芯片正装模组封装方法实施例7各工序示意图。19(A) to 19(R) are schematic diagrams of each process in
图20为本发明双面图形芯片正装模组封装结构实施例7结构示意图。FIG. 20 is a structural schematic diagram of
图21为图20的俯视图。FIG. 21 is a top view of FIG. 20 .
图22(A)~图22(R)为本发明双面图形芯片正装模组封装方法实施例8各工序示意图。22(A) to 22(R) are schematic diagrams of each process in
图23为本发明双面图形芯片正装模组封装结构实施例8结构示意图。Fig. 23 is a structural schematic diagram of
图24为图23的俯视图。FIG. 24 is a top view of FIG. 23 .
图25(A)~图25(R)为本发明双面图形芯片正装模组封装方法实施例9各工序示意图。25(A) to 25(R) are schematic diagrams of each process in
图26为本发明双面图形芯片正装模组封装结构实施例9结构示意图。Fig. 26 is a structural schematic diagram of
图27为图26的俯视图。FIG. 27 is a top view of FIG. 26 .
图28(A)~图28(R)为本发明双面图形芯片正装模组封装方法实施例10各工序示意图。28(A) to 28(R) are schematic diagrams of each process in
图29为本发明双面图形芯片正装模组封装结构实施例10结构示意图。Fig. 29 is a structural schematic diagram of
图30为图29的俯视图。FIG. 30 is a top view of FIG. 29 .
图31(A)~图31(R)为本发明双面图形芯片正装模组封装方法实施例11各工序示意图。31(A) to 31(R) are schematic diagrams of each process in Embodiment 11 of the front-mount module packaging method for double-sided graphic chips of the present invention.
图32为本发明双面图形芯片正装模组封装结构实施例11结构示意图。FIG. 32 is a structural schematic diagram of Embodiment 11 of the package structure of the double-sided graphic chip front-mount module of the present invention.
图33为图32的俯视图。FIG. 33 is a top view of FIG. 32 .
图34(A)~图34(R)为本发明双面图形芯片正装模组封装方法实施例12各工序示意图。34(A) to 34(R) are schematic diagrams of each process in
图35为本发明双面图形芯片正装模组封装结构实施例12结构示意图。Fig. 35 is a structural schematic diagram of
图36为图35的俯视图。FIG. 36 is a top view of FIG. 35 .
图37(A)~图37(R)为本发明双面图形芯片正装模组封装方法实施例13各工序示意图。37(A) to 37(R) are schematic diagrams of each process in
图38为本发明双面图形芯片正装模组封装结构实施例13结构示意图。Fig. 38 is a structural schematic diagram of
图39为图38的俯视图。FIG. 39 is a top view of FIG. 38 .
图40(A)~图40(R)为本发明双面图形芯片正装模组封装方法实施例14各工序示意图。40(A) to 40(R) are schematic diagrams of each process in
图41为本发明双面图形芯片正装模组封装结构实施例14结构示意图。Fig. 41 is a structural schematic diagram of
图42为图41的俯视图。FIG. 42 is a top view of FIG. 41 .
图43(A)~图43(R)为本发明双面图形芯片正装模组封装方法实施例15各工序示意图。43(A) to 43(R) are schematic diagrams of each process in
图44为本发明双面图形芯片正装模组封装结构实施例15结构示意图。Fig. 44 is a structural schematic diagram of
图45为图44的俯视图。FIG. 45 is a top view of FIG. 44 .
图46(A)~图46(R)为本发明双面图形芯片正装模组封装方法实施例16各工序示意图。46(A) to 46(R) are schematic diagrams of each process in
图47为本发明双面图形芯片正装模组封装结构实施例16结构示意图。Fig. 47 is a structural schematic diagram of
图48为图47的俯视图。FIG. 48 is a top view of FIG. 47 .
图49(A)~图49(R)为本发明双面图形芯片正装模组封装方法实施例17各工序示意图。49(A) to 49(R) are schematic diagrams of each process in
图50为本发明双面图形芯片正装模组封装结构实施例17结构示意图。Fig. 50 is a structural schematic diagram of
图51为图50的俯视图。FIG. 51 is a top view of FIG. 50 .
图52(A)~图52(R)为本发明双面图形芯片正装模组封装方法实施例18各工序示意图。52(A) to 52(R) are schematic diagrams of each process in
图53为本发明双面图形芯片正装模组封装结构实施例18结构示意图。Fig. 53 is a structural schematic diagram of
图54为图53的俯视图。FIG. 54 is a top view of FIG. 53 .
图55(A)~图55(R)为本发明双面图形芯片正装模组封装方法实施例19各工序示意图。55(A) to 55(R) are schematic diagrams of each process in Embodiment 19 of the front-mount module packaging method for double-sided graphic chips of the present invention.
图56为本发明双面图形芯片正装模组封装结构实施例19结构示意图。Fig. 56 is a structural schematic diagram of Embodiment 19 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.
图57为图56的俯视图。FIG. 57 is a top view of FIG. 56 .
图58(A)~图58(R)为本发明双面图形芯片正装模组封装方法实施例20各工序示意图。58(A) to 58(R) are schematic diagrams of each process in
图59为本发明双面图形芯片正装模组封装结构实施例20结构示意图。Fig. 59 is a structural schematic diagram of
图60为图59的俯视图。FIG. 60 is a top view of FIG. 59 .
图61(A)~图61(R)为本发明双面图形芯片正装模组封装方法实施例21各工序示意图。61(A) to 61(R) are schematic diagrams of each process in Embodiment 21 of the front-mount module packaging method for double-sided graphic chips of the present invention.
图62为本发明双面图形芯片正装模组封装结构实施例21结构示意图。Fig. 62 is a structural schematic diagram of Embodiment 21 of the package structure of the double-sided graphic chip front-mount module of the present invention.
图63为图62的俯视图。FIG. 63 is a top view of FIG. 62 .
图64(A)~图64(R)为本发明双面图形芯片正装模组封装方法实施例22各工序示意图。64(A) to 64(R) are schematic diagrams of each process in Embodiment 22 of the front-mount module packaging method for double-sided graphic chips of the present invention.
图65为本发明双面图形芯片正装模组封装结构实施例22结构示意图。Fig. 65 is a structural schematic diagram of Embodiment 22 of the package structure of the double-sided graphic chip front-mount module of the present invention.
图66为图65的俯视图。FIG. 66 is a top view of FIG. 65 .
图67(A)~图67(R)为本发明双面图形芯片正装模组封装方法实施例23各工序示意图。67(A) to 67(R) are schematic diagrams of each process in Embodiment 23 of the front-mount module packaging method for double-sided graphic chips of the present invention.
图68为本发明双面图形芯片正装模组封装结构实施例23结构示意图。Fig. 68 is a structural schematic diagram of Embodiment 23 of the package structure of the double-sided graphic chip front-mount module of the present invention.
图69为图68的俯视图。FIG. 69 is a top view of FIG. 68 .
图70(A)~图70(R)为本发明双面图形芯片正装模组封装方法实施例24各工序示意图。70(A) to 70(R) are schematic diagrams of each process in Embodiment 24 of the front-mount module packaging method for double-sided graphic chips of the present invention.
图71为本发明双面图形芯片正装模组封装结构实施例24结构示意图。Fig. 71 is a structural schematic diagram of Embodiment 24 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.
图72为图71的俯视图。FIG. 72 is a top view of FIG. 71 .
图73(A)~图73(R)为本发明双面图形芯片正装模组封装方法实施例25各工序示意图。73(A) to 73(R) are schematic diagrams of each process in Embodiment 25 of the packaging method for a double-sided graphic chip front-mount module of the present invention.
图74为本发明双面图形芯片正装模组封装结构实施例25结构示意图。Fig. 74 is a structural schematic diagram of Embodiment 25 of the package structure of the double-sided graphic chip front-mount module of the present invention.
图75为图74的俯视图。FIG. 75 is a top view of FIG. 74 .
图76(A)~图76(R)为本发明双面图形芯片正装模组封装方法实施例26各工序示意图。76(A) to 76(R) are schematic diagrams of each process of the twenty-sixth embodiment of the front-mount module packaging method for double-sided graphics chips of the present invention.
图77为本发明双面图形芯片正装模组封装结构实施例26结构示意图。Fig. 77 is a structural schematic diagram of Embodiment 26 of the packaging structure of the double-sided graphic chip front-mount module of the present invention.
图78为图77的俯视图。FIG. 78 is a top view of FIG. 77 .
图79(A)~图79(R)为本发明双面图形芯片正装模组封装方法实施例27各工序示意图。79(A) to 79(R) are schematic diagrams of each process in
图80为本发明双面图形芯片正装模组封装结构实施例27结构示意图。Fig. 80 is a structural schematic diagram of
图81为图80的俯视图。FIG. 81 is a top view of FIG. 80 .
图82(A)~图82(R)为本发明双面图形芯片正装模组封装方法实施例28各工序示意图。82(A) to 82(R) are schematic diagrams of each process in
图83为本发明双面图形芯片正装模组封装结构实施例28结构示意图。Fig. 83 is a structural schematic diagram of
图84为图83的俯视图。FIG. 84 is a top view of FIG. 83 .
图85为以往采用金属基板的正面进行化学蚀刻及表面电镀层作业图。Fig. 85 is a working diagram of chemical etching and surface electroplating on the front side of a metal substrate in the past.
图86为以往形成的掉脚图。Fig. 86 is a diagram of a footfall formed in the past.
图87为以往的封装结构一示意图。Fig. 87 is a schematic diagram of a conventional package structure.
图88为87的俯视图。Figure 88 is a top view of 87.
图89为以往的封装结构二示意图。FIG. 89 is a schematic diagram of a second conventional package structure.
图90为89的俯视图。Figure 90 is a top view of 89.
图中附图标记:Reference signs in the figure:
基岛1、引脚2、无填料的塑封料(环氧树脂)3、第一金属层4、第二金属层5、导电或不导电粘结物质6、芯片7、金属线8、有填料塑封料(环氧树脂)9、柱子10、金属基板11、光阻胶膜12、光阻胶膜13、光阻胶膜14、光阻胶膜15、连筋16、光阻胶膜17、光阻胶膜18;第三基岛1.1、第三基岛1.2、第三基岛1.3、第四基岛1.4。
(五)具体实施方式(5) Specific implementation methods
本发明双面图形芯片正装模组封装结构及其封装方法如下:The packaging structure and packaging method of the double-sided graphics chip front-loading module of the present invention are as follows:
实施例1:单基岛单圈引脚Example 1: Single base island single turn pin
参见图2和图3,图2为本发明双面图形芯片正装模组封装结构实施例1结构示意图。图3为图2的俯视图。由图2和图3可以看出,本发明双面图形芯片正装模组封装结构,包括基岛1、引脚2、无填料的塑封料(环氧树脂)3、导电或不导电粘结物质6、芯片7、金属线8和有填料塑封料(环氧树脂)9,所述引脚2正面延伸到基岛1旁边,在所述基岛1和引脚2的正面设置有第一金属层4,在所述基岛1和引脚2的背面设置有第二金属层5,在所述基岛1正面第一金属层4上通过导电或不导电粘结物质6设置有芯片7,芯片7正面与引脚2正面第一金属层4之间用金属线8连接,在所述基岛1和引脚2的上部以及芯片7和金属线8外包封有填料塑封料(环氧树脂)9,在所述基岛1和引脚2外围的区域、引脚2与基岛1之间的区域以及引脚2与引脚2之间的区域嵌置有无填料的塑封料(环氧树脂)3,所述无填料的塑封料(环氧树脂)3将基岛1和引脚下部外围、引脚2下部与基岛1下部以及引脚2下部与引脚2下部连接成一体,且使所述基岛和引脚背面尺寸小于基岛和引脚正面尺寸,形成上大下小的基岛和引脚结构,在所述引脚2背面设置有柱子10,柱子10根部埋入所述无填料的塑封料(环氧树脂)3内。Referring to FIG. 2 and FIG. 3 , FIG. 2 is a structural schematic diagram of
其封装方法如下:Its packaging method is as follows:
步骤一、取金属基板
参见图1(A),取一片厚度合适的金属基板11。金属基板的材质可以依据芯片的功能与特性进行变换,例如:铜、铝、铁、铜合金或镍铁合金等。Referring to FIG. 1(A), take a metal substrate 11 with a suitable thickness. The material of the metal substrate can be changed according to the functions and characteristics of the chip, for example: copper, aluminum, iron, copper alloy or nickel-iron alloy.
步骤二、金属基板正面及背面被覆光阻胶膜
参见图1(B),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜12和13,以保护后续的电镀金属层工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(B), the front and back sides of the metal substrate are covered with
步骤三、金属基板正面的光阻胶膜进行需要电镀金属层区域的曝光/显影以及开窗Step 3: Expose/develop the photoresist film on the front of the metal substrate and open the window where the metal layer needs to be plated
参见图1(C),利用曝光显影设备将步骤二完成光阻胶膜被覆作业的金属基板正面进行曝光显影去除部分光阻胶膜,以露出金属基板正面后续需要进行电镀金属层的区域。Referring to FIG. 1(C), use exposure and development equipment to expose and develop the front of the metal substrate that has completed the photoresist film coating operation in
步骤四、金属基板正面已开窗的区域进行金属层电镀被覆
参见图1(D),对步骤三中金属基板正面已开窗的区域进行第一金属层4电镀被覆,该第一金属层4置于所述基岛1与引脚2的正面。Referring to FIG. 1(D), the
步骤五、金属基板正面及背面进行光阻胶膜去膜
参见图1(E),将金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除。Referring to FIG. 1(E), remove the remaining photoresist film on the front side of the metal substrate and the photoresist film on the back side of the metal substrate.
步骤六、金属基板正面及背面被覆光阻胶膜
参见图1(F),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜14和15,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(F), the front and back sides of the metal substrate are coated with
步骤七、金属基板的光阻胶膜进行需要双面蚀刻区域的曝光/显影以及开窗
参见图1(G),利用曝光显影设备将步骤六完成光阻胶膜被覆作业的金属基板正面及背面进行曝光显影去除部分光阻胶膜,以露出局部金属基板以备后续需要进行的金属基板双面蚀刻作业。Referring to Figure 1(G), use the exposure and development equipment to expose and develop the front and back of the metal substrate that has completed the photoresist film coating operation in
步骤八、金属基板进行双面蚀刻作业
参见图1(H),完成步骤七的曝光/显影以及开窗作业后,即在金属基板的正面及背面进行各图形的蚀刻作业,蚀刻出基岛1和引脚2的正面和背面,同时将引脚正面尽可能的延伸到基岛旁边,且使所述基岛1和引脚2的背面尺寸小于基岛1和引脚2的正面尺寸,形成上大下小的基岛1和引脚2结构;以及在引脚2背面形成柱子10,并在基岛1与引脚2之间和引脚2与引脚2之间留有连筋16。Referring to Fig. 1(H), after completing the exposure/development and window opening operation in
步骤九、金属基板正面及背面进行光阻胶膜去膜
参见图1(I),将金属基板正面和背面余下的光阻胶膜全部揭除,制成引线框,Referring to Figure 1 (I), the remaining photoresist films on the front and back of the metal substrate are all removed to form a lead frame.
步骤十、装片Step ten, loading film
参见图1(J),在基岛1正面第一金属层4上通过导电或不导电粘结物质6进行芯片7的植入。Referring to FIG. 1(J), the
步骤十一、打金属线Step 11, hit the metal wire
参见图1(K),将已完成芯片植入作业的半成品进行芯片正面与引脚正面第一金属层之间打金属线8作业。Referring to FIG. 1(K), the semi-finished product that has completed the chip implantation operation is subjected to the
步骤十二、包封有填料塑封料(环氧树脂)
参见图1(L),将已打线完成的半成品正面进行包封有填料塑封料(环氧树脂)9作业,并进行塑封料包封后的固化作业,使基岛和引脚的上部以及芯片和金属线外均被有填料塑封料(环氧树脂)包封。Referring to Figure 1(L), the front side of the semi-finished product that has been wired is encapsulated with filler molding compound (epoxy resin) 9, and the curing operation is performed after the molding compound is encapsulated, so that the base island and the upper part of the pin and Both the chip and the metal wire are encapsulated by a filler plastic compound (epoxy resin).
步骤十三、被覆光阻胶膜Step 13: Coating photoresist film
参见图1(M),利用被覆设备在将已完成包封有填料塑封料(环氧树脂)作业的半成品的正面及背面分别被覆可进行曝光显影的光阻胶膜17和18,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(M), the front and back of the semi-finished product that has been encapsulated with filler molding compound (epoxy resin) are coated with
步骤十四、已完成包封有填料塑封料(环氧树脂)作业的半成品的背面进行需要蚀刻区域的曝光/显影以及开窗
参见图1(N),利用曝光显影设备将步骤十三完成光阻胶膜被覆作业的已完成包封有填料塑封料(环氧树脂)作业的半成品背面进行曝光显影去除部分光阻胶膜,以露出步骤八金属基板双面蚀刻作业后留有的连筋16以及在引脚2背面形成的柱子10,以备后续需要进行柱子根部和连筋蚀刻作业。Referring to Fig. 1(N), use the exposure and development equipment to expose and develop the back of the semi-finished product that has completed the coating operation of the photoresist film in
步骤十五、第二次蚀刻作业Step fifteen, the second etching operation
参见图1(O),完成步骤十四的曝光/显影以及开窗作业后,即在完成包封有填料塑封料(环氧树脂)作业的半成品背面进行各图形的蚀刻作业,将步骤八金属基板双面蚀刻作业后留有的连筋16全部蚀刻掉,在这个过程中所述柱子10的根部也会同时的蚀刻掉相对的厚度,使柱子根部不露出包封后的封装结构背面,避免产生断路。Referring to Figure 1(O), after completing the exposure/development and window opening operations in step fourteen, the etching operation of each pattern is performed on the back of the semi-finished product that is encapsulated with filler molding compound (epoxy resin), and the step eight metal The
步骤十六、半成品正面及背面进行光阻胶膜去膜
参见图1(P),将完成步骤十五蚀刻作业的半成品背面余下的光阻胶膜以及半成品正面的光阻胶膜全部揭除。Referring to FIG. 1(P), the remaining photoresist film on the back of the semi-finished product and the photoresist film on the front of the semi-finished product after the etching operation in
步骤十七、包封无填料的塑封料(环氧树脂)Step seventeen, encapsulating the plastic compound (epoxy resin) without filler
参见图1(Q),将已完成步骤十六所述去膜作业的半成品背面进行包封无填料的塑封料(环氧树脂)作业,并进行塑封料包封后的固化作业,使基岛1和引脚2外围的区域、引脚2与基岛1之间的区域以及引脚2与引脚2之间的区域均嵌置无填料的塑封料(环氧树脂)3,该无填料的塑封料(环氧树脂)3将基岛1和引脚下部外围、引脚2下部与基岛1下部以及引脚2下部与引脚2下部连接成一体,且使所述柱子10根部埋入该无填料的塑封料(环氧树脂)3内。Referring to Figure 1(Q), the back of the semi-finished product that has completed the film removal operation described in
特别说明:但也因为多了所述柱子10在封装体内,反而在封装体内的结构更为强壮了(好比混泥土中增加了钢筋又有强度又有韧性)Special note: but also because there are
步骤十八、基岛和引脚的背面进行金属层电镀被覆
参见图1(R),对已完成步骤十七包封无填料塑封料作业的所述基岛和引脚的背面进行第二金属层5电镀被覆作业,而电镀的材料可以是锡、镍金、镍钯金....等金属材质。Referring to Fig. 1 (R), the
步骤十九、切割成品Step nineteen, cut the finished product
参见图2和图3,将已完成步骤十八第二金属层电镀被覆的半成品进行切割作业,使原本以列阵式集合体方式连在一起的芯片一颗颗独立开来,制得双面图形芯片正装模组封装结构成品。Referring to Figure 2 and Figure 3, the semi-finished product that has completed the electroplating and coating of the second metal layer in
实施例2:下沉基岛露出型单圈引脚Embodiment 2: sunken base island exposed type single-turn pin
参见图4~6,图4(A)~图4(R)为本发明双面图形芯片正装模组封装方法实施例2各工序示意图。图5为本发明双面图形芯片正装模组封装结构实施例2结构示意图。图6为图5的俯视图。由图4、图5和图6可以看出,实施例2与实施例1的不同之处仅在于:所述基岛1为下沉型基岛,即基岛1正面中央区域下沉。Referring to Figures 4-6, Figures 4(A)-4(R) are schematic diagrams of each process in
实施例3:埋入型基岛单圈引脚Embodiment 3: Embedded base island single-turn pin
参见图7~9,图7(A)~图7(R)为本发明双面图形芯片正装模组封装方法实施例3各工序示意图。图8为本发明双面图形芯片正装模组封装结构实施例3结构示意图。图9为图8的俯视图。由图7、图8和图9可以看出,实施例3与实施例1的不同之处仅在于:所述基岛1为埋入型基岛,即基岛1背面埋入所述无填料的塑封料(环氧树脂)3内。Referring to FIGS. 7 to 9, FIGS. 7(A) to 7(R) are schematic diagrams of each process in
实施例4:多凸点基岛露出型单圈引脚Embodiment 4: Multi-bump base island exposed single-turn pin
参见图10~12,图10(A)~图10(R)为本发明双面图形芯片正装模组封装方法实施例4各工序示意图。图11为本发明双面图形芯片正装模组封装结构实施例4结构示意图。图12为图11的俯视图。由图10、图11和图12可以看出,实施例4与实施例1的不同之处仅在于:所述基岛1为多凸点基岛,即基岛1表面设置有多个凸点。Referring to Figures 10-12, Figures 10(A)-10(R) are schematic diagrams of each process in
实施例5:基岛露出型多圈引脚Embodiment 5: Base island exposed multi-turn pin
参见图13~15,图13(A)~图13(R)为本发明双面图形芯片正装模组封装方法实施例5各工序示意图。图14为本发明双面图形芯片正装模组封装结构实施例5结构示意图。图15为图14的俯视图。由图13~15可以看出,实施例5与实施例1的不同之处在于:所述引脚2有多圈。Referring to Figures 13-15, Figures 13(A)-13(R) are schematic diagrams of each process in
实施例6:下沉基岛露出型多圈引脚Embodiment 6: sunken base island exposed multi-turn pin
参见图16~18,图16(A)~图16(R)为本发明双面图形芯片正装模组封装方法实施例6各工序示意图。图17为本发明双面图形芯片正装模组封装结构实施例6结构示意图。图18为图17的俯视图。由图16~18可以看出,实施例6与实施例2的不同之处在于:所述引脚2有多圈。Referring to Figures 16-18, Figures 16(A)-16(R) are schematic diagrams of each process in
实施例7:埋入型基岛多圈引脚Embodiment 7: Embedded base island multi-turn pin
参见图19~21,图19(A)~图19(R)为本发明双面图形芯片正装模组封装方法实施例7各工序示意图。图20为本发明双面图形芯片正装模组封装结构实施例7结构示意图。图21为图20的俯视图。由图19~21可以看出,实施例7与实施例3的不同之处在于:所述引脚2有多圈。Referring to Figures 19-21, Figures 19(A)-19(R) are schematic diagrams of each process in
实施例8:多凸点基岛露出型多圈引脚Embodiment 8: multi-bump base island exposed multi-turn pin
参见图22~24,图22(A)~图22(R)为本发明双面图形芯片正装模组封装方法实施例8各工序示意图。图23为本发明双面图形芯片正装模组封装结构实施例8结构示意图。图24为图23的俯视图。由图22~24可以看出,实施例8与实施例4的不同之处在于:所述引脚2有多圈。Referring to Figures 22-24, Figures 22(A)-22(R) are schematic diagrams of each process in
实施例9:多个基岛露出型单圈引脚Embodiment 9: Multiple base island exposed single-turn pins
参见图25~27,图25(A)~图25(R)为本发明双面图形芯片正装模组封装方法实施例9各工序示意图。图26为本发明双面图形芯片正装模组封装结构实施例9结构示意图。图27为图26的俯视图。由图25~27可以看出,实施例9与实施例1的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 25-27, Figures 25(A)-25(R) are schematic diagrams of each process in
实施例10:多个下沉基岛露出型单圈引脚Embodiment 10: Multiple sunken base island exposed single-turn pins
参见图28~30,图28(A)~图28(R)为本发明双面图形芯片正装模组封装方法实施例10各工序示意图。图29为本发明双面图形芯片正装模组封装结构实施例10结构示意图。图30为图29的俯视图。由图28~30可以看出,实施例10与实施例2的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 28-30, Figures 28(A)-28(R) are schematic diagrams of each process in
实施例11:多个埋入型基岛单圈引脚Example 11: Multiple Buried Base Island Single Turn Pins
参见图31~33,图31(A)~图31(R)为本发明双面图形芯片正装模组封装方法实施例11各工序示意图。图32为本发明双面图形芯片正装模组封装结构实施例11结构示意图。图33为图32的俯视图。由图31~33可以看出,实施例11与实施例3的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 31-33, Figures 31(A)-31(R) are schematic diagrams of each process in Embodiment 11 of the packaging method of a double-sided graphic chip front-mount module of the present invention. FIG. 32 is a structural schematic diagram of Embodiment 11 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 33 is a top view of FIG. 32 . It can be seen from FIGS. 31 to 33 that the difference between Embodiment 11 and
实施例12:多个多凸点基岛露出型单圈引脚Embodiment 12: Multiple multi-bump base island exposed single-turn pins
参见图34~36,图34(A)~图34(R)为本发明双面图形芯片正装模组封装方法实施例12各工序示意图。图35为本发明双面图形芯片正装模组封装结构实施例12结构示意图。图36为图35的俯视图。由图34~36可以看出,实施例12与实施例4的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 34 to 36, Figures 34(A) to 34(R) are schematic diagrams of each process in
实施例13:多个基岛露出型多圈引脚Embodiment 13: Multiple base island exposed multi-turn pins
参见图37~39,图37(A)~图37(R)为本发明双面图形芯片正装模组封装方法实施例13各工序示意图。图38为本发明双面图形芯片正装模组封装结构实施例13结构示意图。图39为图38的俯视图。由图37~39可以看出,实施例13与实施例1的不同之处在于:所述基岛1有多个,引脚2有多圈。Referring to Figures 37 to 39, Figures 37(A) to 37(R) are schematic diagrams of each process in
实施例14:多个下沉基岛露出型多圈引脚Embodiment 14: Exposed multi-turn pins with multiple sinking base islands
参见图40~42,图40(A)~图40(R)为本发明双面图形芯片正装模组封装方法实施例14各工序示意图。图41为本发明双面图形芯片正装模组封装结构实施例14结构示意图。图42为图41的俯视图。由图40~42可以看出,实施例14与实施例2的不同之处在于:所述基岛1有多个,引脚2有多圈。Referring to Figures 40-42, Figures 40(A)-40(R) are schematic diagrams of each process in
实施例15:多个埋入型基岛多圈引脚Example 15: Multiple Buried Base Island Multiturn Pins
参见图43~45,图43(A)~图43(R)为本发明双面图形芯片正装模组封装方法实施例15各工序示意图。图44为本发明双面图形芯片正装模组封装结构实施例15结构示意图。图45为图44的俯视图。由图43~45可以看出,实施例15与实施例3的不同之处在于:所述基岛1有多个,引脚2有多圈。Referring to Figures 43-45, Figures 43(A)-43(R) are schematic diagrams of each process in
实施例16:多个多凸点基岛露出型多圈引脚Embodiment 16: Multiple multi-bump base island exposed multi-turn pins
参见图46~48,图46(A)~图46(R)为本发明双面图形芯片正装模组封装方法实施例16各工序示意图。图47为本发明双面图形芯片正装模组封装结构实施例16结构示意图。图48为图47的俯视图。由图46~48可以看出,实施例16与实施例4的不同之处在于:所述基岛1有多个,引脚2有多圈。Referring to Figures 46-48, Figures 46(A)-46(R) are schematic diagrams of each process in
实施例17:基岛露出型及下沉基岛露出型单圈引脚Embodiment 17: base island exposed type and sunken base island exposed type single-turn pin
参见图49~51,图49(A)~图49(R)为本发明双面图形芯片正装模组封装方法实施例17各工序示意图。图50为本发明双面图形芯片正装模组封装结构实施例17结构示意图。图51为图50的俯视图。由图49~51可以看出,实施例17与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第二基岛1.2,所述第二基岛1.2正面中央区域下沉,在所述第一基岛1.1和引脚2的正面设置第一金属层4,在所述第一基岛1.1、第二基岛1.2和引脚2的背面设置第二金属层5,在第二基岛1.2正面中央下沉区域和第一基岛1.1正面通过导电或不导电粘结物质6设置芯片7,芯片7正面与引脚2正面第一金属层4之间以及芯片7与芯片7之间均用金属线8连接,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第一基岛1.1与第二基岛1.2之间的区域、第二基岛1.2与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第一基岛1.1下部、第一基岛1.1与第二基岛1.2下部、第二基岛1.2与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2有单圈。Referring to Figures 49-51, Figures 49(A)-49(R) are schematic diagrams of each process in
实施例18:基岛露出型及下沉基岛露出型多圈引脚Embodiment 18: Multi-turn pins with exposed base island and sunken base island exposed type
参见图52~54,图52(A)~图52(R)为本发明双面图形芯片正装模组封装方法实施例18各工序示意图。图53为本发明双面图形芯片正装模组封装结构实施例18结构示意图。图54为图53的俯视图。由图52~54可以看出,实施例18与实施例17的不同之处在于:所述引脚2有多圈。Referring to Figures 52-54, Figures 52(A)-52(R) are schematic diagrams of each process in
实施例19:基岛露出型及埋入型基岛单圈引脚Embodiment 19: base island exposed type and embedded type base island single-turn pin
参见图55~57,图55(A)~图55(R)为本发明双面图形芯片正装模组封装方法实施例19各工序示意图。图56为本发明双面图形芯片正装模组封装结构实施例19结构示意图。图57为图56的俯视图。由图55~57可以看出,实施例19与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第三基岛1.3,在所述第一基岛1.1第三基岛1.3和引脚2的正面设置第一金属层4,在所述第一基岛1.1和引脚2的背面设置第二金属层5,芯片7正面与引脚2正面第一金属层4之间以及芯片7与芯片7之间均用金属线8连接,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第三基岛1.3背面、第三基岛1.3与第一基岛1.1之间的区域、第三基岛1.3与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第一基岛1.1下部、第三基岛1.3背面、第三基岛1.3背面与第一基岛1.1下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有单圈。Referring to Figures 55-57, Figures 55(A)-55(R) are schematic diagrams of each process in Embodiment 19 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 56 is a structural schematic diagram of Embodiment 19 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 57 is a top view of FIG. 56 . It can be seen from Figures 55 to 57 that the difference between Embodiment 19 and
实施例20:基岛露出型及埋入型基岛多圈引脚Embodiment 20: base island exposed type and embedded type base island multi-turn pin
参见图58~60,图58(A)~图58(R)为本发明双面图形芯片正装模组封装方法实施例20各工序示意图。图59为本发明双面图形芯片正装模组封装结构实施例20结构示意图。图60为图59的俯视图。由图58~60可以看出,实施例20与实施例19的不同之处在于:所述引脚(2)有多圈。Referring to Figures 58-60, Figures 58(A)-58(R) are schematic diagrams of each process in
实施例21:基岛露出型及多凸点基岛露出型单圈引脚Embodiment 21: Exposed base island type and multi-bump base island exposed type single-turn pin
参见图61~63,图61(A)~图61(R)为本发明双面图形芯片正装模组封装方法实施例21各工序示意图。图62为本发明双面图形芯片正装模组封装结构实施例21结构示意图。图63为图62的俯视图。由图61~63可以看出,实施例21与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第四基岛1.4,所述第四基岛1.4正面设置成多凸点状结构,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第一基岛1.1与第四基岛1.4之间的区域、第四基岛1.4与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料的塑封料(环氧树脂)3将引脚下部外围、引脚2与第一基岛1.1下部、第一基岛1.1与第四基岛1.4下部、第四基岛1.4与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有单圈。Referring to Figures 61-63, Figures 61(A)-61(R) are schematic diagrams of each process in Embodiment 21 of the front-mount module packaging method for double-sided graphic chips of the present invention. Fig. 62 is a structural schematic diagram of Embodiment 21 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 63 is a top view of FIG. 62 . It can be seen from Figures 61 to 63 that the difference between Embodiment 21 and
实施例22:基岛露出型及多凸点基岛露出型多圈引脚Embodiment 22: Base island exposed type and multi-bump base island exposed multi-turn pin
参见图64~66,图64(A)~图64(R)为本发明双面图形芯片正装模组封装方法实施例22各工序示意图。图65为本发明双面图形芯片正装模组封装结构实施例22结构示意图。图66为图65的俯视图。由图64~66可以看出,实施例22与实施例21的不同之处在于:所述引脚2有多圈。Referring to Figures 64-66, Figures 64(A)-64(R) are schematic diagrams of each process in Embodiment 22 of the front-mount module packaging method for double-sided graphics chips of the present invention. Fig. 65 is a structural schematic diagram of Embodiment 22 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 66 is a top view of FIG. 65 . It can be seen from FIGS. 64 to 66 that the difference between Embodiment 22 and Embodiment 21 lies in that the
实施例23:下沉基岛露出型及埋入型基岛露出型单圈引脚Embodiment 23: sunken base island exposed type and buried base island exposed type single-turn pin
参见图67~69,图67(A)~图67(R)为本发明双面图形芯片正装模组封装方法实施例23各工序示意图。图68为本发明双面图形芯片正装模组封装结构实施例23结构示意图。图69为图68的俯视图。由图67~69可以看出,实施例23与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第二基岛1.2,另一组为第三基岛1.3,所述第二基岛1.2正面中央区域下沉,在第二基岛1.2正面中央下沉区域和第三基岛1.3正面通过导电或不导电粘结物质6设置芯片7,在所述引脚2外围的区域、引脚2与第二基岛1.2之间的区域、第三基岛1.3背面、第二基岛背面1.2与第二基岛1.2之间的区域、第三基岛1.3背面与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第二基岛1.2下部、第三基岛1.3、第三基岛1.3与第二基岛1.2下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 67-69, Figures 67(A)-67(R) are schematic diagrams of each process in Embodiment 23 of the front-mount module packaging method for double-sided graphics chips of the present invention. Fig. 68 is a structural schematic diagram of Embodiment 23 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 69 is a top view of FIG. 68 . It can be seen from Figures 67 to 69 that the difference between Embodiment 23 and
实施例24:下沉基岛露出型及埋入型基岛露出型多圈引脚Embodiment 24: sunken base island exposed type and buried base island exposed multi-turn pin
参见图70~72,图70(A)~图70(R)为本发明双面图形芯片正装模组封装方法实施例24各工序示意图。图71为本发明双面图形芯片正装模组封装结构实施例24结构示意图。图72为图71的俯视图。由图70~72可以看出,实施例24与实施例23的不同之处在于:所述引脚2有多圈。Referring to Figures 70-72, Figures 70(A)-70(R) are schematic diagrams of each process in Embodiment 24 of the front-mount module packaging method for double-sided graphics chips of the present invention. Fig. 71 is a structural schematic diagram of Embodiment 24 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 72 is a top view of FIG. 71 . It can be seen from FIGS. 70-72 that the difference between Embodiment 24 and Embodiment 23 lies in that the
实施例25:下沉基岛露出型及多凸点基岛露出型单圈引脚Embodiment 25: Sunken base island exposed type and multi-bump base island exposed single-turn pin
参见图73~75,图73(A)~图73(R)为本发明双面图形芯片正装模组封装方法实施例25各工序示意图。图74为本发明双面图形芯片正装模组封装结构实施例25结构示意图。图75为图74的俯视图。由图73~75可以看出,实施例25与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第二基岛1.2,另一组为第四基岛1.4,所述第二基岛1.2正面中央区域下沉,第四基岛1.4正面设置成多凸点状结构,在所述第四基岛1.4和引脚2的正面设置第一金属层4,在所述第二基岛1.2、第四基岛1.4和引脚2的背面设置第二金属层5,在所述第二基岛1.2正面中央下沉区域和第四基岛1.4正面通过导电或不导电粘结物质6设置芯片7,在所述引脚2外围的区域、引脚2与第二基岛1.2之间的区域、第二基岛1.2与第四基岛1.4之间的区域、第四基岛1.4与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料的塑封料(环氧树脂)3将引脚下部外围、引脚2与第二基岛1.2下部、第二基岛1.2与第四基岛1.4下部、第四基岛1.4与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 73 to 75, Figures 73(A) to 73(R) are schematic diagrams of each process in Embodiment 25 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 74 is a structural schematic diagram of Embodiment 25 of the package structure of the double-sided graphic chip front-mount module of the present invention. FIG. 75 is a top view of FIG. 74 . It can be seen from Figures 73 to 75 that the difference between Embodiment 25 and
实施例26:下沉基岛露出型及多凸点基岛露出型多圈引脚Embodiment 26: sunken base island exposed type and multi-bump base island exposed multi-turn pin
参见图76~78,图76(A)~图76(R)为本发明双面图形芯片正装模组封装方法实施例26各工序示意图。图77为本发明双面图形芯片正装模组封装结构实施例26结构示意图。图78为图77的俯视图。由图76~78可以看出,实施例26与实施例25的不同之处在于:所述引脚2有多圈。Referring to Figures 76-78, Figures 76(A)-76(R) are schematic diagrams of each process in Embodiment 26 of the packaging method for a double-sided graphic chip front-mount module of the present invention. Fig. 77 is a structural schematic diagram of Embodiment 26 of the packaging structure of the double-sided graphic chip front-mount module of the present invention. FIG. 78 is a top view of FIG. 77 . It can be seen from FIGS. 76 to 78 that the difference between Embodiment 26 and Embodiment 25 lies in that the
实施例27:埋入型基岛及多凸点基岛露出型单圈引脚Embodiment 27: Embedded base island and multi-bump base island exposed single-turn pin
参见图79~81,图79(A)~图79(R)为本发明双面图形芯片正装模组封装方法实施例27各工序示意图。图80为本发明双面图形芯片正装模组封装结构实施例27结构示意图。图81为图80的俯视图。由图79~81可以看出,实施例27与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第三基岛1.3,另一组为第四基岛1.4,所述第四基岛1.4正面设置成多凸点状结构,在所述第三基岛1.3、第四基岛1.4和引脚2的正面设置第一金属层4,在所述第四基岛1.4和引脚2的背面设置第二金属层5,在所述引脚2外围的区域、引脚2与第四基岛1.4之间的区域、第三基岛1.3背面、第二基岛1.2与第四基岛1.4之间的区域、第三基岛1.3与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第四基岛1.4下部、第三基岛1.3背面、第三基岛1.3背面与第四基岛1.4下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 79-81, Figures 79(A)-79(R) are schematic diagrams of each process in
实施例28:埋入型基岛及多凸点基岛露出型多圈引脚Embodiment 28: Embedded base island and multi-bump base island exposed multi-turn pin
参见图82~84,图82(A)~图82(R)为本发明双面图形芯片正装模组封装方法实施例28各工序示意图。图83为本发明双面图形芯片正装模组封装结构实施例28结构示意图。图84为图83的俯视图。由图82~84可以看出,实施例28与实施例27的不同之处在于:所述引脚2有多圈。Referring to Figures 82 to 84, Figures 82(A) to 82(R) are schematic diagrams of each process in
Claims (15)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010102730299A CN101958305B (en) | 2010-09-04 | 2010-09-04 | Double-sided graphics chip front-mount module packaging structure and packaging method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010102730299A CN101958305B (en) | 2010-09-04 | 2010-09-04 | Double-sided graphics chip front-mount module packaging structure and packaging method |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101958305A CN101958305A (en) | 2011-01-26 |
CN101958305B true CN101958305B (en) | 2012-09-19 |
Family
ID=43485553
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2010102730299A Active CN101958305B (en) | 2010-09-04 | 2010-09-04 | Double-sided graphics chip front-mount module packaging structure and packaging method |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101958305B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103824782A (en) * | 2014-01-29 | 2014-05-28 | 南通富士通微电子股份有限公司 | QFN frame manufacturing method |
JP6577373B2 (en) * | 2016-01-18 | 2019-09-18 | 新光電気工業株式会社 | Lead frame, manufacturing method thereof, and semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1635635A (en) * | 2004-12-17 | 2005-07-06 | 江苏长电科技股份有限公司 | Direct-coupled chip package structure |
CN201051498Y (en) * | 2007-05-30 | 2008-04-23 | 宁波康强电子股份有限公司 | Integrated circuit out lead framework |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100744138B1 (en) * | 2006-06-22 | 2007-08-01 | 삼성전자주식회사 | Ball Grid Array Semiconductor Package and Manufacturing Method Thereof |
US7989930B2 (en) * | 2007-10-25 | 2011-08-02 | Infineon Technologies Ag | Semiconductor package |
TWI364820B (en) * | 2008-03-07 | 2012-05-21 | Chipmos Technoligies Inc | Chip structure |
CN201936875U (en) * | 2010-09-04 | 2011-08-17 | 江苏长电科技股份有限公司 | Double-sided graphic chip normal-mounting module packaging structure |
-
2010
- 2010-09-04 CN CN2010102730299A patent/CN101958305B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1635635A (en) * | 2004-12-17 | 2005-07-06 | 江苏长电科技股份有限公司 | Direct-coupled chip package structure |
CN201051498Y (en) * | 2007-05-30 | 2008-04-23 | 宁波康强电子股份有限公司 | Integrated circuit out lead framework |
Also Published As
Publication number | Publication date |
---|---|
CN101958305A (en) | 2011-01-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101958300B (en) | Double-sided graphic chip inversion module packaging structure and packaging method thereof | |
CN101950726B (en) | First-coating last-etching single package method for positively packaging double-sided graphic chip | |
CN103400767B (en) | First sealing chip flipchip bump three-dimensional systematic metal circuit board and process after erosion | |
CN101814482A (en) | Base island lead frame structure and production method thereof | |
CN101958257B (en) | Packaging method of directly placing firstly-plated and later-etched module by double-sided graphic chip | |
CN101958303B (en) | Double-side graph chip forward single package structure and package method thereof | |
CN101969032A (en) | Double-sided graphic chip right-handed electroplating-etching module packaging method | |
CN101958305B (en) | Double-sided graphics chip front-mount module packaging structure and packaging method | |
CN101958299B (en) | Method for packaging single double-sided graphic chip by way of directly arranging and then sequentially plating and etching | |
CN101958301B (en) | Double-side graph chip direct-put single package structure and package method thereof | |
CN103400777B (en) | First sealing chip formal dress salient point three-dimensional systematic metal circuit board and process after erosion | |
CN201936875U (en) | Double-sided graphic chip normal-mounting module packaging structure | |
CN201936874U (en) | Double-sided graphics chip positive single packaging structure | |
CN102683315B (en) | Barrel-plating four-side pinless packaging structure and manufacturing method thereof | |
CN201838577U (en) | Module packaging structure for inverted mounting of chip with double-sided graphics | |
CN102005430B (en) | Double-sided graphics chip flip-chip module packaging method adopting plating firstly and etching secondly | |
CN101958304B (en) | Double-side graph chip direct-put module package structure and package method thereof | |
CN101958302B (en) | Double-side graph chip inverse single package structure and package method thereof | |
CN102420206A (en) | Four-side pin-free packaging structure subjected to plating and etching sequentially and manufacturing method thereof | |
CN201838576U (en) | Single packaging structure for direct arranging of chip with double-sided graphics | |
CN201838579U (en) | Module packaging structure for direct arranging of chip with double-sided graphics | |
CN102867791B (en) | Multi-chip reversely-arranged etched-encapsulated base island-buried encapsulating structure and manufacturing method thereof | |
CN201927599U (en) | Module package structure for plating prior to etching of double-sided graphic flip chips | |
CN202003984U (en) | Single first-plating second-etching packaging structure of flip chip with double-sided graphs | |
CN202003985U (en) | Directly placed, first plated, then carved single packaging structure of two-sided figure chip |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |