CN201936874U - Double-sided graphics chip positive single packaging structure - Google Patents
Double-sided graphics chip positive single packaging structure Download PDFInfo
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- CN201936874U CN201936874U CN2010205178864U CN201020517886U CN201936874U CN 201936874 U CN201936874 U CN 201936874U CN 2010205178864 U CN2010205178864 U CN 2010205178864U CN 201020517886 U CN201020517886 U CN 201020517886U CN 201936874 U CN201936874 U CN 201936874U
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Abstract
本实用新型涉及一种双面图形芯片正装单颗封装结构,所述结构包括基岛(1)、引脚(2)、无填料的塑封料(环氧树脂)(3)、导电或不导电粘结物质(6)、芯片(7)、金属线(8)和有填料塑封料(环氧树脂)(9),所述引脚(2)正面延伸到基岛(1)旁边,所述无填料的塑封料(3)将基岛(1)和引脚(2)下部外围、引脚(2)下部与基岛(1)下部以及引脚(2)下部与引脚(2)下部连接成一体,且使基岛和引脚背面尺寸小于基岛和引脚正面尺寸,形成上大下小的基岛和引脚结构,有填料塑封料(9)将引脚(2)正面局部单元进行包覆,在引脚(2)背面设置有柱子(10),柱子(10)根部埋入所述无填料的塑封料(3)内。本实用新型装片时可承受超高温且不会因不同物质的不同物理性质而产生引线框扭曲,也不会再有产生掉脚的问题和能使金属线的长度缩短的问题。
The utility model relates to a double-sided graphic chip front-loading single-chip packaging structure, the structure includes a base island (1), pins (2), plastic sealing compound (epoxy resin) (3) without filler, conductive or non-conductive Adhesive substance (6), chip (7), metal wire (8) and filler molding compound (epoxy resin) (9), the front side of the pin (2) extends to the side of the base island (1), the Filler-free molding compound (3) connects base island (1) and pin (2) lower periphery, pin (2) lower part and base island (1) lower part and pin (2) lower part and pin (2) lower part Connect into one, and make the size of the base island and the back of the pin smaller than the size of the base island and the front of the pin to form a structure of the base island and the pin with a large upper part and a smaller bottom. The unit is covered, and a column (10) is arranged on the back of the pin (2), and the root of the column (10) is embedded in the plastic sealing compound (3) without filler. The utility model can withstand ultra-high temperature during chip loading, and the lead frame will not be distorted due to different physical properties of different substances, and the problem of missing feet and shortening the length of metal wires will no longer occur.
Description
(一)技术领域(1) Technical field
本实用新型涉及一种双面图形芯片正装单颗封装结构。属于半导体封装技术领域。The utility model relates to a front-mounted single-chip package structure of a double-sided graphics chip. It belongs to the technical field of semiconductor packaging.
(二)背景技术(2) Background technology
传统的芯片封装结构的制作方式是:采用金属基板的正面进行化学蚀刻及表面电镀层后,即完成引线框的制作(如图43所示)。而引线框的背面则在封装过程中再进行蚀刻。该法存在以下不足:The traditional manufacturing method of the chip package structure is: after chemical etching and surface electroplating are performed on the front side of the metal substrate, the production of the lead frame is completed (as shown in FIG. 43 ). The backside of the leadframe is etched during the packaging process. This law has the following shortcomings:
因为塑封前只在金属基板正面进行了半蚀刻工作,而在塑封过程中塑封料只有包裹住引脚半只脚的高度,所以塑封体与引脚的束缚能力就变小了,如果塑封体贴片到PCB板上不是很好时,再进行返工重贴,就容易产生掉脚的问题(如图44所示)。尤其塑封料的种类是采用有填料时候,因为材料在生产过程的环境与后续表面贴装的应力变化关系,会造成金属与塑封料产生垂直型的裂缝,其特性是填料比例越高则越硬越脆越容易产生裂缝。Because only half-etching work is done on the front of the metal substrate before plastic sealing, and the plastic sealing material is only half a foot high to cover the pins during the plastic sealing process, so the binding ability between the plastic package and the pins becomes smaller. If the plastic package is considerate When the chip is not well attached to the PCB board, rework and re-attachment will easily cause the problem of foot drop (as shown in Figure 44). Especially when the type of molding compound is filled, because the relationship between the environment of the material in the production process and the stress change of the subsequent surface mount will cause vertical cracks between the metal and the molding compound, the characteristic is that the higher the filler ratio, the harder it is The more brittle the easier it is to crack.
另外,由于芯片与引脚之间的距离较远,金属线的长度较长,如图45~46所示,金属线成本较高(尤其是昂贵的纯金质的金属线);同样由于金属线的长度较长,使得芯片的信号输出速度较慢(尤其是存储类的产品以及需要大量数据的计算,更为突出);也同样由于金属线的长度较长,所以在金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也较高;再由于芯片与引脚之间的距离较远,使得封装的体积与面积较大,材料成本较高,废弃物较多。In addition, due to the long distance between the chip and the pins, the length of the metal wire is relatively long, as shown in Figures 45-46, the cost of the metal wire is relatively high (especially the expensive pure gold metal wire); The length of the wire is longer, which makes the signal output speed of the chip slower (especially for storage products and calculations that require a large amount of data); The interference of parasitic resistance/capacitance and parasitic poles on the signal is also high; and because the distance between the chip and the pins is long, the volume and area of the package are large, the cost of materials is high, and there is more waste.
为此,本申请人在先申请了一件名称为《有基岛引线框结构及其生产方法》的发明专利,其申请号为:201010165476.0。其主要技术特征是:采用金属基板的背面先进行半蚀刻,在金属基板的背面形成凹陷的半蚀刻区域,同时相对形成基岛和引脚的背面,再在所述半蚀刻区域,填涂上无填料的软性填缝剂,并同时进行烘烤,使无填料的软性填缝剂固化成无填料的塑封料(环氧树脂),以包裹住引脚的背面。然后再在金属基板的正面进行半蚀刻,同时相对形成基岛和引脚的正面。其有益效果主要有:For this reason, the applicant previously applied for an invention patent titled "Based Island Lead Frame Structure and Its Production Method", and its application number is: 201010165476.0. Its main technical features are: use the back of the metal substrate to half-etch first, form a recessed half-etched area on the back of the metal substrate, and at the same time form the base island and the back of the pin relatively, and then fill and coat the half-etched area. Filler-free soft sealant, and bake at the same time, so that the filler-free soft sealant cures into a filler-free molding compound (epoxy resin) to wrap the backside of the pin. Then half etch is performed on the front side of the metal substrate, and at the same time, the base island and the front side of the pin are relatively formed. Its beneficial effects mainly include:
1)由于在所述金属基板的背面引脚与引脚间的区域嵌置有无填料的软性填缝剂,该无填料的软性填缝剂与在塑封过程中的金属基板正面的常规有填料塑封料(环氧树脂)一起包裹住整个引脚的高度,所以塑封体与引脚的束缚能力就变大了,不会再有产生掉脚的问题,如图47。1) Since the area between the pins and the pins on the back of the metal substrate is embedded with a soft sealant without filler, the soft sealant without filler is different from the conventional sealant on the front side of the metal substrate in the plastic sealing process. There is a filler plastic compound (epoxy resin) that covers the entire height of the pins together, so the binding capacity between the plastic package and the pins becomes larger, and there will be no problem of falling feet, as shown in Figure 47.
2)由于采用了引线框正面与背面分开蚀刻作业的方法,所以在蚀刻作业中可形成背面引脚的尺寸稍小而正面引脚尺寸稍大的结构,而同个引脚的上下大小不同尺寸在被无填料的塑封料(环氧树脂)所包裹的更紧更不容易产生滑动而掉脚。2) Due to the method of separate etching operations on the front and back of the lead frame, a structure in which the size of the back pins is slightly smaller and the size of the front pins is slightly larger can be formed during the etching operation, while the upper and lower sizes of the same pin are different It is tighter and less likely to slip and fall when it is wrapped by a filler-free molding compound (epoxy resin).
3)由于应用了引线框背面与正面分开蚀刻的技术,所以能够将引线框正面的引脚尽可能的延伸到基岛的旁边,促使芯片与引脚距离大幅的缩短,如图47~48,如此金属线所使用的成本也可以大幅的降低(尤其是昂贵的纯金质的金属线)。3) Due to the application of the technology of separate etching on the back and front of the lead frame, the pins on the front of the lead frame can be extended to the side of the base island as much as possible, which greatly shortens the distance between the chip and the pins, as shown in Figures 47-48. The cost of such metal wires can also be greatly reduced (especially expensive pure gold metal wires).
4)也因为金属线的缩短使得芯片的信号输出速度也大幅的增速(尤其存储类的产品以及需要大量数据的计算,更为突出),由于金属线的长度变短了,所以金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也大幅度的降低。4) Also because of the shortening of the metal wire, the signal output speed of the chip is also greatly increased (especially for storage products and calculations that require a large amount of data), and because the length of the metal wire is shortened, the metal wire The interference of the existing parasitic resistance/capacitance and parasitic poles to the signal is also greatly reduced.
5)因运用了引脚的延伸技术,所以可以容易的制作出高脚数与高密度的脚之间的距离,使得封装的体积与面积可以大幅度的缩小。5) Due to the use of pin extension technology, the distance between high pin count and high density pins can be easily produced, so that the volume and area of the package can be greatly reduced.
6)因为将封装后的体积大幅度的缩小,更直接的体现出材料成本大幅度的下降与因为材料用量的减少也大幅度的减少废弃物环保的困扰。6) Because the volume after packaging is greatly reduced, it more directly reflects the substantial reduction of material costs and the reduction of material consumption also greatly reduces the environmental problems of waste and environmental protection.
但是,还是存在有以下的不足:由于封装前先进行引线框背面无填料塑封料的包裹引脚作业,再进行引线框正面的高温装片和打线作业时,因引线框和无填料塑封料两种材料的物理性能不同,两种材料的膨胀系数也不同,在高温下受热形变不同,导致后续装片时引线框产生扭曲。因此该种封装结构在装片时不能够耐超高温(200℃以上)。而以往是通过把封装体体积做得很大来达到耐高温的要求,但现在要求封装体的体积越来越小而功率是越来越大的情况下就耐不了超高温了。However, there are still following deficiencies: before encapsulation, the wrapping pin operation of the backside of the lead frame without filler molding compound is carried out, and when the high-temperature chip loading and wiring operations on the front of the lead frame are carried out, the lead frame and the filler-free plastic sealant The physical properties of the two materials are different, the coefficients of expansion of the two materials are also different, and the thermal deformation at high temperature is different, which leads to distortion of the lead frame during subsequent chip mounting. Therefore, this kind of packaging structure cannot withstand ultra-high temperature (above 200° C.) during chip loading. In the past, the requirement of high temperature resistance was achieved by making the volume of the package body large, but now the volume of the package body is required to be smaller and the power is larger and larger, and it cannot withstand ultra-high temperature.
(三)发明内容(3) Contents of the invention
本实用新型的目的在于克服上述不足,提供一种装片时可承受超高温且不会因不同物质的不同物理性质而产生引线框扭曲,也不会再有产生掉脚的问题和能使金属线的长度缩短的双面图形芯片正装单颗封装结构。The purpose of this utility model is to overcome the above-mentioned shortcomings, and to provide a lead frame that can withstand ultra-high temperature during chip loading and will not cause distortion of the lead frame due to different physical properties of different substances, and will not cause the problem of falling feet and can make the metal Double-sided graphics chips with shortened line length are mounted in single-chip package structure.
本实用新型的目的是这样实现的:一种双面图形芯片正装单颗封装结构,包括基岛、引脚、无填料的塑封料(环氧树脂)、导电或不导电粘结物质、芯片、金属线和有填料塑封料(环氧树脂),所述引脚正面延伸到基岛旁边,在所述基岛和引脚的正面设置有第一金属层,在所述基岛和引脚的背面设置有第二金属层,在所述基岛正面第一金属层上通过导电或不导电粘结物质设置有芯片,芯片正面与引脚正面第一金属层之间用金属线连接,在所述基岛和引脚的上部以及芯片和金属线外包封有填料塑封料(环氧树脂),在所述基岛和引脚外围的区域、引脚与基岛之间的区域以及引脚与引脚之间的区域嵌置有无填料的塑封料(环氧树脂),所述无填料的塑封料(环氧树脂)将基岛和引脚下部外围、引脚下部与基岛下部以及引脚下部与引脚下部连接成一体,且使所述基岛和引脚背面尺寸小于基岛和引脚正面尺寸,形成上大下小的基岛和引脚结构,其特点是:所述有填料塑封料(环氧树脂)将引脚正面局部单元进行包覆,在所述引脚背面设置有柱子,柱子根部埋入所述无填料的塑封料(环氧树脂)内。The purpose of this utility model is achieved like this: a kind of double-sided figure chip is adorned single encapsulation structure, comprises base island, pin, plastic encapsulant (epoxy resin) without filler, conductive or non-conductive bonding substance, chip, Metal wire and filler molding compound (epoxy resin), the front of the pin extends to the side of the base island, a first metal layer is arranged on the front of the base island and the pin, and the front of the base island and the pin The back side is provided with a second metal layer, and a chip is provided on the first metal layer on the front side of the base island through a conductive or non-conductive adhesive substance. The front side of the chip is connected with the first metal layer on the front side of the pin with a metal wire. The upper part of the base island and the pins, as well as the chip and the metal wires are encapsulated with filler molding compound (epoxy resin), the area around the base island and the pins, the area between the pins and the base island, and the pins and the pins. The area between the pins is embedded with an unfilled molding compound (epoxy) that connects the base island to the lower periphery of the pin, the lower portion of the pin to the lower portion of the base island, and the lead The lower part of the foot is integrated with the lower part of the pin, and the size of the base island and the back of the pin is smaller than the size of the base island and the front of the pin, forming a base island and pin structure with a large top and a small bottom, which is characterized by: the Filler molding compound (epoxy resin) covers the partial unit on the front of the pin, and a pillar is arranged on the back of the pin, and the root of the pillar is buried in the molding compound (epoxy resin) without filler.
本实用新型的有益效果是:The beneficial effects of the utility model are:
1、引线框耐超高温(200℃以上)1. The lead frame is ultra-high temperature resistant (above 200°C)
由于采用了双面图形蚀刻引线框技术,一次完成引线框的正、背两面双面蚀刻,同时封装时先进行引线框正面的高温装片打线再进行引线框背面的引脚包裹作业,使装片打线时只有引线框一种材料,在使用超高温的制程过程中因没有多种材料膨胀系数不同所带来的冲击,确保了引线框的耐超高温(一般是200℃以下)性能。Due to the use of double-sided graphic etching lead frame technology, the front and back double-sided etching of the lead frame is completed at one time. At the same time, when packaging, the high-temperature chip mounting and wiring on the front of the lead frame is performed first, and then the pin wrapping operation on the back of the lead frame is performed. There is only one material of the lead frame for chip loading and wiring. In the process of using ultra-high temperature, there is no impact caused by different expansion coefficients of various materials, which ensures the ultra-high temperature resistance (generally below 200°C) performance of the lead frame. .
2、能确保引线框装片强度2. It can ensure the strength of the lead frame
因为不先做预包封,引线框装片时承受的压力大,打线时会使引线框产生振动,引线框会出现下陷现象。本实用新型通过在引线框背面留有柱子的设计,以增加打线时引线框的强度。Because the pre-encapsulation is not done first, the pressure on the lead frame is high when the chip is loaded, and the lead frame will vibrate when the wire is bonded, and the lead frame will sag. The utility model adopts the design of pillars on the back of the lead frame to increase the strength of the lead frame when wiring.
3、确保不会再有产生掉脚的问题3. Make sure that there will be no more problems with feet falling
由于采用了双面蚀刻的工艺技术,所以可以轻松的规划设计与制造出上大下小的引脚结构,可以使上下层塑封料紧密的将上大下小的引脚结构一起包裹住,所以塑封体与引脚的束缚能力就变大了,不会再有产生掉脚的问题。Due to the use of double-sided etching technology, it is easy to plan, design and manufacture pin structures with upper and lower pins, and the upper and lower plastic molding compounds can tightly wrap the upper and lower pin structures together, so The binding ability between the plastic package and the pins becomes larger, and there will be no more problems of falling feet.
4、确保金属线的长度缩短4. Make sure the length of the metal wire is shortened
1)由于应用了引线框背面与正面同时且分开蚀刻的技术,所以能够将引线框正面的引脚尽可能的延伸到后续需装芯片的区域旁边,促使芯片与引脚距离大幅的缩短,如图47~图48,如此金属线的长度也缩短了,金属线的成本也可以大幅的降低(尤其是昂贵的纯金质的金属线);1) Due to the application of the technology of simultaneous and separate etching on the back and front of the lead frame, the pins on the front of the lead frame can be extended as far as possible to the side of the area where the chip needs to be installed later, which greatly shortens the distance between the chip and the pin, such as As shown in Fig. 47 to Fig. 48, the length of the metal wire is also shortened, and the cost of the metal wire can also be greatly reduced (especially the expensive pure gold metal wire);
2)也因为金属线的长度缩短使得芯片的信号输出速度也大幅的增速(尤其存储类的产品以及需要大量数据的计算,更为突出),由于金属线的长度变短了,所以金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也大幅度的降低。2) Also because the length of the metal wire is shortened, the signal output speed of the chip is also greatly increased (especially for storage products and calculations that require a large amount of data). The interference of the existing parasitic resistance/capacitance and parasitic poles to the signal is also greatly reduced.
5、使封装的体积与面积可以大幅度的缩小5. The volume and area of the package can be greatly reduced
因运用了引脚的延伸技术,所以可以容易的制作出高脚数与高密度的脚与脚之间的距离,使得封装的体积与面积可以大幅度的缩小。Due to the use of pin extension technology, it is easy to produce a high number of pins and a high-density pin-to-pin distance, so that the volume and area of the package can be greatly reduced.
6、材料成本和材料用量减少6. Reduced material cost and material consumption
因为将封装后的体积大幅度的缩小,更直接的体现出材料成本大幅度的下降与因为材料用量的减少也大幅度的减少废弃物环保的困扰。Because the volume after packaging is greatly reduced, it more directly reflects the substantial reduction in material costs and the reduction in the amount of materials used also greatly reduces the problem of waste and environmental protection.
7、采用局部單元的单颗封装的优点有:7. The advantages of using a single package of local units are:
1)在不同的应用中可以将塑封体边缘的引脚伸出塑封体。1) In different applications, the pins on the edge of the plastic package can be extended out of the plastic package.
2)塑封体边缘的引脚伸出塑封体外可以清楚的检查出焊接在PCB板上的情况。2) The pins on the edge of the plastic package extend out of the plastic package to clearly check the soldering on the PCB.
3)模块型的面积较大会容易因为多种不同的材料结构所产生收缩率不同的应立变形,而局部单元的单颗封装就可以完全分散多种不同的材料结构所产生收缩率不同的应立变形。3) The large area of the modular type will easily cause the deformation of the different shrinkage rates due to a variety of different material structures, and the single package of the local unit can completely disperse the different shrinkage rates of the different material structures. vertical deformation.
4)单颗封装在进行塑封体切割分离时,因为要切割的厚度只有引脚的厚度,所以切割的速度可以比模块型的封装结构要来得快很多,且切割用的刀片因为切割的厚度便薄了所以切割刀片的寿命相对的也就变的更长了。4) When a single package is cut and separated from the plastic package, because the thickness to be cut is only the thickness of the pin, the cutting speed can be much faster than that of the modular package structure, and the cutting blade is easy to cut because of the cutting thickness. It is thinner, so the life of the cutting blade is relatively longer.
(四)附图说明(4) Description of drawings
图1(A)~图1(R)为本实用新型双面图形芯片正装单颗封装方法实施例1各工序示意图。1(A) to 1(R) are schematic diagrams of each process in
图2为本实用新型双面图形芯片正装单颗封装结构实施例1结构示意图。Fig. 2 is a structural schematic diagram of
图3为图2的俯视图。FIG. 3 is a top view of FIG. 2 .
图4(A)~图4(R)为本实用新型双面图形芯片正装单颗封装方法实施例2各工序示意图。4(A) to 4(R) are schematic diagrams of each process in
图5为本实用新型双面图形芯片正装单颗封装结构实施例2结构示意图。Fig. 5 is a structural schematic diagram of
图6为图5的俯视图。FIG. 6 is a top view of FIG. 5 .
图7(A)~图7(R)为本实用新型双面图形芯片正装单颗封装方法实施例3各工序示意图。7(A) to 7(R) are schematic diagrams of each process in
图8为本实用新型双面图形芯片正装单颗封装结构实施例3结构示意图。Fig. 8 is a structural schematic diagram of
图9为图8的俯视图。FIG. 9 is a top view of FIG. 8 .
图10(A)~图10(R)为本实用新型双面图形芯片正装单颗封装方法实施例4各工序示意图。10(A) to 10(R) are schematic diagrams of each process in
图11为本实用新型双面图形芯片正装单颗封装结构实施例4结构示意图。FIG. 11 is a structural schematic diagram of
图12为图11的俯视图。FIG. 12 is a top view of FIG. 11 .
图13(A)~图13(R)为本实用新型双面图形芯片正装单颗封装方法实施例5各工序示意图。13(A) to 13(R) are schematic diagrams of each process in
图14为本实用新型双面图形芯片正装单颗封装结构实施例5结构示意图。Fig. 14 is a structural schematic diagram of
图15为图14的俯视图。FIG. 15 is a top view of FIG. 14 .
图16(A)~图16(R)为本实用新型双面图形芯片正装单颗封装方法实施例6各工序示意图。16(A) to 16(R) are schematic diagrams of each process in
图17为本实用新型双面图形芯片正装单颗封装结构实施例6结构示意图。Fig. 17 is a structural schematic diagram of
图18为图17的俯视图。FIG. 18 is a top view of FIG. 17 .
图19(A)~图19(R)为本实用新型双面图形芯片正装单颗封装方法实施例7各工序示意图。19(A) to 19(R) are schematic diagrams of each process in
图20为本实用新型双面图形芯片正装单颗封装结构实施例7结构示意图。Fig. 20 is a structural schematic diagram of
图21为图20的俯视图。FIG. 21 is a top view of FIG. 20 .
图22(A)~图22(R)为本实用新型双面图形芯片正装单颗封装方法实施例8各工序示意图。22(A) to 22(R) are schematic diagrams of each process in
图23为本实用新型双面图形芯片正装单颗封装结构实施例8结构示意图。Fig. 23 is a structural schematic diagram of
图24为图23的俯视图。FIG. 24 is a top view of FIG. 23 .
图25(A)~图25(R)为本实用新型双面图形芯片正装单颗封装方法实施例9各工序示意图。25(A) to 25(R) are schematic diagrams of each process in Embodiment 9 of the double-sided graphics chip front-mounting single-chip packaging method of the present invention.
图26为本实用新型双面图形芯片正装单颗封装结构实施例9结构示意图。Fig. 26 is a structural schematic diagram of Embodiment 9 of the double-sided graphics chip front-mounted single-chip package structure of the present invention.
图27为图26的俯视图。FIG. 27 is a top view of FIG. 26 .
图28(A)~图28(R)为本实用新型双面图形芯片正装单颗封装方法实施例10各工序示意图。28(A) to 28(R) are schematic diagrams of each process in
图29为本实用新型双面图形芯片正装单颗封装结构实施例10结构示意图。FIG. 29 is a structural schematic diagram of
图30为图29的俯视图。FIG. 30 is a top view of FIG. 29 .
图31(A)~图31(R)为本实用新型双面图形芯片正装单颗封装方法实施例11各工序示意图。31(A) to 31(R) are schematic diagrams of each process in
图32为本实用新型双面图形芯片正装单颗封装结构实施例11结构示意图。Fig. 32 is a structural schematic diagram of
图33为图32的俯视图。FIG. 33 is a top view of FIG. 32 .
图34(A)~图34(R)为本实用新型双面图形芯片正装单颗封装方法实施例12各工序示意图。34(A) to 34(R) are schematic diagrams of each process in
图35为本实用新型双面图形芯片正装单颗封装结构实施例12结构示意图。Fig. 35 is a structural schematic diagram of
图36为图35的俯视图。FIG. 36 is a top view of FIG. 35 .
图37(A)~图37(R)为本实用新型双面图形芯片正装单颗封装方法实施例13各工序示意图。37(A) to 37(R) are schematic diagrams of each process in
图38为本实用新型双面图形芯片正装单颗封装结构实施例13结构示意图。Fig. 38 is a structural schematic diagram of
图39为图38的俯视图。FIG. 39 is a top view of FIG. 38 .
图40(A)~图40(R)为本实用新型双面图形芯片正装单颗封装方法实施例14各工序示意图。40(A) to 40(R) are schematic diagrams of each process in
图41为本实用新型双面图形芯片正装单颗封装结构实施例14结构示意图。Fig. 41 is a structural schematic diagram of
图42为图41的俯视图。FIG. 42 is a top view of FIG. 41 .
图43为以往采用金属基板的正面进行化学蚀刻及表面电镀层作业图。Fig. 43 is a working diagram of chemical etching and surface electroplating on the front side of a metal substrate in the past.
图44为以往形成的掉脚图。Fig. 44 is a diagram of a footfall formed in the past.
图45为以往的封装结构一示意图。FIG. 45 is a schematic diagram of a conventional package structure.
图46为45的俯视图。FIG. 46 is a top view of 45 .
图47为以往的封装结构二示意图。FIG. 47 is a schematic diagram of a second conventional package structure.
图48为47的俯视图。Figure 48 is a top view of 47.
图中附图标记:Reference signs in the figure:
基岛1、引脚2、无填料的塑封料(环氧树脂)3、第一金属层4、第二金属层5、导电或不导电粘结物质6、芯片7、金属线8、有填料塑封料(环氧树脂)9、柱子10、金属基板11、光阻胶膜12、光阻胶膜13、光阻胶膜14、光阻胶膜15、连筋16、光阻胶膜17、光阻胶膜18;第三基岛1.1、第三基岛1.2、第三基岛1.3、第四基岛1.4。
(五)具体实施方式(5) Specific implementation methods
本实用新型双面图形芯片正装单颗封装结构如下:The double-sided graphics chip of the utility model is installed with a single package structure as follows:
实施例1:单基岛单圈引脚Example 1: Single base island single turn pin
参见图2和图3,图2为本实用新型双面图形芯片正装单颗封装结构实施例1结构示意图。图3为图2的俯视图。由图2和图3可以看出,本实用新型双面图形芯片正装单颗封装结构,包括基岛1、引脚2、无填料的塑封料(环氧树脂)3、导电或不导电粘结物质6、芯片7、金属线8和有填料塑封料(环氧树脂)9,所述引脚2正面延伸到基岛1旁边,在所述基岛1和引脚2的正面设置有第一金属层4,在所述基岛1和引脚2的背面设置有第二金属层5,在所述基岛1正面第一金属层4上通过导电或不导电粘结物质6设置有芯片7,芯片7正面与引脚2正面第一金属层4之间用金属线8连接,在所述基岛1和引脚2的上部以及芯片7和金属线8外包封有填料塑封料(环氧树脂)9,该有填料塑封料(环氧树脂)9将引脚2正面局部单元进行包覆,在所述基岛1和引脚2外围的区域、引脚2与基岛1之间的区域以及引脚2与引脚2之间的区域嵌置有无填料的塑封料(环氧树脂)3,所述无填料的塑封料(环氧树脂)3将基岛1和引脚2下部外围、引脚2下部与基岛1下部以及引脚2下部与引脚2下部连接成一体,且使所述基岛和引脚背面尺寸小于基岛和引脚正面尺寸,形成上大下小的基岛和引脚结构,在所述引脚2背面设置有柱子10,柱子10根部埋入所述无填料的塑封料(环氧树脂)3内。Referring to Fig. 2 and Fig. 3, Fig. 2 is a structural schematic diagram of
其封装方法如下:Its packaging method is as follows:
步骤一、取金属基板
参见图1(A),取一片厚度合适的金属基板11。金属基板的材质可以依据芯片的功能与特性进行变换,例如:铜、铝、铁、铜合金或镍铁合金等。Referring to FIG. 1(A), take a
步骤二、金属基板正面及背面被覆光阻胶膜
参见图1(B),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜12和13,以保护后续的电镀金属层工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(B), the front and back sides of the metal substrate are covered with
步骤三、金属基板正面的光阻胶膜进行需要电镀金属层区域的曝光/显影以及开窗Step 3: Expose/develop the photoresist film on the front of the metal substrate and open the window where the metal layer needs to be plated
参见图1(C),利用曝光显影设备将步骤二完成光阻胶膜被覆作业的金属基板正面进行曝光显影去除部分光阻胶膜,以露出金属基板正面后续需要进行电镀金属层的区域。Referring to FIG. 1(C), use exposure and development equipment to expose and develop the front of the metal substrate that has completed the photoresist film coating operation in
步骤四、金属基板正面已开窗的区域进行金属层电镀被覆
参见图1(D),对步骤三中金属基板正面已开窗的区域进行第一金属层4电镀被覆,该第一金属层4置于所述基岛1与引脚2的正面。Referring to FIG. 1(D), the
步骤五、金属基板正面及背面进行光阻胶膜去膜
参见图1(E),将金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除。Referring to FIG. 1(E), remove the remaining photoresist film on the front side of the metal substrate and the photoresist film on the back side of the metal substrate.
步骤六、金属基板正面及背面被覆光阻胶膜
参见图1(F),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜14和15,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(F), the front and back sides of the metal substrate are coated with
步骤七、金属基板的光阻胶膜进行需要双面蚀刻区域的曝光/显影以及开窗
参见图1(G),利用曝光显影设备将步骤六完成光阻胶膜被覆作业的金属基板正面及背面进行曝光显影去除部分光阻胶膜,以露出局部金属基板以备后续需要进行的金属基板双面蚀刻作业。Referring to Figure 1(G), use the exposure and development equipment to expose and develop the front and back of the metal substrate that has completed the photoresist film coating operation in
步骤八、金属基板进行双面蚀刻作业
参见图1(H),完成步骤七的曝光/显影以及开窗作业后,即在金属基板的正面及背面进行各图形的蚀刻作业,蚀刻出基岛1和引脚2的正面和背面,同时将引脚正面尽可能的延伸到基岛旁边,且使所述基岛1和引脚2的背面尺寸小于基岛1和引脚2的正面尺寸,形成上大下小的基岛1和引脚2结构;以及在引脚2背面形成柱子10,并在基岛1与引脚2之间和引脚2与引脚2之间留有连筋16。Referring to Fig. 1(H), after completing the exposure/development and window opening operation in
步骤九、金属基板正面及背面进行光阻胶膜去膜Step 9. Remove the photoresist film on the front and back of the metal substrate
参见图1(I),将金属基板正面和背面余下的光阻胶膜全部揭除,制成引线框,Referring to Figure 1 (I), the remaining photoresist films on the front and back of the metal substrate are all removed to form a lead frame.
步骤十、装片Step ten, loading film
参见图1(J),在基岛1正面第一金属层4上通过导电或不导电粘结物质6进行芯片7的植入。Referring to FIG. 1(J), the
步骤十一、打金属线
参见图1(K),将已完成芯片植入作业的半成品进行芯片正面与引脚正面第一金属层之间打金属线8作业。Referring to FIG. 1(K), the semi-finished product that has completed the chip implantation operation is subjected to the
步骤十二、包封有填料塑封料(环氧树脂)
参见图1(L),将已打线完成的半成品正面进行局部单元包封有填料塑封料(环氧树脂)9作业,使引脚2正面局部单元区域露出有填料塑封料(环氧树脂)9,并进行塑封料包封后的固化作业,使基岛和引脚的上部以及芯片和金属线外均被有填料塑封料(环氧树脂)包封。Referring to Figure 1(L), the front side of the semi-finished product that has been wired is partially encapsulated with filler molding compound (epoxy resin) 9, so that the partial unit area on the front side of
步骤十三、被覆光阻胶膜Step 13: Coating photoresist film
参见图1(M),利用被覆设备在将已完成包封有填料塑封料(环氧树脂)作业的半成品的正面及背面分别被覆可进行曝光显影的光阻胶膜17和18,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(M), the front and back of the semi-finished product that has been encapsulated with filler molding compound (epoxy resin) are coated with photoresist films 17 and 18 that can be exposed and developed by coating equipment to protect subsequent etching process work. The photoresist film can be a dry photoresist thin film or a wet photoresist film.
步骤十四、已完成包封有填料塑封料(环氧树脂)作业的半成品的背面进行需要蚀刻区域的曝光/显影以及开窗
参见图1(N),利用曝光显影设备将步骤十三完成光阻胶膜被覆作业的已完成包封有填料塑封料(环氧树脂)作业的半成品背面进行曝光显影去除部分光阻胶膜,以露出步骤八金属基板双面蚀刻作业后留有的连筋16以及在引脚2背面形成的柱子10,以备后续需要进行柱子根部和连筋蚀刻作业。Referring to Fig. 1(N), use the exposure and development equipment to expose and develop the back of the semi-finished product that has completed the coating operation of the photoresist film in
步骤十五、第二次蚀刻作业Step fifteen, the second etching operation
参见图1(O),完成步骤十四的曝光/显影以及开窗作业后,即在完成包封有填料塑封料(环氧树脂)作业的半成品背面进行各图形的蚀刻作业,将步骤八金属基板双面蚀刻作业后留有的连筋16全部蚀刻掉,在这个过程中所述柱子10的根部也会同时的蚀刻掉相对的厚度,使柱子根部不露出包封后的封装结构背面,避免产生断路。Referring to Figure 1(O), after completing the exposure/development and window opening operations in step fourteen, the etching operation of each pattern is performed on the back of the semi-finished product that is encapsulated with filler molding compound (epoxy resin), and the step eight metal The ribs 16 left after the double-sided etching of the substrate are all etched away. During this process, the roots of the
步骤十六、半成品正面及背面进行光阻胶膜去膜Step 16. Remove the photoresist film on the front and back of the semi-finished product
参见图1(P),将完成步骤十五蚀刻作业的半成品背面余下的光阻胶膜以及半成品正面的光阻胶膜全部揭除。Referring to FIG. 1(P), the remaining photoresist film on the back of the semi-finished product and the photoresist film on the front of the semi-finished product after the etching operation in
步骤十七、包封无填料的塑封料(环氧树脂)Step seventeen, encapsulating the plastic compound (epoxy resin) without filler
参见图1(Q),将已完成步骤十六所述去膜作业的半成品背面进行包封无填料的塑封料(环氧树脂)作业,并进行塑封料包封后的固化作业,使基岛1和引脚2外围的区域、引脚2与基岛1之间的区域以及引脚2与引脚2之间的区域均嵌置无填料的塑封料(环氧树脂)3,该无填料的塑封料Referring to Figure 1(Q), the back of the semi-finished product that has completed the film removal operation described in step 16 is encapsulated with a filler-free molding compound (epoxy resin), and the curing operation is performed after the molding compound is encapsulated, so that the
(环氧树脂)3将基岛1和引脚2下部外围、引脚2下部与基岛1下部以及引脚2下部与引脚2下部连接成一体,且使所述柱子10根部埋入该无填料的塑封料(环氧树脂)3内。(Epoxy resin) 3 connect the
特别说明:但也因为多了所述柱子10在封装体内,反而在封装体内的结构更为强壮了(好比混泥土中增加了钢筋又有强度又有韧性)Special note: but also because there are
步骤十八、基岛和引脚的背面以及引脚的正面进行金属层电镀被覆Step 18, the base island and the back of the pin and the front of the pin are electroplated with a metal layer
参见图1(R),对已完成步骤十七包封无填料塑封料作业的所述基岛和引脚的背面以及步骤十二所述露出有填料塑封料(环氧树脂)的引脚2正面局部单元区域分别进行第二金属层5和第一金属层4的电镀被覆作业,而电镀的材料可以是锡、镍金、镍钯金....等金属材质。Referring to Fig. 1 (R), the base island and the back side of the pins that have completed step seventeen encapsulating no-filler molding compound and the
步骤十九、切割成品Step nineteen, cut the finished product
参见图2和图3,将已完成步骤十八第二金属层电镀被覆的半成品进行切割作业,使原本以列阵式集合体方式连在一起的芯片一颗颗独立开来,制得双面图形芯片正装单颗封装结构成品。Referring to Figure 2 and Figure 3, the semi-finished product that has completed the electroplating and coating of the second metal layer in step 18 is cut, so that the chips that were originally connected together in the form of an array assembly are separated one by one to obtain a double-sided The graphics chip is being installed in a single package structure.
实施例2:下沉基岛露出型单圈引脚Embodiment 2: sunken base island exposed type single-turn pin
参见图4~6,图4(A)~图4(R)为本实用新型双面图形芯片正装单颗封装方法实施例2各工序示意图。图5为本实用新型双面图形芯片正装单颗封装结构实施例2结构示意图。图6为图5的俯视图。由图4、图5和图6可以看出,实施例2与实施例1的不同之处仅在于:所述基岛1为下沉型基岛,即基岛1正面中央区域下沉。Referring to Figures 4 to 6, Figures 4(A) to 4(R) are schematic diagrams of each process in
实施例3:埋入型基岛单圈引脚Embodiment 3: Embedded base island single-turn pin
参见图7~9,图7(A)~图7(R)为本实用新型双面图形芯片正装单颗封装方法实施例3各工序示意图。图8为本实用新型双面图形芯片正装单颗封装结构实施例3结构示意图。图9为图8的俯视图。由图7、图8和图9可以看出,实施例3与实施例1的不同之处仅在于:所述基岛1为埋入型基岛,即基岛1背面埋入所述无填料的塑封料(环氧树脂)3内。Referring to Figures 7 to 9, Figures 7(A) to 7(R) are schematic diagrams of each process in
实施例4:多凸点基岛露出型单圈引脚Embodiment 4: Multi-bump base island exposed single-turn pin
参见图10~12,图10(A)~图10(R)为本实用新型双面图形芯片正装单颗封装方法实施例4各工序示意图。图11为本实用新型双面图形芯片正装单颗封装结构实施例4结构示意图。图12为图11的俯视图。由图10、图11和图12可以看出,实施例4与实施例1的不同之处仅在于:所述基岛1为多凸点基岛,即基岛1表面设置有多个凸点。Referring to Figures 10-12, Figures 10(A)-10(R) are schematic diagrams of each process in
实施例5:多个基岛露出型单圈引脚Embodiment 5: Multiple base island exposed single-turn pins
参见图13~15,图13(A)~图13(R)为本实用新型双面图形芯片正装单颗封装方法实施例5各工序示意图。图14为本实用新型双面图形芯片正装单颗封装结构实施例5结构示意图。图15为图14的俯视图。由图13~15可以看出,实施例5与实施例1的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 13-15, Figures 13(A)-13(R) are schematic diagrams of each process in
实施例6:多个下沉基岛露出型单圈引脚Embodiment 6: Multiple sunken base island exposed single-turn pins
参见图16~18,图16(A)~图16(R)为本实用新型双面图形芯片正装单颗封装方法实施例6各工序示意图。图17为本实用新型双面图形芯片正装单颗封装结构实施例6结构示意图。图18为图17的俯视图。由图16~18可以看出,实施例6与实施例2的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 16-18, Figures 16(A)-16(R) are schematic diagrams of each process in
实施例7:多个埋入型基岛单圈引脚Example 7: Multiple Buried Base Island Single Turn Pins
参见图19~21,图19(A)~图19(R)为本实用新型双面图形芯片正装单颗封装方法实施例7各工序示意图。图20为本实用新型双面图形芯片正装单颗封装结构实施例7结构示意图。图21为图20的俯视图。由图19~21可以看出,实施例7与实施例3的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 19-21, Figures 19(A)-19(R) are schematic diagrams of each process in
实施例8:多个多凸点基岛露出型单圈引脚Embodiment 8: Multiple multi-bump base island exposed single-turn pins
参见图22~24,图22(A)~图22(R)为本实用新型双面图形芯片正装单颗封装方法实施例8各工序示意图。图23为本实用新型双面图形芯片正装单颗封装结构实施例8结构示意图。图24为图23的俯视图。由图22~24可以看出,实施例8与实施例4的不同之处在于:所述基岛1有多个,引脚2有单圈。Referring to Figures 22 to 24, Figures 22(A) to 22(R) are schematic diagrams of each process in
实施例9:基岛露出型及下沉基岛露出型单圈引脚Embodiment 9: base island exposed type and sunken base island exposed type single-turn pin
参见图25~27,图25(A)~图25(R)为本实用新型双面图形芯片正装单颗封装方法实施例9各工序示意图。图26为本实用新型双面图形芯片正装单颗封装结构实施例9结构示意图。图27为图26的俯视图。由图25~27可以看出,实施例9与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第二基岛1.2,所述第二基岛1.2正面中央区域下沉,在所述第一基岛1.1和引脚2的正面设置第一金属层4,在所述第一基岛1.1、第二基岛1.2和引脚2的背面设置第二金属层5,在第二基岛1.2正面中央下沉区域和第一基岛1.1正面通过导电或不导电粘结物质6设置芯片7,芯片7正面与引脚2正面第一金属层4之间以及芯片7与芯片7之间均用金属线8连接,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第一基岛1.1与第二基岛1.2之间的区域、第二基岛1.2与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第一基岛1.1下部、第一基岛1.1与第二基岛1.2下部、第二基岛1.2与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2有单圈。Referring to Figures 25-27, Figures 25(A)-25(R) are schematic diagrams of each process in Embodiment 9 of the front-mounting single-chip packaging method for double-sided graphics chips of the present invention. Fig. 26 is a structural schematic diagram of Embodiment 9 of the double-sided graphics chip front-mounted single-chip package structure of the present invention. FIG. 27 is a top view of FIG. 26 . It can be seen from Figures 25 to 27 that the difference between Embodiment 9 and
实施例10:基岛露出型及埋入型基岛单圈引脚Embodiment 10: base island exposed type and embedded type base island single-turn pin
参见图28~30,图28(A)~图28(R)为本实用新型双面图形芯片正装单颗封装方法实施例10各工序示意图。图29为本实用新型双面图形芯片正装单颗封装结构实施例10结构示意图。图30为图29的俯视图。由图28~30可以看出,实施例10与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第三基岛1.3,在所述第一基岛1.1第三基岛1.3和引脚2的正面设置第一金属层4,在所述第一基岛1.1和引脚2的背面设置第二金属层5,芯片7正面与引脚2正面第一金属层4之间以及芯片7与芯片7之间均用金属线8连接,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第三基岛1.3背面、第三基岛1.3与第一基岛1.1之间的区域、第三基岛1.3与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第一基岛1.1下部、第三基岛1.3背面、第三基岛1.3背面与第一基岛1.1下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有单圈。Referring to Figures 28-30, Figures 28(A)-28(R) are schematic diagrams of each process in
实施例11:基岛露出型及多凸点基岛露出型单圈引脚Embodiment 11: base island exposed type and multi-bump base island exposed type single-turn pin
参见图31~33,图31(A)~图31(R)为本实用新型双面图形芯片正装单颗封装方法实施例11各工序示意图。图32为本实用新型双面图形芯片正装单颗封装结构实施例11结构示意图。图33为图32的俯视图。由图31~33可以看出,实施例11与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第一基岛1.1,另一组为第四基岛1.4,所述第四基岛1.4正面设置成多凸点状结构,在所述引脚2外围的区域、引脚2与第一基岛1.1之间的区域、第一基岛1.1与第四基岛1.4之间的区域、第四基岛1.4与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料的塑封料(环氧树脂)3将引脚下部外围、引脚2与第一基岛1.1下部、第一基岛1.1与第四基岛1.4下部、第四基岛1.4与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有单圈。Referring to Figures 31-33, Figures 31(A)-31(R) are schematic diagrams of each process in
实施例12:下沉基岛露出型及埋入型基岛露出型单圈引脚Embodiment 12: Sunken base island exposed type and buried base island exposed type single-turn pin
参见图34~36,图34(A)~图34(R)为本实用新型双面图形芯片正装单颗封装方法实施例12各工序示意图。图35为本实用新型双面图形芯片正装单颗封装结构实施例12结构示意图。图36为图35的俯视图。由图34~36可以看出,实施例12与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第二基岛1.2,另一组为第三基岛1.3,所述第二基岛1.2正面中央区域下沉,在第二基岛1.2正面中央下沉区域和第三基岛1.3正面通过导电或不导电粘结物质6设置芯片7,在所述引脚2外围的区域、引脚2与第二基岛1.2之间的区域、第三基岛1.3背面、第二基岛背面1.2与第二基岛1.2之间的区域、第三基岛1.3背面与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第二基岛1.2下部、第三基岛1.3、第三基岛1.3与第二基岛1.2下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 34 to 36, Figures 34(A) to 34(R) are schematic diagrams of each process in
实施例13:下沉基岛露出型及多凸点基岛露出型单圈引脚Embodiment 13: Sunken base island exposed type and multi-bump base island exposed type single-turn pin
参见图37~39,图37(A)~图37(R)为本实用新型双面图形芯片正装单颗封装方法实施例13各工序示意图。图38为本实用新型双面图形芯片正装单颗封装结构实施例13结构示意图。图39为图38的俯视图。由图37~39可以看出,实施例13与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第二基岛1.2,另一组为第四基岛1.4,所述第二基岛1.2正面中央区域下沉,第四基岛1.4正面设置成多凸点状结构,在所述第四基岛1.4和引脚2的正面设置第一金属层4,在所述第二基岛1.2、第四基岛1.4和引脚2的背面设置第二金属层5,在所述第二基岛1.2正面中央下沉区域和第四基岛1.4正面通过导电或不导电粘结物质6设置芯片7,在所述引脚2外围的区域、引脚2与第二基岛1.2之间的区域、第二基岛1.2与第四基岛1.4之间的区域、第四基岛1.4与引脚2之间的区域以及引脚2与引脚2之间的区域嵌置无填料塑封料3,所述无填料的塑封料(环氧树脂)3将引脚下部外围、引脚2与第二基岛1.2下部、第二基岛1.2与第四基岛1.4下部、第四基岛1.4与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 37-39, Figures 37(A)-37(R) are schematic diagrams of each process in
实施例14:埋入型基岛及多凸点基岛露出型单圈引脚Embodiment 14: Embedded base island and multi-bump base island exposed single-turn pin
参见图40~42,图40(A)~图40(R)为本实用新型双面图形芯片正装单颗封装方法实施例14各工序示意图。图41为本实用新型双面图形芯片正装单颗封装结构实施例14结构示意图。图42为图41的俯视图。由图40~42可以看出,实施例14与实施例1的不同之处在于:所述基岛1有二组也可以是多组基岛,一组为第三基岛1.3,另一组为第四基岛1.4,所述第四基岛1.4正面设置成多凸点状结构,在所述第三基岛1.3、第四基岛1.4和引脚2的正面设置第一金属层4,在所述第四基岛1.4和引脚2的背面设置第二金属层5,在所述引脚2外围的区域、引脚2与第四基岛1.4之间的区域、第三基岛1.3背面、第二基岛1.2与第四基岛1.4之间的区域、第三基岛1.3与引脚2之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料3,所述无填料塑封料3将引脚下部外围、引脚2与第四基岛1.4下部、第三基岛1.3背面、第三基岛1.3背面与第四基岛1.4下部、第三基岛1.3背面与引脚2下部以及引脚2与引脚2下部连接成一体,所述引脚2设置有一圈。Referring to Figures 40-42, Figures 40(A)-40(R) are schematic diagrams of each process in
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