CN202003984U - Single first-plating second-etching packaging structure of flip chip with double-sided graphs - Google Patents
Single first-plating second-etching packaging structure of flip chip with double-sided graphs Download PDFInfo
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- CN202003984U CN202003984U CN 201020517844 CN201020517844U CN202003984U CN 202003984 U CN202003984 U CN 202003984U CN 201020517844 CN201020517844 CN 201020517844 CN 201020517844 U CN201020517844 U CN 201020517844U CN 202003984 U CN202003984 U CN 202003984U
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
本实用新型涉及一种双面图形芯片倒装先镀后刻单颗封装结构,包括引脚(2)、无填料的塑封料(环氧树脂)(3)、锡金属的粘结物质(6)、芯片(7)有填料塑封料(环氧树脂)(9),在所述引脚(2)外围的区域以及引脚(2)与引脚(2)之间的区域嵌置有无填料的塑封料(3),且使所述引脚背面尺寸小于引脚正面尺寸,形成上大下小的引脚结构,引脚(2)正面延伸到后续贴装芯片的下方,在所述引脚(2)的正面设置有第一金属层(4),在所述引脚(2)的背面设置有第二金属层(5),在后续贴装芯片的下方的引脚(2)正面第一金属层(4)上通过锡金属的粘结物质(6)设置有芯片(7),在所述引脚(2)的上部以及芯片(7)外包封有填料塑封料(9),该有填料塑封料(9)将引脚(2)正面局部单元进行包覆。本实用新型芯片封装结构不会再有产生掉脚的问题。
The utility model relates to a double-sided graphic chip flip-chip firstly plated and then engraved with a single package structure, comprising pins (2), plastic sealing material (epoxy resin) without filler (3), tin metal bonding material (6 ), the chip (7) has a filler molding compound (epoxy resin) (9), whether there is embedded in the peripheral area of the pin (2) and the area between the pin (2) and the pin (2) The plastic encapsulant (3) of the filler, and make the size of the back of the pin smaller than the front size of the pin to form a pin structure with a large top and a small bottom. The front of the pin (2) extends to the bottom of the subsequent mounting chip. The front side of the pin (2) is provided with a first metal layer (4), and the back side of the pin (2) is provided with a second metal layer (5), and the pin (2) below the subsequent mounted chip On the first metal layer (4) on the front side, a chip (7) is provided through a bonding substance (6) of tin metal, and a filler molding compound (9) is encapsulated on the upper part of the pin (2) and the chip (7) , the filler plastic compound (9) covers the front part of the pin (2). The chip packaging structure of the utility model does not have the problem of falling feet.
Description
(一)技术领域(1) Technical field
本实用新型涉及一种双面图形芯片倒装先镀后刻单颗封装结构。属于半导体封装技术领域。The utility model relates to a double-sided graphic chip flip-chip firstly plated and then engraved with a single package structure. It belongs to the technical field of semiconductor packaging.
(二)背景技术(2) Background technology
传统的芯片封装结构的制作方式是:采用金属基板的正面进行化学蚀刻及表面电镀层后,即完成引线框的制作(如图7所示)。而引线框的背面则在封装过程中再进行蚀刻。该法存在以下不足:The traditional manufacturing method of the chip packaging structure is: after chemical etching and surface electroplating are performed on the front side of the metal substrate, the production of the lead frame is completed (as shown in FIG. 7 ). The backside of the leadframe is etched during the packaging process. This law has the following shortcomings:
因为塑封前只在金属基板正面进行了半蚀刻工作,而在塑封过程中塑封料只有包裹住引脚半只脚的高度,所以塑封体与引脚的束缚能力就变小了,如果塑封体贴片到PCB板上不是很好时,再进行返工重贴,就容易产生掉脚的问题(如图8所示)。尤其塑封料的种类是采用有填料时候,因为材料在生产过程的环境与后续表面贴装的应力变化关系,会造成金属与塑封料产生垂直型的裂缝,其特性是填料比例越高则越硬越脆越容易产生裂缝。Because only half-etching work is done on the front of the metal substrate before plastic sealing, and the plastic sealing material is only half a foot high to cover the pins during the plastic sealing process, so the binding ability between the plastic package and the pins becomes smaller. If the plastic package is considerate When the chip is not well attached to the PCB board, rework and re-attachment will easily cause the problem of foot drop (as shown in Figure 8). Especially when the type of molding compound is filled, because the relationship between the environment of the material in the production process and the stress change of the subsequent surface mount will cause vertical cracks between the metal and the molding compound, the characteristic is that the higher the filler ratio, the harder it is The more brittle the easier it is to crack.
另外,由于芯片与引脚之间的距离较远,金属线的长度较长,如图9~10所示,金属线成本较高(尤其是昂贵的纯金质的金属线);同样由于金属线的长度较长,使得芯片的信号输出速度较慢(尤其是存储类的产品以及需 要大量数据的计算,更为突出);也同样由于金属线的长度较长,所以在金属线所存在的寄生电阻/寄生电容与寄生电杆对信号的干扰也较高;再由于芯片与引脚之间的距离较远,使得封装的体积与面积较大,材料成本较高,废弃物较多。In addition, due to the long distance between the chip and the pins, the length of the metal wire is relatively long, as shown in Figures 9-10, the cost of the metal wire is relatively high (especially the expensive pure gold metal wire); The length of the wire is longer, which makes the signal output speed of the chip slower (especially for storage products and calculations that require a large amount of data); The interference of parasitic resistance/capacitance and parasitic poles on the signal is also high; and because the distance between the chip and the pin is long, the volume and area of the package are large, the cost of materials is high, and there is more waste.
(三)发明内容(3) Contents of the invention
本实用新型的目的在于克服上述不足,提供一种不会再有产生掉脚的问题的双面图形芯片倒装先镀后刻单颗封装结构。The purpose of the utility model is to overcome the above-mentioned disadvantages and provide a double-sided graphic chip flip-chip flip-chip first plating and then engraving single-chip packaging structure without the problem of pin drop.
本实用新型的目的是这样实现的:一种双面图形芯片倒装先镀后刻单颗封装结构,包括引脚、无填料的塑封料(环氧树脂)、锡金属的粘结物质、芯片有填料塑封料(环氧树脂),在所述引脚外围的区域以及引脚与引脚之间的区域嵌置有无填料的塑封料(环氧树脂),所述无填料的塑封料(环氧树脂)将引脚下部外围以及引脚下部与引脚下部连接成一体,且使所述引脚背面尺寸小于引脚正面尺寸,形成上大下小的引脚结构,所述引脚正面延伸到后续贴装芯片的下方,在所述引脚的正面设置有第一金属层,在所述引脚的背面设置有第二金属层,在所述后续贴装芯片的下方的引脚正面第一金属层上通过锡金属的粘结物质设置有芯片,在所述引脚的上部以及芯片外包封有填料塑封料(环氧树脂),该有填料塑封料(环氧树脂)将引脚正面局部单元进行包覆。The purpose of this utility model is achieved like this: a kind of double-sided graphics chip flip-chip is first plated and then engraved with a single package structure, including pins, plastic packaging materials (epoxy resin) without fillers, bonding substances of tin metal, chip There is a filling molding compound (epoxy resin), and the area around the pin and the area between the pins are embedded with a filling-free molding compound (epoxy resin), and the filling-free molding compound ( Epoxy resin) connects the periphery of the lower part of the pin and the lower part of the pin to the lower part of the pin as a whole, and makes the size of the back of the pin smaller than the size of the front of the pin to form a pin structure with a large top and a small bottom. Extending to the bottom of the subsequent mounted chip, a first metal layer is provided on the front of the pin, a second metal layer is provided on the back of the pin, and the front of the pin below the subsequent mounted chip On the first metal layer, a chip is provided with a bonding substance of tin metal, and a filler molding compound (epoxy resin) is encapsulated on the top of the pin and outside the chip, and the filler molding compound (epoxy resin) wraps the pin Front partial unit cladding.
本实用新型的有益效果是:The beneficial effects of the utility model are:
1、确保不会再有产生掉脚的问题1. Ensure that there will be no more problems with feet falling
由于引线框采用了双面蚀刻的工艺技术,所以可以轻松的规划设计与 制造出上大下小的引脚结构,可以使上下层塑封料紧密的将上大下小的引脚结构一起包裹住,所以塑封体与引脚的束缚能力就变大了,不会再有产生掉脚的问题。Since the lead frame adopts the double-sided etching process technology, it is easy to plan, design and manufacture the pin structure with large upper and lower pins, and the upper and lower pin structures can be tightly wrapped by the upper and lower plastic molding compounds. , so the binding ability between the plastic package and the pins becomes larger, and there will be no more problems of falling feet.
2、由于应用了引线框背面与正面分开蚀刻的技术,所以能够将引线框正面的引脚尽可能的延伸到封装体的中心,促使芯片与引脚位置能够与芯片键合的位置相同,如图6所示,如此电性的传输将可大幅度提升(尤其存储类的产品以及需要大量数据的计算,更为突出)。2. Due to the application of the technology of separately etching the back and front of the lead frame, the pins on the front of the lead frame can be extended to the center of the package as much as possible, so that the position of the chip and the pin can be the same as the position of the chip bonding, such as As shown in Figure 6, such electrical transmission will be greatly improved (especially for storage products and calculations that require a large amount of data).
3、使封装的体积与面积可以大幅度的缩小3. The volume and area of the package can be greatly reduced
因运用了引脚的延伸技术,所以可以容易的制作出高脚数与高密度的脚与脚之间的距离,使得封装的体积与面积可以大幅度的缩小。Due to the use of pin extension technology, it is easy to produce a high number of pins and a high-density pin-to-pin distance, so that the volume and area of the package can be greatly reduced.
4、材料成本和材料用量减少4. Reduced material cost and material consumption
因为将封装后的体积大幅度的缩小,更直接的体现出材料成本大幅度的下降与因为材料用量的减少也大幅度的减少废弃物环保的困扰。Because the volume after packaging is greatly reduced, it more directly reflects the substantial reduction in material costs and the reduction in the amount of materials used also greatly reduces the problem of waste and environmental protection.
5、采用局部单元的单颗封装的优点有:5. The advantages of using a single package of local units are:
1)在不同的应用中可以将塑封体边缘的引脚伸出塑封体。1) In different applications, the pins on the edge of the plastic package can be extended out of the plastic package.
2)塑封体边缘的引脚伸出塑封体外可以清楚的检查出焊接在PCB板上的情况。2) The pins on the edge of the plastic package extend out of the plastic package to clearly check the soldering on the PCB.
3)模块型的面积较大会容易因为多种不同的材料结构所产生收缩率不同的应立变形,而局部单元的单颗封装就可以完全分散多种不同的材料结构所产生收缩率不同的应立变形。3) The large area of the modular type will easily cause the deformation of the different shrinkage rates due to a variety of different material structures, and the single package of the local unit can completely disperse the different shrinkage rates of the different material structures. vertical deformation.
4)单颗封装在进行塑封体切割分离时,因为要切割的厚度只有引脚的 厚度,所以切割的速度可以比模块型的封装结构要来得快很多,且切割用的刀片因为切割的厚度便薄了所以切割刀片的寿命相对的也就变的更长了。4) When a single package is cut and separated from the plastic package, because the thickness to be cut is only the thickness of the pin, the cutting speed can be much faster than that of the modular package structure, and the cutting blade is easy to cut because of the cutting thickness. It is thinner, so the life of the cutting blade is relatively longer.
(四)附图说明(4) Description of drawings
图1(A)~图1(Q)为本实用新型双面图形芯片倒装先镀后刻单颗封装结构实施例1各工序示意图。Fig. 1(A) ~ Fig. 1(Q) are schematic diagrams of each process of embodiment 1 of the double-sided graphics chip flip-chip of the present invention, firstly plated and then engraved with a single package structure.
图2为本实用新型双面图形芯片倒装单颗封装结构实施例1结构示意图。Fig. 2 is a structural schematic diagram of Embodiment 1 of the double-sided graphics chip flip-chip single package structure of the present invention.
图3为图2的俯视图。FIG. 3 is a top view of FIG. 2 .
图4(A)~图4(Q)为本实用新型双面图形芯片倒装先镀后刻单颗封装结构实施例2各工序示意图。Fig. 4(A) ~ Fig. 4(Q) are schematic diagrams of each process of
图5为本实用新型双面图形芯片倒装单颗封装结构实施例2结构示意图。Fig. 5 is a structural schematic diagram of
图6为图5的俯视图。FIG. 6 is a top view of FIG. 5 .
图7为以往采用金属基板的正面进行化学蚀刻及表面电镀层作业图。FIG. 7 is a diagram of conventional chemical etching and surface electroplating on the front side of a metal substrate.
图8为以往形成的掉脚图。Fig. 8 is a diagram of a footfall formed in the past.
图9为以往的封装结构一示意图。FIG. 9 is a schematic diagram of a conventional packaging structure.
图10为图9的俯视图。FIG. 10 is a top view of FIG. 9 .
图中附图标记:Reference signs in the figure:
引脚2、无填料的塑封料(环氧树脂)3、第一金属层4、第二金属层5、锡金属的粘结物质6、芯片7、有填料塑封料(环氧树脂)9、金属基板 10、光阻胶膜11、光阻胶膜12、光阻胶膜13、光阻胶膜14、光阻胶膜15、光阻胶膜16。
(五)具体实施方式(5) Specific implementation methods
本实用新型双面图形芯片倒装先镀后刻单颗封装结构如下:The double-sided graphic chip flip chip of the utility model is first plated and then engraved with a single package structure as follows:
实施例1:单芯片单圈引脚Example 1: Single-chip single-turn pin
参见图2和图3,图2为本实用新型双面图形芯片倒装单颗封装结构实施例1结构示意图。图3为图2的俯视图。由图2和图3可以看出,本实用新型双面图形芯片倒装单颗封装结构,包括引脚2、无填料的塑封料(环氧树脂)3、锡金属的粘结物质6、芯片7有填料塑封料(环氧树脂)9,所述引脚2正面尽可能的延伸到后续贴装芯片的下方,在所述引脚2的正面设置有第一金属层4,在所述引脚2的背面设置有第二金属层5,在所述后续贴装芯片的下方的引脚2正面第一金属层4上通过锡金属的粘结物质6设置有芯片7,在所述引脚2的上部以及芯片7外包封有填料塑封料(环氧树脂)9,该有填料塑封料(环氧树脂)9将引脚2正面局部单元进行包覆,在所述引脚2外围的区域以及引脚2与引脚2之间的区域嵌置有无填料的塑封料(环氧树脂)3,所述无填料的塑封料(环氧树脂)3将引脚下部外围以及引脚2下部与引脚2下部连接成一体,且使所述引脚背面尺寸小于引脚正面尺寸,形成上大下小的引脚结构。Referring to Fig. 2 and Fig. 3, Fig. 2 is a structural schematic diagram of Embodiment 1 of the double-sided graphics chip flip chip packaging structure of the present invention. FIG. 3 is a top view of FIG. 2 . As can be seen from Fig. 2 and Fig. 3, the utility model double-sided graphics chip flip-chip single package structure includes
其封装结构如下:Its packaging structure is as follows:
步骤一、取金属基板Step 1. Take the metal substrate
参见图1(A),取一片厚度合适的金属基板10。金属基板的材质可以依Referring to FIG. 1(A), take a
据芯片的功能与特性进行变换,例如:铜、铝、铁、铜合金或镍铁合金等。Transform according to the function and characteristics of the chip, such as: copper, aluminum, iron, copper alloy or nickel-iron alloy, etc.
步骤二、金属基板正面及背面被覆光阻胶膜
参见图1(B),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜11和12,以保护后续的电镀金属层工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(B), the front and back sides of the metal substrate are coated with
步骤三、金属基板正面的光阻胶膜进行需要电镀金属层区域的曝光/显影以及开窗Step 3: Expose/develop the photoresist film on the front of the metal substrate and open the window where the metal layer needs to be plated
参见图1(C),利用曝光显影设备将步骤二完成光阻胶膜被覆作业的金属基板正面进行曝光显影去除部分光阻胶膜,以露出金属基板正面后续需要进行电镀金属层的区域。Referring to FIG. 1(C), use exposure and development equipment to expose and develop the front of the metal substrate that has completed the photoresist film coating operation in
步骤四、金属基板正面已开窗的区域进行金属层电镀被覆
参见图1(D),对步骤三中金属基板正面已开窗的区域进行第一金属层4电镀被覆,该第一金属层4置于所述引脚2的正面。Referring to FIG. 1(D), the
步骤五、金属基板正面及背面进行光阻胶膜去膜
参见图1(E),将金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除。Referring to FIG. 1(E), remove the remaining photoresist film on the front side of the metal substrate and the photoresist film on the back side of the metal substrate.
步骤六、金属基板正面及背面被覆光阻胶膜
参见图1(F),利用被覆设备在金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜13和14,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式光阻胶膜。Referring to FIG. 1(F), the front and back sides of the metal substrate are coated with
步骤七、金属基板背面的光阻胶膜进行需要蚀刻区域的曝光/显影以及开窗
参见图1(G),利用曝光显影设备将步骤六完成光阻胶膜被覆作业的金属基板背面进行曝光显影去除部分光阻胶膜,以露出局部金属基板以备后续需要进行的金属基板背面蚀刻作业。Referring to Figure 1(G), use the exposure and development equipment to expose and develop the back of the metal substrate that has completed the photoresist film coating operation in
步骤八、金属基板进行背面蚀刻作业Step 8. Etching the back of the metal substrate
参见图1(H),完成步骤七的曝光/显影以及开窗作业后,即在金属基板的背面进行各图形的蚀刻作业,蚀刻出引脚2的背面,同时将引脚正面尽可能的延伸到后续贴装芯片的下方。Referring to Figure 1(H), after completing the exposure/development and window opening operations in
步骤九、金属基板正面及背面进行光阻胶膜去膜
参见图1(I),将金属基板正面和背面余下的光阻胶膜全部揭除。Referring to FIG. 1(I), the remaining photoresist films on the front and back of the metal substrate are all removed.
步骤十、包封无填料的塑封料(环氧树脂)
参见图1(J),将已完成步骤九所述去膜作业的金属基板背面进行包封无填料的塑封料(环氧树脂)作业,并进行塑封料包封后的固化作业,使引脚2外围的区域以及引脚2与引脚2之间的区域均嵌置无填料的塑封料(环氧树脂)3,该无填料的塑封料(环氧树脂)3将引脚下部外围以及引脚2下部与引脚2下部连接成一体。Referring to Figure 1(J), the back of the metal substrate that has completed the film removal operation described in
步骤十一、被覆光阻胶膜
参见图1(K),利用被覆设备在将已完成包封无填料塑封料作业的金属基板的正面及背面分别被覆可进行曝光显影的光阻胶膜15和16,以保护后续的蚀刻工艺作业。而此光阻胶膜可以是干式光阻薄胶膜也可以是湿式 光阻胶膜。Referring to Fig. 1(K), use the coating equipment to coat the front and back of the metal substrate that has completed the encapsulation of the filler-free molding compound with photoresist films 15 and 16 that can be exposed and developed, so as to protect the subsequent etching process. . And this photoresist film can be dry type photoresist film also can be wet type photoresist film.
步骤十二、已完成包封无填料塑封料作业的金属基板的正面进行需要蚀刻区域的曝光/显影以及开窗Step 12: Expose/develop the area to be etched and open the window on the front side of the metal substrate that has completed the encapsulation of the non-filler molding compound
参见图1(L),利用曝光显影设备将步骤十一完成光阻胶膜被覆作业的已完成包封无填料塑封料作业的金属基板正面进行曝光显影去除部分光阻胶膜,以备后续需要进行金属基板正面蚀刻作业。Referring to Figure 1(L), use the exposure and development equipment to expose and develop the front side of the metal substrate that has completed the encapsulation and non-filler molding compound operation in
步骤十三、金属基板正面蚀刻作业
参见图1(M),完成步骤十二的曝光/显影以及开窗作业后,即在完成包封无填料塑封料作业的金属基板正面进行各图形的蚀刻作业,蚀刻出引脚2的正面,且使所述引脚2的背面尺寸小于引脚2的正面尺寸,形成上大下小的引脚2结构。Referring to FIG. 1(M), after completing the exposure/development and window opening operations in
步骤十四、金属基板正面及背面进行光阻胶膜去膜
参见图1(N),将完成步骤十三蚀刻作业的金属基板正面余下的光阻胶膜以及金属基板背面的光阻胶膜全部揭除,制成引线框。Referring to FIG. 1(N), the remaining photoresist film on the front side of the metal substrate and the photoresist film on the back side of the metal substrate after
步骤十五、装片Step fifteen, loading film
参见图1(O),在所述后续贴装芯片的下方的引脚2正面第一金属层4上通过锡金属的粘结物质6进行芯片7的植入。Referring to FIG. 1(O),
步骤十六、包封有填料塑封料(环氧树脂)Step 16. Encapsulate with filler molding compound (epoxy resin)
参见图1(P),将已打线完成的半成品正面进行局部单元包封有填料塑封料(环氧树脂)9作业,使引脚2正面局部单元区域露出有填料塑封料(环氧树脂)9,并进行塑封料包封后的固化作业,使引脚的上部以及芯片 外均被有填料塑封料(环氧树脂)包封。Referring to Figure 1(P), the front of the semi-finished product that has been wired is partially encapsulated with filler molding compound (epoxy resin) 9, so that the partial unit area on the front of
步骤十七、引脚的背面以及正面进行金属层电镀被覆Step seventeen, the back and front of the pins are electroplated with metal layer
参见图1(Q),对已完成步骤十七包封有填料塑封料(环氧树脂)作业的所述引脚的背面以及步骤十六所述露出有填料塑封料(环氧树脂)9的引脚2正面区域分别进行第二金属层5和第一金属层4电镀被覆作业,而电镀的材料可以是锡、镍金、镍钯金....等金属材质。Referring to Fig. 1 (Q), the back side of the pin that has been encapsulated with filler molding compound (epoxy resin) in step 17 and exposed with filler molding compound (epoxy resin) 9 described in step 16 The
步骤十八、切割成品Step 18. Cutting the finished product
参见图2和图3,将已完成步骤十八第二金属层电镀被覆的半成品进行切割作业,使原本以列阵式集合体方式连在一起的芯片一颗颗独立开来,制得双面图形芯片倒装单颗封装结构成品。Referring to Figure 2 and Figure 3, the semi-finished product that has completed the electroplating and coating of the second metal layer in step 18 is cut, so that the chips that were originally connected together in the form of an array assembly are separated one by one to obtain a double-sided Graphic chip flip-chip package structure finished product.
实施例2:多芯片单圈引脚Example 2: Multi-chip single-turn pin
图4(A)~图4(Q)为本实用新型双面图形芯片倒装先镀后刻单颗封装结构实施例2各工序示意图。图5为本实用新型双面图形芯片倒装单颗封装结构实施例2结构示意图。图6为图5的俯视图。由图4、图5和图6可以看出,实施例2与实施例1的不同之处仅在于:所述芯片7设置有多颗。Fig. 4(A) ~ Fig. 4(Q) are schematic diagrams of each process of
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CN110690191B (en) * | 2019-11-05 | 2025-03-25 | 长电科技(滁州)有限公司 | Double-sided chip packaging structure and packaging method |
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