[go: up one dir, main page]

CN201838578U - Single packaging structure for mounting of plating-to-carving chip with double-sided graphics - Google Patents

Single packaging structure for mounting of plating-to-carving chip with double-sided graphics Download PDF

Info

Publication number
CN201838578U
CN201838578U CN2010205178667U CN201020517866U CN201838578U CN 201838578 U CN201838578 U CN 201838578U CN 2010205178667 U CN2010205178667 U CN 2010205178667U CN 201020517866 U CN201020517866 U CN 201020517866U CN 201838578 U CN201838578 U CN 201838578U
Authority
CN
China
Prior art keywords
pin
base island
island
area
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2010205178667U
Other languages
Chinese (zh)
Inventor
王新潮
梁志忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN2010205178667U priority Critical patent/CN201838578U/en
Application granted granted Critical
Publication of CN201838578U publication Critical patent/CN201838578U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Packaging Of Annular Or Rod-Shaped Articles, Wearing Apparel, Cassettes, Or The Like (AREA)

Abstract

本实用新型涉及一种双面图形芯片正装先镀后刻单颗封装结构，包括基岛(1)、引脚(2)、无填料的塑封料(环氧树脂)(3)、导电或不导电粘结物质(6)、芯片(7)、金属线(8)和有填料塑封料(环氧树脂)(9)，所述引脚(2)正面延伸到基岛(1)旁边，在所述基岛(1)和引脚(2)的上部以及芯片(7)和金属线(8)外包封有填料塑封料(9)，在所述基岛(1)和引脚(2)外围的区域、引脚(2)与基岛(1)之间的区域以及引脚(2)与引脚(2)之间的区域嵌置有无填料的塑封料(3)，且使所述基岛和引脚背面尺寸小于基岛和引脚正面尺寸，形成上大下小的基岛和引脚结构，其特征在于：所述有填料塑封料(9)将引脚(2)正面局部单元进行包覆。本实用新型封装结构不会再有产生掉脚的问题和能使金属线的长度缩短。

The utility model relates to a double-sided graphics chip packaging structure first plated and then engraved with a single chip, comprising a base island (1), pins (2), plastic sealing material (epoxy resin) (3) Conductive bonding substance (6), chip (7), metal wire (8) and filler molding compound (epoxy resin) (9), the front side of the pin (2) extends to the side of the base island (1), in The upper part of the base island (1) and the pins (2), as well as the chip (7) and the metal wire (8) are encapsulated with a filler plastic compound (9), and the base island (1) and the pins (2) The peripheral area, the area between the pin (2) and the base island (1) and the area between the pin (2) and the pin (2) are embedded with a filler-free molding compound (3), and all the The size of the base island and the back of the pin is smaller than the size of the base island and the front of the pin, forming a base island and pin structure with a large top and a small bottom, and it is characterized in that: the filler plastic compound (9) seals the front of the pin (2) Local units are clad. The package structure of the utility model can no longer cause the problem of falling feet and can shorten the length of the metal wire.

Description

Two-sided graphic chips formal dress plates earlier and afterwards carves single encapsulating structure
(1) technical field
The utility model relates to first plating of a kind of two-sided graphic chips formal dress and afterwards carves single encapsulating structure.Belong to the semiconductor packaging field.
(2) background technology
The production method of traditional chip-packaging structure is: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in figure 43) of lead frame.Etching is then carried out at the back side of lead frame again in encapsulation process.This method has the following disadvantages:
Because only carried out the work that etches partially before the plastic packaging in the metal substrate front, and plastic packaging material only wraps the height of half pin of pin in the plastic packaging process, so the constraint ability of plastic-sealed body and pin has just diminished, when if the plastic-sealed body paster is not fine to pcb board, do over again again and heavily paste, with regard to the problem (as shown in figure 44) that is easy to generate pin.Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
In addition, because the distance between chip and the pin is far away, the length of metal wire is longer, shown in Figure 45～46, and metal wire cost higher (the especially metal wire of Ang Gui proof gold matter); Same because the length of metal wire is longer, make that the signal output speed of chip is slow (especially the product of storage class and the calculating that needs mass data are more outstanding); Too because the length of metal wire is longer, so also higher to the interference of signal in existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole; Because the distance between chip and the pin is far away, make that the volume and the area of encapsulation are bigger again, material cost is higher, and discarded object is more.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, provides a kind of and does not have the problem that produces pin again and can make first plating of two-sided graphic chips formal dress of the contraction in length of metal wire afterwards carve single encapsulating structure.
The purpose of this utility model is achieved in that and comprises Ji Dao, pin, packless plastic packaging material (epoxy resin), conduction or non-conductive bonding material, chip, metal wire and filler plastic packaging material (epoxy resin) arranged, described pin front extends to next door, basic island, front at described Ji Dao and pin is provided with the first metal layer, be provided with second metal level at the back side of described Ji Dao and pin, on the first metal layer of front, described basic island, be provided with chip by conduction or non-conductive bonding material, be connected with metal wire between chip front side and the pin front the first metal layer, outside the top of described Ji Dao and pin and chip and metal wire, be encapsulated with filler plastic packaging material (epoxy resin), zone in described Ji Dao and pin periphery, zone and the zone between pin and the pin between pin and the basic island are equipped with packless plastic packaging material (epoxy resin), described packless plastic packaging material (epoxy resin) is with Ji Dao and periphery, pin bottom, pin bottom and Ji Dao bottom and pin bottom and pin bottom link into an integrated entity, and make described Ji Dao and pin back side size less than Ji Dao and the positive size of pin, form up big and down small Ji Dao and pin configuration, it is characterized in that: described have filler plastic packaging material (epoxy resin) that the positive local unit of pin is coated.
The beneficial effects of the utility model are:
1, guarantees not have again the problem that produces pin
Because lead frame has adopted two-sided etched technology, so planning and designing easily with produce up big and down small pin configuration, the levels plastic packaging material is wrapped up big and down small pin configuration closely together, so the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again.
2, guarantee the contraction in length of metal wire
1) separates etched technology owing to used the lead frame back side with the front, so the pin in lead frame front can be extended to as much as possible the follow-up next door, zone that needs cartridge chip, impel chip and pin distance significantly to shorten, as Fig. 2～Fig. 3, so the length of metal wire has also shortened, and the cost of metal wire also can significantly reduce (the especially metal wire of Ang Gui proof gold matter);
2) also because the contraction in length of metal wire makes also significantly speedup (the especially product of storage class and the calculating that needs mass data of signal output speed of chip, more outstanding), because the length of metal wire has shortened, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are to the also significantly reduction of interference of signal.
3, the volume of encapsulation and area can significantly be dwindled
Because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin.
4, material cost and material usage reduce
Because volume after being encapsulated is significantly dwindled, more direct embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
5, the advantage of single encapsulation of the local Single of employing unit has:
1) in different application, the pin at plastic-sealed body edge can be stretched out plastic-sealed body.
2) pin at plastic-sealed body edge stretches out outside the plastic-sealed body and can clearly check out situation about being welded on the pcb board.
3) area of modular type is easy because multiple different shrinkage that material structure produces is different should stand distortion than conference, and single encapsulation of local unit just can disperse fully multiple different shrinkage that material structure produces different should stand distortion.
4) single is encapsulated in when carrying out the plastic-sealed body cutting and separating, because the thickness that cuts has only the thickness of pin, so the speed of cutting can be come much soon than the encapsulating structure of modular type, so and incisory blade because the thickness of cutting just approached life-span of cutting blade relative also just become longer.
(4) description of drawings
Fig. 1 (A)～Fig. 1 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 1 each operation schematic diagram.
Fig. 2 is single encapsulating structure embodiment 1 structural representation of the two-sided graphic chips formal dress of the utility model.
Fig. 3 is the vertical view of Fig. 2.
Fig. 4 (A)～Fig. 4 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 2 each operation schematic diagram.
Fig. 5 is single encapsulating structure embodiment 2 structural representations of the two-sided graphic chips formal dress of the utility model.
Fig. 6 is the vertical view of Fig. 5.
Fig. 7 (A)～Fig. 7 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 3 each operation schematic diagram.
Fig. 8 is single encapsulating structure embodiment 3 structural representations of the two-sided graphic chips formal dress of the utility model.
Fig. 9 is the vertical view of Fig. 8.
Figure 10 (A)～Figure 10 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 4 each operation schematic diagram.
Figure 11 is single encapsulating structure embodiment 4 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 12 is the vertical view of Figure 11.
Figure 13 (A)～Figure 13 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 5 each operation schematic diagram.
Figure 14 is single encapsulating structure embodiment 5 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 15 is the vertical view of Figure 14.
Figure 16 (A)～Figure 16 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 6 each operation schematic diagram.
Figure 17 is single encapsulating structure embodiment 6 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 18 is the vertical view of Figure 17.
Figure 19 (A)～Figure 19 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 7 each operation schematic diagram.
Figure 20 is single encapsulating structure embodiment 7 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 21 is the vertical view of Figure 20.
Figure 22 (A)～Figure 22 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 8 each operation schematic diagram.
Figure 23 is single encapsulating structure embodiment 8 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 24 is the vertical view of Figure 23.
Figure 25 (A)～Figure 25 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 5 each operation schematic diagram.
Figure 26 is single encapsulating structure embodiment 5 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 27 is the vertical view of Figure 26.
Figure 28 (A)～Figure 28 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 6 each operation schematic diagram.
Figure 29 is single encapsulating structure embodiment 6 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 30 is the vertical view of Figure 29.
Figure 31 (A)～Figure 31 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 11 each operation schematic diagram.
Figure 32 is single encapsulating structure embodiment 11 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 33 is the vertical view of Figure 32.
Figure 34 (A)～Figure 34 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 12 each operation schematic diagram.
Figure 35 is single encapsulating structure embodiment 12 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 36 is the vertical view of Figure 35.
Figure 37 (A)～Figure 37 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 13 each operation schematic diagram.
Figure 38 is single encapsulating structure embodiment 13 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 39 is the vertical view of Figure 38.
Figure 40 (A)～Figure 40 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 14 each operation schematic diagram.
Figure 41 is single encapsulating structure embodiment 14 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 42 is the vertical view of Figure 41.
Figure 43 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Figure 44 pin figure for what formed in the past.
Figure 45 is an encapsulating structure schematic diagram in the past.
Figure 46 is 45 vertical view.
Reference numeral among the figure:
The base island 1, pin 2, packless plastic packaging material (epoxy resin) 3, the first metal layer 4, second metal level 5, conduction or non-conductive bonding material 6, chip 7, metal wire 8, filler plastic packaging material (epoxy resin) 9, metal substrate 10, photoresistance glued membrane 11, photoresistance glued membrane 12, photoresistance glued membrane 13, photoresistance glued membrane 14, photoresistance glued membrane 15, photoresistance glued membrane 16 are arranged;
The 1.3, the 4th basic island 1.4, the 1.2, the 3rd basic island, the 1.1, the 3rd basic island, the 3rd basic island.
(5) embodiment
The two-sided graphic chips formal dress of the utility model plates earlier that afterwards to carve single encapsulating structure as follows:
Embodiment 1: single basic island individual pen pin
Referring to Fig. 2 and Fig. 3, Fig. 2 is single encapsulating structure embodiment 1 structural representation of the two-sided graphic chips formal dress of the utility model.Fig. 3 is the vertical view of Fig. 2.By Fig. 2 and Fig. 3 as can be seen, single encapsulating structure of the two-sided graphic chips formal dress of the utility model, comprise basic island 1, pin 2, packless plastic packaging material (epoxy resin) 3, conduction or non-conductive bonding material 6, chip 7, metal wire 8 and filler plastic packaging material (epoxy resin) 9 is arranged, described pin 2 fronts extend to 1 next door, basic island as much as possible, front at described basic island 1 and pin 2 is provided with the first metal layer 4, the back side at described basic island 1 and pin 2 is provided with second metal level 5, on the 1 front the first metal layer 4 of described basic island, be provided with chip 7 by conduction or non-conductive bonding material 6, chip 7 positive with pin 2 front the first metal layers 4 between be connected with metal wire 8, outside the top of described basic island 1 and pin 2 and chip 7 and metal wire 8, be encapsulated with filler plastic packaging material (epoxy resin) 9, this has filler plastic packaging material (epoxy resin) 9 that pin 2 positive local unit are coated, zone in described basic island 1 and pin 2 peripheries, zone between zone between pin 2 and the basic island 1 and pin 2 and the pin 2 is equipped with packless plastic packaging material (epoxy resin) 3, described packless plastic packaging material (epoxy resin) 3 is with basic island 1 and periphery, pin bottom, pin 2 bottoms and 1 bottom, basic island and pin 2 bottoms and pin 2 bottoms link into an integrated entity, and make described Ji Dao and pin back side size less than Ji Dao and the positive size of pin, form up big and down small Ji Dao and pin configuration.
Its encapsulating structure is as follows:
Step 1, get metal substrate
Referring to Fig. 1 (A), get the suitable metal substrate of a slice thickness 10.The material of metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper, aluminium, iron, copper alloy or dilval etc.
Step 2, metal substrate front and back side lining photoresistance glued membrane
Referring to Fig. 1 (B), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 11 and 12 of exposure imaging, to protect follow-up electroplated metal layer process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane in step 3, metal substrate front needs the exposure of plated metal layer region/develop and windows
Referring to Fig. 1 (C), the metal substrate front that utilizes exposure imaging equipment that step 2 is finished photoresistance glued membrane lining operation is carried out exposure imaging and is removed part photoresistance glued membrane, carries out the zone of electroplated metal layer to expose the positive follow-up needs of metal substrate.
The zone of having windowed in step 4, metal substrate front is carried out metal level and is electroplated lining
Referring to Fig. 1 (D), the first metal layer 4 plating linings are carried out in the zone of having windowed in metal substrate front in the step 3, this first metal layer 4 places the front of described basic island 1 and pin 2.
Photoresistance glued membrane striping is carried out at step 5, metal substrate front and the back side
Referring to Fig. 1 (E), the positive remaining photoresistance glued membrane of metal substrate and the photoresistance glued membrane at the metal substrate back side are all removed.
Step 6, metal substrate front and back side lining photoresistance glued membrane
Referring to Fig. 1 (F), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 13 and 14 of exposure imaging, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane at step 7, the metal substrate back side needs the exposure of etching area/develop and windows
Referring to Fig. 1 (G), exposure imaging removal part photoresistance glued membrane is carried out at the metal substrate back side that utilizes exposure imaging equipment that step 6 is finished photoresistance glued membrane lining operation, to expose the metal substrate back etched operation that the localized metallic substrate carries out in order to follow-up needs.
Step 8, metal substrate carry out the back etched operation
Referring to Fig. 1 (H), after the exposure/development and windowing task of completing steps seven, promptly carry out the etching operation of each figure at the back side of metal substrate, etch the back side of basic island 1 and pin 2, simultaneously the pin front is extended to as much as possible next door, basic island.
Photoresistance glued membrane striping is carried out at step 9, metal substrate front and the back side
Referring to Fig. 1 (I), the photoresistance glued membrane of metal substrate front and back remainder is all removed.
Step 10, seal packless plastic packaging material (epoxy resin)
Referring to Fig. 1 (J), packless plastic packaging material (epoxy resin) operation is sealed at the metal substrate back side of completing steps nine described striping operations, and carry out curing operation after plastic packaging material is sealed, make zone between zone, pin 2 and the basic island 1 of basic island 1 and pin 2 peripheries and the zone between pin 2 and the pin 2 all set packless plastic packaging material (epoxy resin) 3, this packless plastic packaging material (epoxy resin) 3 links into an integrated entity basic island 1 and periphery, pin bottom, pin 2 bottoms and 1 bottom, basic island and pin 2 bottoms and pin 2 bottoms.
Step 11, lining photoresistance glued membrane
Referring to Fig. 1 (K), utilize by coating equipment in the front that will finish the metal substrate of sealing the operation of no filler plastic packaging material and the back side be covered respectively and can carry out the photoresistance glued membrane 15 and 16 of exposure imaging, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
Step 12, the front of having finished the metal substrate of sealing the operation of no filler plastic packaging material need the exposure of etching area/develop and window
Referring to Fig. 1 (L), exposure imaging removal part photoresistance glued membrane is carried out in the metal substrate front of sealing the operation of no filler plastic packaging material of finishing that utilizes exposure imaging equipment that step 11 is finished photoresistance glued membrane lining operation, carries out the operation of metal substrate front-side etch in order to follow-up needs.
Step 13, the operation of metal substrate front-side etch
Referring to Fig. 1 (M), after the exposure/development and windowing task of completing steps 12, promptly finish the etching operation that each figure is carried out in the metal substrate front of sealing the operation of no filler plastic packaging material, etch the front of basic island 1 and pin 2, and make the positive size of the back side size of described basic island 1 and pin 2, form up big and down small basic island 1 and pin 2 structures less than basic island 1 and pin 2.
Photoresistance glued membrane striping is carried out at step 14, metal substrate front and the back side
Referring to Fig. 1 (N), the positive remaining photoresistance glued membrane of the metal substrate of completing steps 13 etching operations and the photoresistance glued membrane at the metal substrate back side are all removed, make lead frame.
Step 15, load
Referring to Fig. 1 (O), on the 1 front the first metal layer 4 of basic island, carry out the implantation of chip 7 by conduction or non-conductive bonding material 6.
Step 10 six, break metal wire
Referring to Fig. 1 (P), the semi-finished product of finishing chip implantation operation are carried out playing metal wire 8 operations between chip front side and the pin front the first metal layer.
Step 10 seven, be encapsulated with filler plastic packaging material (epoxy resin)
Referring to Fig. 1 (Q), the semi-finished product front that routing is finished is carried out local unit and is encapsulated with filler plastic packaging material (epoxy resin) 9 operations, pin 2 positive local unit zones are exposed filler plastic packaging material (epoxy resin) 9 is arranged, and carry out curing operation after plastic packaging material is sealed, make the top of Ji Dao and pin and chip and metal wire all be had filler plastic packaging material (epoxy resin) to seal outward.
The back side of step 10 eight, Ji Dao and pin and the front of pin are carried out metal level and are electroplated lining referring to Fig. 1 (R), completing steps 17 is encapsulated with the back side of the described Ji Dao of filler plastic packaging material (epoxy resin) operation and pin and step 10 seven are described exposes that second metal level 5 is carried out in the pin 2 positive local unit zones that filler plastic packaging material (epoxy resin) 9 is arranged respectively and the first metal layer 4 is electroplated the lining operations, and the material of electroplating can be tin, nickel gold, NiPdAu .... wait metal material.
Step 10 nine, cutting finished product
Referring to Fig. 2 and Fig. 3, the semi-finished product of ten eight the second metal levels of completing steps being electroplated lining carry out cutting operation, make originally more than of chips that connect together in array formula aggregate mode independent, make single encapsulating structure finished product of two-sided graphic chips formal dress.
Embodiment 2: base island exposed type individual pen pin sinks
Referring to Fig. 4～6, Fig. 4 (A)～Fig. 4 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 2 each operation schematic diagram.Fig. 5 is single encapsulating structure embodiment 2 structural representations of the two-sided graphic chips formal dress of the utility model.Fig. 6 is the vertical view of Fig. 5.By Fig. 4, Fig. 5 and Fig. 6 as can be seen, embodiment 2 only is with the difference of embodiment 1: described basic island 1 is sinking type Ji Dao, and promptly basic island 1 front middle section sinks.
Embodiment 3: baried type base island individual pen pin
Referring to Fig. 7～9, Fig. 7 (A)～Fig. 7 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 3 each operation schematic diagram.Fig. 8 is single encapsulating structure embodiment 3 structural representations of the two-sided graphic chips formal dress of the utility model.Fig. 9 is the vertical view of Fig. 8.By Fig. 7, Fig. 8 and Fig. 9 as can be seen, embodiment 3 only is with the difference of embodiment 1: described basic island 1 is baried type Ji Dao, and 1 back side, promptly basic island is imbedded in the described packless plastic packaging material (epoxy resin) 3.
Embodiment 4: the base island exposed type individual pen of multi-convex point pin
Referring to Figure 10～12, Figure 10 (A)～Figure 10 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 4 each operation schematic diagram.Figure 11 is single encapsulating structure embodiment 4 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 12 is the vertical view of Figure 11.By Figure 10, Figure 11 and Figure 12 as can be seen, embodiment 4 only is with the difference of embodiment 1: described basic island 1 is multi-convex point Ji Dao, and 1 surface, promptly basic island is provided with a plurality of salient points.
Embodiment 5: a plurality of base island exposed type individual pen pins
Referring to Figure 13～15, Figure 13 (A)～Figure 13 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 5 each operation schematic diagram.Figure 14 is single encapsulating structure embodiment 5 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 15 is the vertical view of Figure 14.By Figure 13～15 as can be seen, embodiment 5 is with the difference of embodiment 1: described basic island 1 has a plurality of, and pin 2 has individual pen.
Embodiment 6: the base island exposed type individual pen of a plurality of sinkings pin
Referring to Figure 16～18, Figure 16 (A)～Figure 16 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 6 each operation schematic diagram.Figure 17 is single encapsulating structure embodiment 6 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 18 is the vertical view of Figure 17.By Figure 16～18 as can be seen, embodiment 6 is with the difference of embodiment 2: described basic island 1 has a plurality of, and pin 2 has individual pen.
Embodiment 7: a plurality of baried type bases island individual pen pin
Referring to Figure 19～21, Figure 19 (A)～Figure 19 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 7 each operation schematic diagram.Figure 20 is single encapsulating structure embodiment 7 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 21 is the vertical view of Figure 20.By Figure 19～21 as can be seen, embodiment 7 is with the difference of embodiment 3: described basic island 1 has a plurality of, and pin 2 has individual pen.
Embodiment 8: the base island exposed type individual pen of a plurality of multi-convex points pin
Referring to Figure 22～24, Figure 22 (A)～Figure 22 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 8 each operation schematic diagram.Figure 23 is single encapsulating structure embodiment 8 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 24 is the vertical view of Figure 23.By Figure 22～24 as can be seen, embodiment 8 is with the difference of embodiment 4: described basic island 1 has a plurality of, and pin 2 has individual pen.
Embodiment 9: the base island exposed type and the base island exposed type individual pen pin that sinks
Referring to Figure 25～27, Figure 25 (A)～Figure 25 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 9 each operation schematic diagram.Figure 26 is single encapsulating structure embodiment 9 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 27 is the vertical view of Figure 26.By Figure 25～27 as can be seen, embodiment 9 is with the difference of embodiment 1: described basic island 1 has two groups also can be many group Ji Dao, one group is the first basic island 1.1, another group is the second basic island 1.2, the described second basic island 1.2 front middle sections sink, front at the described first basic island 1.1 and pin 2 is provided with the first metal layer 4, on the described first basic island 1.1, the back side of the second basic island 1.2 and pin 2 is provided with second metal level 5, by conduction or non-conductive bonding material 6 chip 7 is set in the second basic island 1.2 positive central sunken regions and 1.1 fronts, the first basic island, chip 7 positive with pin 2 front the first metal layers 4 between and all be connected between chip 7 and the chip 7 with metal wire 8, zone in described pin 2 peripheries, zone between the pin 2 and the first basic island 1.1, zone between the first basic island 1.1 and the second basic island 1.2, no filler plastic packaging material 3 is set in zone between the second basic island 1.2 and the pin 2 and the zone between pin 2 and the pin 2, described no filler plastic packaging material 3 is with periphery, pin bottom, pin 2 and 1.1 bottoms, the first basic island, the first basic island 1.1 and 1.2 bottoms, the second basic island, the second basic island 1.2 links into an integrated entity with pin 2 bottoms with pin 2 bottoms and pin 2, and described pin 2 has individual pen.
Embodiment 10: base island exposed type and baried type base island individual pen pin
Referring to Figure 28～30, Figure 28 (A)～Figure 28 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 10 each operation schematic diagram.Figure 29 is single encapsulating structure embodiment 10 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 30 is the vertical view of Figure 29.By Figure 28～30 as can be seen, embodiment 10 is with the difference of embodiment 1: described basic island 1 has two groups also can be many group Ji Dao, one group is the first basic island 1.1, another group is the 3rd basic island 1.3, front at described first the 3rd basic island 1.3, basic island 1.1 and pin 2 is provided with the first metal layer 4, the back side at the described first basic island 1.1 and pin 2 is provided with second metal level 5, chip 7 positive with pin 2 front the first metal layers 4 between and all be connected between chip 7 and the chip 7 with metal wire 8, zone in described pin 2 peripheries, zone between the pin 2 and the first basic island 1.1,1.3 back sides, the 3rd basic island, zone between the 3rd basic island 1.3 and the first basic island 1.1, no filler plastic packaging material 3 is set in zone and the zone between pin and the pin between the 3rd basic island 1.3 and the pin 2, described no filler plastic packaging material 3 is with periphery, pin bottom, pin 2 and 1.1 bottoms, the first basic island, 1.3 back sides, the 3rd basic island, the 3rd 1.3 back sides, basic island and 1.1 bottoms, the first basic island, the 3rd 1.3 back sides, basic island and pin 2 bottoms and pin 2 link into an integrated entity with pin 2 bottoms, and described pin 2 is provided with individual pen.
Embodiment 11: the base island exposed type individual pen of base island exposed type and multi-convex point pin
Referring to Figure 31～33, Figure 31 (A)～Figure 31 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 11 each operation schematic diagram.Figure 32 is single encapsulating structure embodiment 11 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 33 is the vertical view of Figure 32.By Figure 31～33 as can be seen, embodiment 11 is with the difference of embodiment 1: described basic island 1 has two groups also can be many group Ji Dao, one group is the first basic island 1.1, another group is the 4th basic island 1.4, multi-convex point shape structure is arranged in 1.4 fronts, the described the 4th basic island, zone in described pin 2 peripheries, zone between the pin 2 and the first basic island 1.1, zone between the first basic island 1.1 and the 4th basic island 1.4, no filler plastic packaging material 3 is set in zone between the 4th basic island 1.4 and the pin 2 and the zone between pin 2 and the pin 2, described packless plastic packaging material (epoxy resin) 3 is with periphery, pin bottom, pin 2 and 1.1 bottoms, the first basic island, the first basic island 1.1 and 1.4 bottoms, the 4th basic island, the 4th basic island 1.4 links into an integrated entity with pin 2 bottoms with pin 2 bottoms and pin 2, and described pin 2 is provided with individual pen.
Embodiment 12: the base island exposed type individual pen of base island exposed type and baried type pin sinks
Referring to Figure 34～36, Figure 34 (A)～Figure 34 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 12 each operation schematic diagram.Figure 35 is single encapsulating structure embodiment 12 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 36 is the vertical view of Figure 35.By Figure 34～36 as can be seen, embodiment 12 is with the difference of embodiment 1: described basic island 1 has two groups also can be many group Ji Dao, one group is the second basic island 1.2, another group is the 3rd basic island 1.3, the described second basic island 1.2 front middle sections sink, by conduction or non-conductive bonding material 6 chip 7 is set in the second basic island 1.2 positive central sunken regions and 1.3 fronts, the 3rd basic island, zone in described pin 2 peripheries, zone between the pin 2 and the second basic island 1.2,1.3 back sides, the 3rd basic island, zone between the second Ji Dao back side 1.2 and the second basic island 1.2, no filler plastic packaging material 3 is set in zone and the zone between pin and the pin between the 3rd 1.3 back sides, basic island and the pin 2, described no filler plastic packaging material 3 is with periphery, pin bottom, pin 2 and 1.2 bottoms, the second basic island, the 3rd basic island 1.3, the 3rd basic island 1.3 and 1.2 bottoms, the second basic island, the 3rd 1.3 back sides, basic island and pin 2 bottoms and pin 2 link into an integrated entity with pin 2 bottoms, and described pin 2 is provided with a circle.
Embodiment 13: the base island exposed type individual pen of base island exposed type and multi-convex point pin sinks
Referring to Figure 37～39, Figure 37 (A)～Figure 37 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 13 each operation schematic diagram.Figure 38 is single encapsulating structure embodiment 13 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 39 is the vertical view of Figure 38.By Figure 37～39 as can be seen, embodiment 13 is with the difference of embodiment 1: described basic island 1 has two groups also can be many group Ji Dao, one group is the second basic island 1.2, another group is the 4th basic island 1.4, the described second basic island 1.2 front middle sections sink, multi-convex point shape structure is arranged in 1.4 fronts, the 4th basic island, front at the described the 4th basic island 1.4 and pin 2 is provided with the first metal layer 4, on the described second basic island 1.2, the back side of the 4th basic island 1.4 and pin 2 is provided with second metal level 5, by conduction or non-conductive bonding material 6 chip 7 is set in the described second basic island 1.2 positive central sunken regions and 1.4 fronts, the 4th basic island, zone in described pin 2 peripheries, zone between the pin 2 and the second basic island 1.2, zone between the second basic island 1.2 and the 4th basic island 1.4, no filler plastic packaging material 3 is set in zone between the 4th basic island 1.4 and the pin 2 and the zone between pin 2 and the pin 2, described packless plastic packaging material (epoxy resin) 3 is with periphery, pin bottom, pin 2 and 1.2 bottoms, the second basic island, the second basic island 1.2 and 1.4 bottoms, the 4th basic island, the 4th basic island 1.4 links into an integrated entity with pin 2 bottoms with pin 2 bottoms and pin 2, and described pin 2 is provided with a circle.
Embodiment 14: the base island exposed type individual pen of baried type Ji Dao and multi-convex point pin
Referring to Figure 40～42, Figure 40 (A)～Figure 40 (R) is that first plating of the two-sided graphic chips formal dress of the utility model afterwards carved single encapsulating structure embodiment 14 each operation schematic diagram.41 is single encapsulating structure embodiment 14 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 42 is 41 vertical view.By Figure 40～42 as can be seen, embodiment 14 is with the difference of embodiment 1: described basic island 1 has two groups also can be many group Ji Dao, one group is the 3rd basic island 1.3, another group is the 4th basic island 1.4, multi-convex point shape structure is arranged in 1.4 fronts, the described the 4th basic island, on the described the 3rd basic island 1.3, the front of the 4th basic island 1.4 and pin 2 is provided with the first metal layer 4, the back side at the described the 4th basic island 1.4 and pin 2 is provided with second metal level 5, zone in described pin 2 peripheries, zone between pin 2 and the 4th basic island 1.4,1.3 back sides, the 3rd basic island, zone between the second basic island 1.2 and the 4th basic island 1.4, no filler plastic packaging material 3 is set in zone and the zone between pin and the pin between the 3rd basic island 1.3 and the pin 2, described no filler plastic packaging material 3 is with periphery, pin bottom, pin 2 and 1.4 bottoms, the 4th basic island, 1.3 back sides, the 3rd basic island, the 3rd 1.3 back sides, basic island and 1.4 bottoms, the 4th basic island, the 3rd 1.3 back sides, basic island and pin 2 bottoms and pin 2 link into an integrated entity with pin 2 bottoms, and described pin 2 is provided with a circle.

Claims (12)

1.一种双面图形芯片正装先镀后刻单颗封装结构，包括基岛(1)、引脚(2)、无填料的塑封料(3)、导电或不导电粘结物质(6)、芯片(7)、金属线(8)和有填料塑封料(9)，所述引脚(2)正面延伸到基岛(1)旁边，在所述基岛(1)和引脚(2)的正面设置有第一金属层(4)，在所述基岛(1)和引脚(2)的背面设置有第二金属层(5)，在所述基岛(1)正面第一金属层(4)上通过导电或不导电粘结物质(6)设置有芯片(7)，芯片(7)正面与引脚(2)正面第一金属层(4)之间用金属线(8)连接，在所述基岛(1)和引脚(2)的上部以及芯片(7)和金属线(8)外包封有填料塑封料(9)，在所述基岛(1)和引脚(2)外围的区域、引脚(2)与基岛(1)之间的区域以及引脚(2)与引脚(2)之间的区域嵌置有无填料的塑封料(3)，所述无填料的塑封料(3)将基岛(1)和引脚下部外围、引脚(2)下部与基岛(1)下部以及引脚(2)下部与引脚(2)下部连接成一体，且使所述基岛和引脚背面尺寸小于基岛和引脚正面尺寸，形成上大下小的基岛和引脚结构，其特征在于：所述有填料塑封料(9)将引脚(2)正面局部单元进行包覆。1. A double-sided graphic chip front-mounted first plated and then engraved single package structure, including base island (1), pins (2), plastic packaging compound without filler (3), conductive or non-conductive adhesive material (6) , a chip (7), a metal wire (8) and a filler molding compound (9), the front side of the pin (2) extends to the side of the base island (1), and the base island (1) and the pin (2) ) is provided with a first metal layer (4), on the back of the base island (1) and pins (2) is provided with a second metal layer (5), on the front of the base island (1) the first A chip (7) is arranged on the metal layer (4) through a conductive or non-conductive bonding substance (6), and a metal wire (8) is used between the front of the chip (7) and the first metal layer (4) on the front of the pin (2). ) connection, the upper part of the base island (1) and pins (2) and the chip (7) and metal wire (8) are encapsulated with filler plastic compound (9), and the base island (1) and lead The area around the foot (2), the area between the pin (2) and the base island (1), and the area between the pin (2) and the pin (2) are embedded with plastic encapsulant (3) without filler , the filler-free molding compound (3) connects the periphery of the base island (1) and the lower part of the pin, the lower part of the pin (2) and the lower part of the base island (1) and the lower part of the pin (2) and the lower part of the pin (2) connected into one body, and make the size of the base island and the back of the pin smaller than the size of the base island and the front of the pin, forming a base island and pin structure with a large top and a small bottom, and it is characterized in that: the plastic sealing compound with filler (9) Cover the front part of the pin (2) with a unit. 2.根据权利要求1所述的一种双面图形芯片正装先镀后刻单颗封装结构，其特征在于基岛(1)背面露出所述无填料的塑封料(3)。2. A double-sided graphic chip front-mounting structure according to claim 1, wherein the packaging structure of a single chip is engraved after plating first, and is characterized in that the plastic sealing compound (3) without filler is exposed on the back of the base island (1). 3.根据权利要求1所述的一种双面图形芯片正装先镀后刻单颗封装结构，其特征在于基岛(1)正面中央区域下沉。3. A double-sided graphic chip package structure according to claim 1, characterized in that the central area of the front surface of the base island (1) is sunken. 4.根据权利要求1所述的一种双面图形芯片正装先镀后刻单颗封装结构，其特征在于基岛（1）背面埋入所述无填料的塑封料（3）内。 4. A double-sided graphics chip package structure with front-mounted plating first and then engraved with a single chip according to claim 1, characterized in that the back of the base island (1) is embedded in the plastic packaging compound (3) without filler. the 5.根据权利要求1所述的一种双面图形芯片正装先镀后刻单颗封装结构，其特征在于所述基岛(1)正面设置成多凸点状结构。5. A double-sided graphics chip package structure according to claim 1, characterized in that the front surface of the base island (1) is arranged in a multi-bump structure. 6.根据权利要求2～5其中之一所述的一种双面图形芯片正装先镀后刻单颗封装结构，其特征在于所述基岛(1)有多个，引脚(2)有单圈。6. According to one of claims 2 to 5, a double-sided graphics chip is mounted first and then engraved with a single package structure, which is characterized in that there are multiple base islands (1), and the pins (2) have lap. 7.根据权利要求1所述的一种双面图形芯片正装先镀后刻单颗封装结构，其特征在于所述基岛(1)有二组，一组为第一基岛(1.1)，另一组为第二基岛(1.2)，所述第二基岛(1.2)正面中央区域下沉，在所述第一基岛(1.1)和引脚(2)的正面设置有第一金属层(4)，在所述第一基岛(1.1)、第二基岛(1.2)和引脚(2)的背面设置有第二金属层(5)，在第二基岛(1.2)正面中央下沉区域和第一基岛(1.1)正面通过导电或不导电粘结物质(6)设置有芯片(7)，芯片(7)正面与引脚(2)正面第一金属层(4)之间以及芯片(7)与芯片(7)之间均用金属线(8)连接，在所述引脚(2)外围的区域、引脚(2)与第一基岛(1.1)之间的区域、第一基岛(1.1)与第二基岛(1.2)之间的区域、第二基岛(1.2)与引脚(2)之间的区域以及引脚(2)与引脚(2)之间的区域嵌置无填料塑封料(3)，所述无填料塑封料(3)将引脚下部外围、引脚(2)与第一基岛(1.1)下部、第一基岛(1.1)与第二基岛(1.2)下部、第二基岛(1.2)与引脚(2)下部以及引脚(2)与引脚(2)下部连接成一体，所述引脚(2)设置有单圈。7. A kind of double-sided graphics chip according to claim 1 is mounted and plated first and then engraved with a single package structure, characterized in that the base island (1) has two groups, one group is the first base island (1.1), The other group is the second base island (1.2), the central area of the front of the second base island (1.2) sinks, and the first metal is provided on the front of the first base island (1.1) and the pin (2). Layer (4), a second metal layer (5) is arranged on the back of the first base island (1.1), the second base island (1.2) and the pin (2), and on the front of the second base island (1.2) The central sinking area and the front of the first base island (1.1) are provided with a chip (7) through a conductive or non-conductive bonding substance (6), and the front of the chip (7) is connected to the first metal layer (4) on the front of the pin (2). between the chips (7) and the chips (7) are all connected by metal wires (8), in the peripheral area of the pins (2), between the pins (2) and the first base island (1.1) area, the area between the first base island (1.1) and the second base island (1.2), the area between the second base island (1.2) and the pin (2), and the pin (2) and the pin ( The area between 2) is embedded with filler-free molding compound (3), and the filler-free molding compound (3) connects the lower periphery of the pin, the pin (2) and the lower part of the first base island (1.1), the first base island (1.1) is integrated with the bottom of the second base island (1.2), the bottom of the second base island (1.2) and the pin (2) and the bottom of the pin (2) and the pin (2), and the pin (2) ) is set with a single turn. 8.根据权利要求1所述的一种双面图形芯片正装先镀后刻单颗封装结构，其特征在于所述基岛(1)有二组，一组为第一基岛(1.1)，另一组为第三基岛(1.3)，在所述第一基岛(1.1)第三基岛(1.3)和引脚(2)的正面设置有第一金属层(4)，在所述第一基岛(1.1)和引脚(2)的背面设置有第二金属层(5)，在 基岛(1)正面通过导电或不导电粘结物质(6)设置有芯片(7)，芯片(7)正面与引脚(2)正面第一金属层(4)之间以及芯片(7)与芯片(7)之间均用金属线(8)连接，在所述基岛(1)和引脚(2)的上部以及芯片(7)和金属线(8)外包封有填料塑封料(9)，在所述引脚(2)外围的区域、引脚(2)与第一基岛(1.1)之间的区域、第三基岛(1.3)背面、第二基岛(1.2)与第一基岛(1.1)之间的区域、第三基岛(1.3)与引脚(2)之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料(3)，所述无填料塑封料(3)将引脚下部外围、引脚(2)与第一基岛(1.1)下部、第三基岛(1.3)背面、第三基岛(1.3)背面与第一基岛(1.1)下部、第三基岛(1.3)背面与引脚(2)下部以及引脚(2)与引脚(2)下部连接成一体，所述引脚(2)设置有单圈。8. A kind of double-sided graphic chip according to claim 1 is mounted and plated first and then engraved with a single package structure, characterized in that the base island (1) has two groups, one group is the first base island (1.1), The other group is the third base island (1.3), the first metal layer (4) is arranged on the front of the first base island (1.1), the third base island (1.3) and the pin (2), and the A second metal layer (5) is provided on the back of the first base island (1.1) and the pin (2), and a chip (7) is provided on the front of the base island (1) through a conductive or non-conductive adhesive substance (6), The front of the chip (7) is connected with the first metal layer (4) of the front of the pin (2) and between the chip (7) and the chip (7) with a metal wire (8). and the upper part of the pin (2), as well as the chip (7) and the metal wire (8) are encapsulated with filler plastic compound (9), in the peripheral area of the pin (2), the pin (2) and the first base The area between the island (1.1), the back of the third base island (1.3), the area between the second base island (1.2) and the first base island (1.1), the third base island (1.3) and the pin (2 ) and the area between pins and pins are embedded with filler-free molding compound (3), and the filler-free molding compound (3) connects the lower periphery of the pin, the pin (2) and the first base island (1.1) bottom, third base island (1.3) back, third base island (1.3) back and first base island (1.1) bottom, third base island (1.3) back and pin (2) bottom and pin (2) is integrally connected with the lower part of the pin (2), and the pin (2) is provided with a single turn. 9.根据权利要求1所述的一种双面图形芯片正装先镀后刻单颗封装结构，其特征在于所述基岛(1)有二组，一组为第一基岛(1.1)，另一组为第四基岛(1.4)，所述第四基岛(1.4)正面设置成多凸点状结构，在所述引脚(2)外围的区域、引脚(2)与第一基岛(1.1)之间的区域、第一基岛(1.1)与第四基岛(1.4)之间的区域、第四基岛(1.4)与引脚(2)之间的区域以及引脚(2)与引脚(2)之间的区域嵌置无填料塑封料(3)，所述无填料的塑封料(3)将引脚下部外围、引脚(2)与第一基岛(1.1)下部、第一基岛(1.1)与第四基岛(1.4)下部、第四基岛(1.4)与引脚(2)下部以及引脚(2)与引脚(2)下部连接成一体，所述引脚(2)设置有单圈。9. A kind of double-sided graphics chip according to claim 1 is mounted and plated first and then engraved with a single package structure, characterized in that the base island (1) has two groups, one group is the first base island (1.1), The other group is the fourth base island (1.4), the front of the fourth base island (1.4) is arranged in a multi-bump structure, in the peripheral area of the pin (2), the pin (2) and the first Area between base island (1.1), area between first base island (1.1) and fourth base island (1.4), area between fourth base island (1.4) and pin (2) and pin The area between (2) and the pin (2) is embedded with a filler-free molding compound (3), and the filler-free molding compound (3) connects the lower periphery of the pin, the pin (2) and the first base island ( 1.1) the bottom, the first base island (1.1) and the fourth base island (1.4) bottom, the fourth base island (1.4) and the bottom of the pin (2) and the pin (2) and the bottom of the pin (2) are connected to form In one piece, the pin (2) is provided with a single turn. 10.根据权利要求1所述的一种双面图形芯片正装先镀后刻单颗封装结构，其特征在于所述基岛(1)有二组也可以是多組基島，一组为第二基 岛(1.2)，另一组为第三基岛(1.3)，所述第二基岛(1.2)正面中央区域下沉，在第二基岛(1.2)正面中央下沉区域和第三基岛(1.3)正面通过导电或不导电粘结物质(6)设置有芯片(7)，在所述引脚(2)外围的区域、引脚(2)与第二基岛(1.2)之间的区域、第三基岛(1.3)背面、第二基岛背面(1.2)与第二基岛(1.2)之间的区域、第三基岛(1.3)背面与引脚(2)之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料(3)，所述无填料塑封料(3)将引脚下部外围、引脚(2)与第二基岛(1.2)下部、第三基岛(1.3)、第三基岛(1.3)与第二基岛(1.2)下部、第三基岛(1.3)背面与引脚(2)下部以及引脚(2)与引脚(2)下部连接成一体，所述引脚(2)设置有单圈。10. A double-sided graphic chip according to claim 1, which is packaged with a single chip engraved after being plated first, characterized in that the base island (1) has two groups or multiple groups of base islands, and one group is the first Two base islands (1.2), another group is the 3rd base island (1.3), said second base island (1.2) sinks in the central area of the front, sinks in the front central area of the second base island (1.2) and the third The front side of the base island (1.3) is provided with a chip (7) through a conductive or non-conductive adhesive substance (6), and in the peripheral area of the pin (2), between the pin (2) and the second base island (1.2) The area between, the back of the third base island (1.3), the area between the back of the second base island (1.2) and the second base island (1.2), the back of the third base island (1.3) and the pins (2) The area between the pins and the pins is embedded with a filler-free molding compound (3), and the filler-free molding compound (3) connects the lower periphery of the pin, the pin (2) and the second base island (1.2) Bottom, third base island (1.3), third base island (1.3) and second base island (1.2) bottom, third base island (1.3) back and pin (2) bottom and pin (2) and lead The lower part of the pin (2) is connected into one body, and the pin (2) is provided with a single loop. 11.根据权利要求1所述的一种双面图形芯片正装先镀后刻单颗封装结构，其特征在于所述基岛(1)有二组，一组为第二基岛(1.2)，另一组为第四基岛(1.4)，所述第二基岛(1.2)正面中央区域下沉，第四基岛(1.4)正面设置成多凸点状结构，在所述第四基岛(1.4)和引脚(2)的正面设置有第一金属层(4)，在所述第二基岛(1.2)、第四基岛(1.4)和引脚(2)的背面设置有第二金属层(5)，在所述第二基岛(1.2)正面中央下沉区域和第四基岛(1.4)正面通过导电或不导电粘结物质(6)设置有芯片(7)，在所述引脚(2)外围的区域、引脚(2)与第二基岛(1.2)之间的区域、第二基岛(1.2)与第四基岛(1.4)之间的区域、第四基岛(1.4)与引脚(2)之间的区域以及引脚(2)与引脚(2)之间的区域嵌置无填料塑封料(3)，所述无填料的塑封料(3)将引脚下部外围、引脚(2)与第二基岛(1.2)下部、第二基岛(1.2)与第四基岛(1.4)下部、第四基岛(1.4)与引脚(2)下部以及引脚(2)与引脚(2)下部连接成一体，所述引脚(2)设置有单圈。 11. A kind of double-sided graphics chip according to claim 1 is mounted and plated first and then engraved with a single package structure, characterized in that the base island (1) has two groups, one group is the second base island (1.2), The other group is the fourth base island (1.4), the central area of the front of the second base island (1.2) sinks, and the front of the fourth base island (1.4) is arranged in a multi-convex structure. (1.4) and the front of the pin (2) are provided with a first metal layer (4), and the second base island (1.2), the fourth base island (1.4) and the back of the pin (2) are provided with a second Two metal layers (5), on the central sinking area of the front of the second base island (1.2) and the front of the fourth base island (1.4) are provided with a chip (7) through a conductive or non-conductive bonding substance (6), on the The peripheral area of the pin (2), the area between the pin (2) and the second base island (1.2), the area between the second base island (1.2) and the fourth base island (1.4), the first The area between the four-base island (1.4) and the pin (2) and the area between the pin (2) and the pin (2) are embedded with a filler-free molding compound (3), and the filler-free molding compound ( 3) Connect the lower periphery of the pin, the lower part of the pin (2) and the second base island (1.2), the lower part of the second base island (1.2) and the fourth base island (1.4), the fourth base island (1.4) and the pin The lower part of (2) and the pin (2) are integrally connected with the lower part of the pin (2), and the pin (2) is provided with a single turn. the 12.根据权利要求1所述的一种双面图形芯片正装先镀后刻单颗封装结构，其特征在于所述基岛(1)有二组，一组为第三基岛(1.3)，另一组为第四基岛(1.4)，所述第四基岛(1.4)正面设置成多凸点状结构，在所述第三基岛(1.3)、第四基岛(1.4)和引脚(2)的正面设置有第一金属层(4)，在所述第四基岛(1.4)和引脚(2)的背面设置有第二金属层(5)，在所述引脚(2)外围的区域、引脚(2)与第四基岛(1.4)之间的区域、第三基岛(1.3)背面、第二基岛(1.2)与第四基岛(1.4)之间的区域、第三基岛(1.3)与引脚(2)之间的区域以及引脚与引脚之间的区域嵌置无填料塑封料(3)，所述无填料塑封料(3)将引脚下部外围、引脚(2)与第四基岛(1.4)下部、第三基岛(1.3)背面、第三基岛(1.3)背面与第四基岛(1.4)下部、第三基岛(1.3)背面与引脚(2)下部以及引脚(2)与引脚(2)下部连接成一体，所述引脚(2)设置有单圈。 12. A kind of double-sided graphic chip according to claim 1 is mounted and plated first and then engraved with a single package structure, characterized in that the base island (1) has two groups, one group is the third base island (1.3), The other group is the fourth base island (1.4), the front of the fourth base island (1.4) is arranged in a multi-convex structure, and the third base island (1.3), the fourth base island (1.4) and the guide A first metal layer (4) is provided on the front of the pin (2), a second metal layer (5) is provided on the back of the fourth base island (1.4) and the pin (2), and a second metal layer (5) is provided on the back of the pin ( 2) The peripheral area, the area between the pin (2) and the fourth base island (1.4), the back of the third base island (1.3), between the second base island (1.2) and the fourth base island (1.4) The area between the third base island (1.3) and the pin (2) and the area between the pins are embedded with filler-free molding compound (3), and the filler-free molding compound (3) will The lower periphery of the pin, the lower part of the pin (2) and the fourth base island (1.4), the back of the third base island (1.3), the back of the third base island (1.3) and the lower part of the fourth base island (1.4), the third base The back of the island (1.3) is integrally connected with the lower part of the pin (2) and the pin (2) is connected with the lower part of the pin (2), and the pin (2) is provided with a single loop. the
CN2010205178667U 2010-09-04 2010-09-04 Single packaging structure for mounting of plating-to-carving chip with double-sided graphics Expired - Fee Related CN201838578U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2010205178667U CN201838578U (en) 2010-09-04 2010-09-04 Single packaging structure for mounting of plating-to-carving chip with double-sided graphics

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2010205178667U CN201838578U (en) 2010-09-04 2010-09-04 Single packaging structure for mounting of plating-to-carving chip with double-sided graphics

Publications (1)

Publication Number Publication Date
CN201838578U true CN201838578U (en) 2011-05-18

Family

ID=44008681

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010205178667U Expired - Fee Related CN201838578U (en) 2010-09-04 2010-09-04 Single packaging structure for mounting of plating-to-carving chip with double-sided graphics

Country Status (1)

Country Link
CN (1) CN201838578U (en)

Similar Documents

Publication Publication Date Title
CN102403283B (en) Ball grid array packaging structure with basic islands and manufacturing method thereof
CN102376656B (en) Island-free four-sided leadless packaging structure and manufacturing method thereof
CN101840901B (en) Lead frame structure without base island electrostatic discharge ring and its production method
CN101950726A (en) First-coating last-etching single package method for positively packaging double-sided graphic chip
CN101814481A (en) No-pad lead frame structure and production method thereof
CN101969032B (en) Double-sided graphic chip right-handed electroplating-etching module packaging method
CN101958257A (en) Direct placement of double-sided graphics chip, first plating and engraving module packaging method
CN101958303B (en) Double-side graph chip forward single package structure and package method thereof
CN201936875U (en) Double-sided graphic chip normal-mounting module packaging structure
CN101958299B (en) Method for packaging single double-sided graphic chip by way of directly arranging and then sequentially plating and etching
CN102420206B (en) Four-side pin-free packaging structure subjected to plating and etching sequentially and manufacturing method thereof
CN201927599U (en) Module package structure for plating prior to etching of double-sided graphic flip chips
CN201838578U (en) Single packaging structure for mounting of plating-to-carving chip with double-sided graphics
CN102005431B (en) Flip-dual face graphic-chip plating-first and etching-second single encapsulation method
CN201838576U (en) Single packaging structure for direct arranging of chip with double-sided graphics
CN101958301B (en) Double-side graph chip direct-put single package structure and package method thereof
CN202394868U (en) Packaging structure of passive devices of single-base-island exposed type multi-circle pin electrostatic discharge rings
CN101958305A (en) Double-sided graphics chip front-mount module packaging structure and packaging method
CN202394898U (en) Single-base-island exposure type single-circle-pin packaging structure
CN202394926U (en) Multi-base embedded multi-loop-pin packaging structure
CN201838580U (en) Single packaging structure for inverted mounting of chip with double-sided graphics
CN101958304B (en) Double-side graph chip direct-put module package structure and package method thereof
CN102005430A (en) Double-sided graphics chip flip-chip module packaging method adopting plating firstly and etching secondly
CN202394897U (en) Encapsulation structure of multi-base-island exposed type single-circle pin passive device
CN202003984U (en) Single first-plating second-etching packaging structure of flip chip with double-sided graphs

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110518

Termination date: 20130904