CN201838580U - Single packaging structure for inverted mounting of chip with double-sided graphics - Google Patents
Single packaging structure for inverted mounting of chip with double-sided graphics Download PDFInfo
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- CN201838580U CN201838580U CN2010205178991U CN201020517899U CN201838580U CN 201838580 U CN201838580 U CN 201838580U CN 2010205178991 U CN2010205178991 U CN 2010205178991U CN 201020517899 U CN201020517899 U CN 201020517899U CN 201838580 U CN201838580 U CN 201838580U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本实用新型涉及一种双面图形芯片倒装单颗封装结构，所述结构包括引脚(2)、无填料的塑封料(环氧树脂)(3)、锡金属的粘结物质(6)、芯片(7)和有填料塑封料(环氧树脂)(9)，所述引脚(2)正面延伸到后续贴装芯片的下方，在所述后续贴装芯片的下方的引脚(2)正面第一金属层(4)上通过锡金属的粘结物质(6)设置有芯片(7)，在所述引脚(2)的上部以及芯片(7)外包封有填料塑封料(9)，在所述引脚(2)外围的区域以及引脚(2)与引脚(2)之间的区域嵌置有无填料的塑封料(3)，所述有填料塑封料(9)将引脚(2)正面局部单元进行包覆，在所述引脚(2)背面设置有柱子(10)，柱子(10)根部埋入所述无填料的塑封料(3)内。本实用新型装片时可承受超高温且不会因不同物质的不同物理性质而产生引线框扭曲，也不会再有产生掉脚的问题。
The utility model relates to a double-sided graphics chip flip-chip packaging structure, the structure includes pins (2), plastic sealing material (epoxy resin) (3) without filler, and tin metal bonding substance (6) , chip (7) and filler molding compound (epoxy resin) (9), the front of the pin (2) extends to the bottom of the follow-up chip, and the pin (2) below the follow-up chip ) on the first metal layer (4) on the front side, a chip (7) is provided through a bonding substance (6) of tin metal, and a filler molding compound (9) is encapsulated on the top of the pin (2) and the chip (7) ), the area around the pin (2) and the area between the pin (2) and the pin (2) are embedded with a filler-free molding compound (3), and the filler molding compound (9) The front part of the pin (2) is coated with a partial unit, and a column (10) is arranged on the back of the pin (2), and the root of the column (10) is embedded in the plastic sealing compound (3) without filler. The utility model can withstand ultra-high temperature during chip loading, and the lead frame will not be distorted due to different physical properties of different materials, and the problem of foot drop will not occur again.
Description
(1) technical field
The utility model relates to single encapsulating structure of a kind of two-sided graphic chips upside-down mounting.Belong to the semiconductor packaging field.
(2) background technology
The production method of traditional chip-packaging structure is: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in Figure 7) of lead frame.Etching is then carried out at the back side of lead frame again in encapsulation process.This method has the following disadvantages:
Because only carried out the work that etches partially before the plastic packaging in the metal substrate front, and plastic packaging material only wraps the height of half pin of pin in the plastic packaging process, so the constraint ability of plastic-sealed body and pin has just diminished, when if the plastic-sealed body paster is not fine to pcb board, do over again again and heavily paste, with regard to the problem (as shown in Figure 8) that is easy to generate pin.Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
In addition, because the distance between chip and the pin is far away, the length of metal wire is longer, shown in Fig. 9～10, and metal wire cost higher (the especially metal wire of Ang Gui proof gold matter); Same because the length of metal wire is longer, make that the signal output speed of chip is slow (especially the product of storage class and the calculating that needs mass data are more outstanding); Too because the length of metal wire is longer, so also higher to the interference of signal in existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole; Because the distance between chip and the pin is far away, make that the volume and the area of encapsulation are bigger again, material cost is higher, and discarded object is more.
For this reason, the applicant in first to file name be called the utility model patent of " flip chip encapsulation structure ", its application number is: 201020177746.7.Its major technique feature is: adopt the back side of metal substrate to etch partially earlier, form the half-etched regions of depression at the back side of metal substrate, form the back side of Ji Dao and pin simultaneously relatively, again in described half-etched regions, packless soft gap filler in the full-filling, and toast simultaneously, make packless soft underfill cures become packless plastic packaging material (epoxy resin), to wrap the back side of pin.And then etch partially in the front of metal substrate, form the front of Ji Dao and pin simultaneously relatively.Its beneficial effect mainly contains:
1) because the zone between the back side of described metal substrate pin and pin is equipped with packless soft gap filler, this packless soft gap filler has filler plastic packaging material (epoxy resin) to wrap the height of whole pin with the routine in the metal substrate front in the plastic packaging process, so the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again, as Figure 11.
2) owing to adopted the positive method of separating the etching operation of lead frame with the back side, so in the etching operation, can form slightly little and the structure that positive pin size is big slightly of the size of back side pin, and slide and fall pin in the tighter more difficult generation of being wrapped up by packless plastic packaging material (epoxy resin) with the size that varies in size up and down of a pin.
3) because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and the highdensity pin.
4) because volume after being encapsulated is significantly dwindled, more direct embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
But, still have following deficiency: because the preceding advanced line lead frame back side of encapsulation does not have the parcel pin operation of filler plastic packaging material, when carrying out the high temperature load in lead frame front and routing operation again, because of the physical property of two kinds of materials of lead frame and no filler plastic packaging material different, the coefficient of expansion of two kinds of materials is also different, at high temperature be subjected to the thermal deformation difference, lead frame produces distortion when causing follow-up load.Therefore this kind encapsulating structure can not superhigh temperature resistant (more than 200 ℃) when load.And be by the packaging body volume being done to such an extent that reach resistant to elevated temperatures requirement very greatly, be with regard to not anti-superhigh temperature under the increasing situation but require the more and more littler and power of the volume of packaging body now. in the past
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, can bear superhigh temperature when a kind of load is provided and can not produce the lead frame distortion, also not have single encapsulating structure of two-sided graphic chips upside-down mounting of the problem that produces pin again because of the different physical properties of different material.
The purpose of this utility model is achieved in that single encapsulating structure of a kind of two-sided graphic chips upside-down mounting, comprise pin, packless plastic packaging material (epoxy resin), the bonding material of tin metal, chip and filler plastic packaging material (epoxy resin) arranged, described pin front extends to the below of follow-up pasting chip, front at described pin is provided with the first metal layer, be provided with second metal level at the back side of described pin, bonding material by tin metal on the pin front the first metal layer below the described follow-up pasting chip is provided with chip, outside the top of described pin and chip, be encapsulated with filler plastic packaging material (epoxy resin), zone and the zone between pin and the pin in described pin periphery are equipped with packless plastic packaging material (epoxy resin), described packless plastic packaging material (epoxy resin) links into an integrated entity periphery, pin bottom and pin bottom and pin bottom, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration, it is characterized in that: described have filler plastic packaging material (epoxy resin) that the positive local unit of pin is coated, be provided with pillar at the described pin back side, the pillar root is imbedded in the described packless plastic packaging material (epoxy resin).
The beneficial effects of the utility model are:
1, lead frame superhigh temperature resistant (more than 200 ℃)
Owing to adopted two-sided figure etched lead frame technology, once finish lead frame just, the back of the body the two-sided etching in two sides, the high temperature load routing in advanced line lead frame front carries out the pin parcel operation at the lead frame back side again when encapsulating simultaneously, has only a kind of material of lead frame when making the load routing, superhigh temperature resistant (generally being below the 200 ℃) performance of lead frame has been guaranteed in impact because of there not being multiple material coefficient of expansion difference to be brought in using the processing procedure process of superhigh temperature.
2, can guarantee lead frame load intensity
Do not seal because do not do in advance earlier, the pressure that bears during the lead frame load is big, can make lead frame produce vibration during load, and the phenomenon of sinking can appear in lead frame.The utility model is by leaving the design of pillar, the intensity of lead frame during with the increase load at the lead frame back side.
3, guarantee not have again the problem that produces pin
Owing to adopted two-sided etched technology, so planning and designing easily with produce up big and down small pin configuration, the levels plastic packaging material is wrapped up big and down small pin configuration closely together, so the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again.
4, separate etched technology owing to used the lead frame back side with the front, so the pin in lead frame front can be extended to as much as possible the center of packaging body, impel chip and the Pin locations can be identical with the position of chip bonding, as shown in Figure 6, so electrical transmission can promote especially the product of storage class and the calculating that needs mass data significantly, and will be more outstanding.
5, the volume of encapsulation and area can significantly be dwindled
Because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin.
6, material cost and material usage reduce
Because volume after being encapsulated is significantly dwindled, more direct embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
7, the advantage of single encapsulation of the local Single of employing unit has:
1) in different application, the pin at plastic-sealed body edge can be stretched out plastic-sealed body.
2) pin at plastic-sealed body edge stretches out outside the plastic-sealed body and can clearly check out situation about being welded on the pcb board.
3) area of modular type is easy because multiple different shrinkage that material structure produces is different should stand distortion than conference, and single encapsulation of local unit just can disperse fully multiple different shrinkage that material structure produces different should stand distortion.
4) single is encapsulated in when carrying out the plastic-sealed body cutting and separating, because the thickness that cuts has only the thickness of pin, so the speed of cutting can be come much soon than the encapsulating structure of modular type, so and incisory blade because the thickness of cutting just approached life-span of cutting blade relative also just become longer.
(4) description of drawings
Fig. 1 (A)～Fig. 1 (Q) is single encapsulating structure embodiment of the two-sided graphic chips upside-down mounting of the utility model 1 each production process schematic diagram.
Fig. 2 is single encapsulating structure embodiment 1 structural representation of the two-sided graphic chips upside-down mounting of the utility model.
Fig. 3 is the vertical view of Fig. 2.
Fig. 4 (A)～Fig. 4 (Q) is single encapsulating structure embodiment of the two-sided graphic chips upside-down mounting of the utility model 2 each production process schematic diagram.
Fig. 5 is single encapsulating structure embodiment 2 structural representations of the two-sided graphic chips upside-down mounting of the utility model.
Fig. 6 is the vertical view of Fig. 5.
Fig. 7 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Fig. 8 pin figure for what formed in the past.
Fig. 9 is encapsulating structure one schematic diagram in the past.
Figure 10 is the vertical view of Fig. 9.
Figure 11 is encapsulating structure two schematic diagrames in the past.
Reference numeral among the figure:
(5) embodiment
Embodiment 1: single-chip individual pen pin
Referring to Fig. 2 and Fig. 3, Fig. 2 is single encapsulating structure embodiment 1 structural representation of the two-sided graphic chips upside-down mounting of the utility model.Fig. 3 is the vertical view of Fig. 2.By Fig. 2 and Fig. 3 as can be seen, single encapsulating structure of the two-sided graphic chips upside-down mounting of the utility model, comprise pin 2, packless plastic packaging material (epoxy resin) 3, the bonding material 6 of tin metal, chip 7 and filler plastic packaging material (epoxy resin) 9 is arranged, described pin 2 fronts extend to the below of follow-up pasting chip, be provided with the first metal layer 4 in the front of described pin 2, be provided with second metal level 5 at the back side of described pin 2, bonding material 6 by tin metal on the 2 front the first metal layers 4 of the pin below the described follow-up pasting chip is provided with chip 7, outside the top of described pin 2 and chip 7, be encapsulated with filler plastic packaging material (epoxy resin) 9, this has filler plastic packaging material (epoxy resin) 9 that pin 2 positive local unit are coated, be equipped with packless plastic packaging material (epoxy resin) 3 in the zone of described pin 2 peripheries and the zone between pin 2 and the pin 2, described packless plastic packaging material (epoxy resin) 3 links into an integrated entity pin periphery, 2 bottom and pin 2 bottoms and pin 2 bottoms, and make described pin 2 back side sizes less than pin 2 positive sizes, form up big and down small pin configuration, be provided with pillar 10 at described pin 2 back sides, pillar 10 roots are imbedded in the described packless plastic packaging material (epoxy resin) 3.
Its method for packing is as follows:
Step 1, get metal substrate
Referring to Fig. 1 (A), get the suitable metal substrate of a slice thickness 11.The material of metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper, aluminium, iron, copper alloy or dilval etc.
Referring to Fig. 1 (B), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 12 and 13 of exposure imaging, to protect follow-up electroplated metal layer process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane in step 3, metal substrate front needs the exposure of plated metal layer region/develop and windows
Referring to Fig. 1 (C), the metal substrate front that utilizes exposure imaging equipment that step 2 is finished photoresistance glued membrane lining operation is carried out exposure imaging and is removed part photoresistance glued membrane, carries out the zone of electroplated metal layer to expose the positive follow-up needs of metal substrate.
The zone of having windowed in step 4, metal substrate front is carried out metal level and is electroplated lining
Referring to Fig. 1 (D), the first metal layer 4 plating linings are carried out in the zone of having windowed in metal substrate front in the step 3, this first metal layer 4 places the front of described pin 2.
Photoresistance glued membrane striping is carried out at step 5, metal substrate front and the back side
Referring to Fig. 1 (E), the positive remaining photoresistance glued membrane of metal substrate and the photoresistance glued membrane at the metal substrate back side are all removed.
Referring to Fig. 1 (F), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 14 and 15 of exposure imaging, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane of step 7, metal substrate needs the exposure of two-sided etching area/develop and windows
Referring to Fig. 1 (G), exposure imaging removal part photoresistance glued membrane is carried out at the metal substrate front and the back side that utilize exposure imaging equipment that step 6 is finished photoresistance glued membrane lining operation, to expose the two-sided etching operation of metal substrate that the localized metallic substrate carries out in order to follow-up needs.
Step 8, metal substrate carry out two-sided etching operation
Referring to Fig. 1 (H), after the exposure/development and windowing task of completing steps seven, the i.e. etching operation of carrying out each figure at the front and the back side of metal substrate, etch the front and back of pin 2, simultaneously the pin front is extended to as much as possible the below of follow-up pasting chip, and make the positive size of the back side size of described pin 2, form up big and down small pin 2 structures less than pin 2; And form pillar 10 at pin 2 back sides, and between pin 2 and pin 2 company's of leaving muscle 16.
Photoresistance glued membrane striping is carried out at step 9, metal substrate front and the back side
Referring to Fig. 1 (I), the photoresistance glued membrane of metal substrate front and back remainder is all removed, make lead frame,
Referring to Fig. 1 (J), the bonding material 6 by tin metal on the 2 front the first metal layers 4 of the pin below the described follow-up pasting chip carries out mounting of chip 7.
Step 11, be encapsulated with filler plastic packaging material (epoxy resin)
Referring to Fig. 1 (K), the semi-finished product front that load is finished is carried out local unit and is encapsulated with filler plastic packaging material (epoxy resin) 9 operations, pin 2 positive local unit zones are exposed filler plastic packaging material (epoxy resin) 9 is arranged, and carry out curing operation after plastic packaging material is sealed, make the top of pin and chip and metal wire all be had filler plastic packaging material (epoxy resin) to seal outward.
Referring to Fig. 1 (L), utilize by coating equipment to be covered respectively and can to carry out the photoresistance glued membrane 17 and 18 of exposure imaging will finishing the half-finished front that is encapsulated with filler plastic packaging material (epoxy resin) operation and the back side, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
Step 13, finish the exposure that the half-finished back side that is encapsulated with filler plastic packaging material (epoxy resin) operation needs etching area/develop and windowing
Referring to Fig. 1 (M), exposure imaging removal part photoresistance glued membrane is carried out at the semi-finished product back side that is encapsulated with filler plastic packaging material (epoxy resin) operation of finishing that utilizes exposure imaging equipment that step 12 is finished photoresistance glued membrane lining operation, to expose company's muscle 16 that leaves after the two-sided etching operation of step 8 metal substrate and the pillar 10 that forms at pin 2 back sides, carry out the pillar root and connect muscle etching operation in order to follow-up needs.
Referring to Fig. 1 (N), after the exposure/development and windowing task of completing steps 13, promptly carry out the etching operation of each figure finishing the semi-finished product back side that is encapsulated with filler plastic packaging material (epoxy resin) operation, the company's muscle 16 that leaves after the two-sided etching operation of step 8 metal substrate is all etched away, root at pillar 10 described in this process also can etch away relative thickness simultaneously, make the pillar root not expose the encapsulating structure back side after sealing, avoid producing and open circuit.
Photoresistance glued membrane striping is carried out at step 15, semi-finished product front and the back side
Referring to Fig. 1 (O), the photoresistance glued membrane of the semi-finished product back side remainder of completing steps 14 etching operations and the photoresistance glued membrane in semi-finished product front are all removed.
Referring to Fig. 1 (P), packless plastic packaging material (epoxy resin) operation is sealed at the semi-finished product back side of completing steps 15 described striping operations, and carry out curing operation after plastic packaging material is sealed, make the zone of pin 2 peripheries and the zone between pin 2 and the pin 2 all set packless plastic packaging material (epoxy resin) 3, this packless plastic packaging material (epoxy resin) 3 links into an integrated entity periphery, pin bottom and pin 2 bottoms and pin 2 bottoms, and described pillar 10 roots are imbedded in this packless plastic packaging material (epoxy resin) 3.
Specify: but also because many described pillars 10 in packaging body, the structure in packaging body is more strong on the contrary (can be compared to mix increased reinforcing bar in the earth intensity but also flexible are arranged not only)
Referring to Fig. 1 (Q), completing steps 16 is sealed the operation of no filler plastic packaging material described pin the back side and step 12 is described exposes the plating lining operation that the pin 2 positive local unit zones that filler plastic packaging material (epoxy resin) is arranged are carried out second metal level 5 and the first metal layer 4 respectively, and the material of electroplating can be tin, nickel gold, NiPdAu .... wait metal material.
Referring to Fig. 2 and Fig. 3, the semi-finished product of ten seven the second metal levels of completing steps being electroplated lining carry out cutting operation, make originally more than of chips that connect together in array formula aggregate mode independent, make single encapsulating structure finished product of two-sided graphic chips upside-down mounting.
Embodiment 2: multicore sheet individual pen pin
Referring to Fig. 4～6, Fig. 4 (A)～Fig. 4 (Q) is single encapsulating structure embodiment of the two-sided graphic chips upside-down mounting of the utility model 2 each production process schematic diagram.Fig. 5 is single encapsulating structure embodiment 2 structural representations of the two-sided graphic chips upside-down mounting of the utility model.Fig. 6 is the vertical view of Fig. 5.By Fig. 4, Fig. 5 and Fig. 6 as can be seen, embodiment 2 only is with the difference of embodiment 1: described chip 7 is provided with many.
Claims (2)
1. single encapsulating structure of a two-sided graphic chips upside-down mounting, comprise pin (2), packless plastic packaging material (3), the bonding material of tin metal (6), chip (7) and filler plastic packaging material (9) is arranged, described pin (2) front extends to the below of follow-up pasting chip, be provided with the first metal layer (4) in the front of described pin (2), be provided with second metal level (5) at the back side of described pin (2), the bonding material (6) that pin below described follow-up pasting chip (2) front the first metal layer (4) is gone up by tin metal is provided with chip (7), outside the top of described pin (2) and chip (7), be encapsulated with filler plastic packaging material (9), be equipped with packless plastic packaging material (3) in the zone of described pin (2) periphery and the zone between pin (2) and the pin (2), described packless plastic packaging material (3) links into an integrated entity pin (2) periphery, bottom and pin (2) bottom and pin (2) bottom, and make described pin (2) back side size less than the positive size of pin (2), form up big and down small pin configuration, it is characterized in that: described have filler plastic packaging material (9) that the positive local unit of pin (2) is coated, be provided with pillar (10) at described pin (2) back side, pillar (10) root is imbedded in the described packless plastic packaging material (3).
2. single encapsulating structure of a kind of two-sided graphic chips upside-down mounting according to claim 1 is characterized in that described chip (7) is provided with many.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205178991U CN201838580U (en) | 2010-09-04 | 2010-09-04 | Single packaging structure for inverted mounting of chip with double-sided graphics |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205178991U CN201838580U (en) | 2010-09-04 | 2010-09-04 | Single packaging structure for inverted mounting of chip with double-sided graphics |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201838580U true CN201838580U (en) | 2011-05-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010205178991U Expired - Fee Related CN201838580U (en) | 2010-09-04 | 2010-09-04 | Single packaging structure for inverted mounting of chip with double-sided graphics |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201838580U (en) |
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2010
- 2010-09-04 CN CN2010205178991U patent/CN201838580U/en not_active Expired - Fee Related
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110518 Termination date: 20130904 |