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CN101540305A - 半导体封装及其工艺 - Google Patents

半导体封装及其工艺 Download PDF

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Publication number
CN101540305A
CN101540305A CNA2009101274968A CN200910127496A CN101540305A CN 101540305 A CN101540305 A CN 101540305A CN A2009101274968 A CNA2009101274968 A CN A2009101274968A CN 200910127496 A CN200910127496 A CN 200910127496A CN 101540305 A CN101540305 A CN 101540305A
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semiconductor chip
chip
central
pins
protrusion
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CN101540305B (zh
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张简宝徽
胡平正
陈建文
李旭阳
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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Abstract

一种半导体封装及其工艺，封装体包括芯片座、多个引脚、芯片以及封装胶体。芯片座包括上倾斜部、下倾斜部以及以具有中心部的凹穴底部定义凹穴的周围边缘区域。每一引脚具有上倾斜部与下倾斜部。芯片配置于凹穴底部的中心部且电性连接至引脚。封装胶体形成于芯片与引脚上，且实质上填满凹穴并实质上覆盖芯片座与引脚的上倾斜部。芯片座与引脚的下倾斜部至少部份延伸至封装胶体的下表面。

Description

半导体封装及其工艺
技术领域
本发明是有关于一种半导体芯片封装，且特别是有关于一种具有一凹穴结构的进阶式四方扁平无引脚封装(advanced Quad Flat No Lead，aQFN)及其工艺。
背景技术
由于使用者对于小尺寸芯片的处理能力的需求越来越大，因此半导体芯片也变得更加复杂。为了解决上述问题，封装技术逐渐发展，举例而说，由增加引脚密度来降低一封装体固定在一印刷电路板上的覆盖面积。此外，有些封装技术，例如四方扁平无引脚封装(Quad Flat No Lead，QFN)，可由提供多行的内引脚与外引脚连接至一导线架的一可抛弃部，来增加引脚密度。然而，这类导线架的制作方式很难达成两行以外的引脚，因此当使用者对于导线架的引脚密度的需求越来越高时，如何利用封装技术来形成所需的引脚密度，实为一待解决的问题。
此外，除了增加引脚密度之外，使用者更希望能由其它的方式来降低封装体的大小，例如是降低封装体的高度。同时，也希望能维持一封装胶体与引脚之间的结合力(mold locking)，并促进封装体能由表面黏着技术接合于一印刷电路板上。当然，也可以制定一符合上述这些目的的封装工艺。然而，目前现有的封装技术只能符合上述其中一些目的，而不符合多数或是所有的目的。
发明内容
本发明的目的是提供一种半导体封装及其工艺。
为实现上述目的，本发明提供的半导体封装，其包括芯片座、多个引脚、半导体芯片与封装胶体。芯片座包括(1)具有上表面且以凹穴底部定义凹穴的周围边缘区域，其中凹穴底部具有中心部(2)配置邻接于周围边缘区域的上表面且面向凹穴的上倾斜部，以及(3)配置邻接于上倾斜部且面向凹穴的下倾斜部。这些引脚环绕芯片座。每一引脚具有上表面、下表面、配置邻接于每一引脚的上表面的上倾斜部以及配置邻接于每一引脚的下表面的下倾斜部。半导体芯片配置于凹穴底部的中心部且电性连接至这些引脚。封装胶体形成于半导体芯片与这些引脚上，以实质上填充于凹穴且实质上覆盖芯片座的上倾斜部与这些引脚的这些上倾斜部，而芯片座的下倾斜部与这些引脚的这些下倾斜部至少部分从封装胶体的下表面向外延伸。
本发明提出的半导体封装的工艺，首先，提供金属承载板。金属承载板包括(1)基部，具有上表面与下表面(2)中心突出部，具有上表面且从基部向上延伸，中心突出部定义基部的上表面的中心区域，中心区域具有中心部(3)多个周围突出部，每一周围突出部具有上表面且从基部向上延伸，并环绕中心突出部(4)第一金属镀层，形成于中心突出部的上表面上与周围突出部的上表面上，以及(5)第二金属镀层，形成于对应中心区域下方、中心突出部下方以及这些周围突出部下方的金属承载板的下表面上。接着，贴附第一半导体芯片于中心突出部。电性连接第一半导体芯片至这些周围突出部至少一第一突出部上。然后，形成封装胶体于第一半导体芯片与这些周围突出部上。最后，蚀刻第二金属镀层之外的金属承载板的下表面的区域，以使这些周围突出部与中心突出部分离而形成多个引脚与芯片座，其中芯片座包括中心突出部与中心区域，每一引脚具有配置邻接每一引脚的下表面的下倾斜部，芯片座具有配置邻接芯片座的下表面的下倾斜部，芯片座的下倾斜部与每一引脚的下倾斜部至少部分从封装胶体的下表面向外延伸。
本发明还提供一种半导体封装，其包括芯片座、多个引脚、半导体芯片以及封装胶体。芯片座包括(1)基部，具有上表面与下表面(2)突出部，从基部向上延伸且配置邻接于基部的周围边缘，其中突出部具有上表面；(3)第一侧表面，延伸介于突出部的上表面与基部的下表面之间，其中第一侧表面具有相较于突出部的上表面更接近基部的下表面的第一尖端。这些引脚环绕芯片座。至少这些引脚之一具有第二尖端的第二侧表面。第一半导体芯片，配置于基部的上表面，且电性连接至这些引脚。封装胶体形成于第一半导体芯片与这些引脚上，以实质上覆盖基部的上表面、第一尖端上方的第一侧表面的至少一部分与第二尖端上方的第二侧表面的至少一部分，而第一尖端下方的第一侧表面的至少一部分与第二尖端下方的第二侧表面的至少一部分突出于封装胶体的下表面。
附图说明
图1为本发明一实施例的一种半导体封装的剖面示意图。
图2为本发明一实施例的一种芯片座的放大剖面示意图。
图3为本发明一实施例的一种引脚的放大剖面示意图。
图4为本发明一实施例的一种金属承载板的一部分的上视图。
图5显示本发明一实施例的一种金属承载板的工艺。
图6显示本发明一实施例的一种半导体封装的工艺。
图7显示本发明一实施例的一种具有多堆叠芯片的半导体封装的工艺。
图8显示本发明一实施例的一种半导体封装进行表面黏着工艺的流程示意图。
图9显示本发明另一实施例的一种半导体封装进行表面工艺的流程示意图。
附图中主要组件符号说明
100、100a、100b封装体；101芯片座；102芯片；102a第一芯片；102b第二芯片；104、104a、104b焊线；106焊垫；108封装胶体；111凹穴；112凹穴底部；112a中心部；112b凹陷部；114周围边缘区域；116、117、126、127金属镀层；140模盖厚度；142厚度；144距离；145引脚间隔；146高度差；148隔开距离；150、151、154、155、164上表面；152、153、156、157、160下表面；162侧表面；166平面；171引脚；171A、171B外引脚；202基部；204、206距离；208侧表面；208a下倾斜部；208b尖端；208c上倾斜部；210保护层；212上表面；212a中心区域；212b凹陷部；213突出部；218上倾斜部；308侧表面；308a下倾斜部；308b尖端；308c上倾斜部；310保护层；400金属承载板；402基部(芯片放置区)；404中心突出部(周围边缘区域)；404a接地段；404b电源段；406周围突出部(周围凸块)；408角落周围突出部；410虚线；500金属承载板；500a、500b内连接部；501铜板；502上表面；504下表面；506、508光阻层；510第一曝光部；512第二曝光部；514第一金属镀层；516第二金属镀层；518、620区域；600a、600b连接封装体；700连接层；800、802焊接界面；804、806液化焊料块；808印刷电路板；900焊料；902焊料块；908印刷电路板。
具体实施方式
为让本发明的上述特征和优点能更明显易懂，以下特举实施例，并配合附图作详细说明。
图1为本发明的一实施例的一种半导体封装的剖面示意图。在本实施例中，封装体100包括一具有一周围边缘区域114的芯片座101，其中周围边缘区域114以一凹穴底部112定义出一凹穴111。周围边缘区域114可完全地环绕凹穴111，但于其它实施例中，周围边缘区域114亦可部分地环绕凹穴111。凹穴底部112具有一中心部112a。凹穴底部112也可包括一环绕中心部112a的凹陷部112b。中心部112a例如是位于凹穴底部112的中央，但当凹陷部112b的宽度不一致时，中心部112a亦可不位于凹穴底部112的中央。凹陷部112b可完全地可完全地环绕中心部112a，但于其它实施例中，凹陷部112b亦可部分地环绕中心部112a。芯片102是由一黏着层(未显示)贴附于凹穴底部112。黏着层例如是一导电黏着材料或一非导电黏着材料，其中非导电黏着材料例如是非导电环氧树脂(epoxy)。在本实施例中，芯片102贴附于中心部112a。芯片102的主动面上的多个焊垫106通过多条焊线104电性连接至这些引脚171与至少部分周围边缘区域114。这些引脚171例如是完全环绕或部分地环绕芯片座101。
图2为本发明的一实施例的一种芯片座的放大剖面示意图。在本实施例中，芯片座101具有一侧表面208，其中侧表面208可完全地或部分地延伸环绕于芯片座101的一周长。图2中，侧表面208包括一配置邻接于周围边缘区域114的一上表面151且面向凹穴111的上倾斜部208c。侧表面208也包括一配置邻接于上倾斜部208c且面向凹穴111的下倾斜部208a。周围边缘区域114亦包括一配置邻接上表面151且朝着凹穴111的上倾斜部218。芯片座101的侧表面208的上倾斜部208c与下倾斜部208a以及周围边缘区域114的上倾斜部218可以是直线或曲线，且不垂直于周围边缘区域114的上表面151。侧表面208亦包括一尖端208b。
图3为本发明的一实施例的一种引脚的放大剖面示意图。在本实施例中，引脚171包括一侧表面308，其中侧表面308可完全地或部分地延伸环绕于引脚171的一周长。于图3中，侧表面308包括一配置邻接于引脚171的一上表面155的上倾斜部308c。侧表面308亦包括一配置邻接于引脚171的一下表面157的下倾斜部308a。引脚171的侧表面308的上倾斜部308c与下倾斜部308a可以是直线或曲线，且分别不垂直于引脚的上表面155与下表面157。侧表面308亦包括一尖端308b。
请同时参考图1、图2与图3，封装胶体108形成于芯片102、芯片座101与引脚171上，以使封装胶体108实质上填充于凹穴111与实质上覆盖周围边缘区域114的上倾斜部218。封装胶体108亦实质上覆盖芯片座101的上倾斜部208c以及引脚171的上倾斜部308c。在此所述的“实质上”一词，部分是意指封装胶体108填充于具有芯片102配置于凹穴底部112的凹穴111，同时也意指封装胶体108填充于凹穴111以充份地减小或降低气泡与湿气，且覆盖芯片102、焊线104、侧表面208的上倾斜部208c、周围边缘区域114的上倾斜部218以及引脚171的上倾斜部308c，用以提供足够的保护来避免受到氧化、湿气以及其它环境条件的影响以符合封装需求。在本实施例中，芯片座101的下倾斜部208a与引脚171的下倾斜部308a至少部分从封装胶体108的下表面160向外延伸。或者，芯片座101的下倾斜部208a或引脚171的下倾斜部308a至少部分从封装胶体108的下表面160向外延伸。
侧表面208的上倾斜部208c、周围边缘区域114的上倾斜部218以及引脚171的上倾斜部308c可显著地增加接触面积，因此除了封装胶体108与芯片座101之间的黏着力以及封装胶体108与引脚171之间的黏着力会增加之外，还可以提高封装胶体108与芯片座101及引脚171之间的结合力(mold locking)，同时亦可延长湿气扩散于封装体100内的时间与路径。
在本实施例中，侧表面208的上倾斜部208c与引脚171的上倾斜部308c实质上具有凹陷的轮廓。在此所述的“实质上”一词指的是侧表面208的上倾斜部208c与引脚171的上倾斜部308c大体而言为凹面，例如朝着芯片座101的中心与引脚171向内环绕，但侧表面208的上倾斜部208c与引脚171的上倾斜部308c可包括不规则的表面或崎岖不平的小尖端，例如为一粗糙表面，以远离芯片座101的中心与引脚171向外环绕。举例而言，图3中引脚171的上倾斜部308c具有一整体形状，其中此整体形状朝着引脚171的中心向内环绕。同时，引脚171的上倾斜部308c是具有许多粗糙的结构。这些粗糙结构于封装时可吸引封装胶体108，因此可增加封装胶体108内的引脚171的结合力。这些粗糙结构可以藉由精准地控制蚀刻速率或其它适合的工艺来形成。同样地，芯片座101的下倾斜部208a与引脚171的下倾斜部308a实质上具有凹陷的轮廓。在此所述的“实质上”一词指的是芯片座101的下倾斜部208a与引脚171的下倾斜部308a大体而言为凹面，例如朝着芯片座101的中心与引脚171向内环绕。举例而言，图2中引脚171的下倾斜部308a具有一整体形状，其中此整体形状朝着引脚171的中心向内环绕。同理，周围边缘区域114的上倾斜部218实质上具有凹陷的轮廓。在此所述的“实质上”一词指的是周围边缘区域114的上倾斜部218大体而言为凹面，例如朝着周围边缘区域114的中心向内环绕。举例而言，图2中周围边缘区域114的上倾斜部218具有一整体形状，其中此整体形状朝着周围边缘区域114的中心向内环绕。
在此必须了解的是，芯片座101可以有不同于上述实施例的描述。举例来说，图2中芯片座101包括一具有一上表面212与一下表面153的基部202，突出部213具有一上表面151，且从基部202延伸向上延伸并配置邻接于基部202的一周围边缘。一侧表面208延伸介于突出部213的上表面151与基部202的下表面153之间，且包括一尖端208b。一侧表面218延伸介于突出部213的上表面151与基部202的上表面212之间。在本实施例中，基部202的上表面212包括一中心区域212a，其中芯片102配置于中心区域212a。基部202的上表面212可更包括一环绕中心区域212a的凹陷部212b。中心区域212a例如大约位于基部202的上表面212的中央，但当凹陷部212b的宽度不一致时，中心区域212a亦可不位于基部202的上表面212的中央。凹陷部212b例如是完全地环绕中心区域212a，但于其它实施例中，凹陷部212b亦可部分地环绕中心区域212a。
在此也必须了解的是，封装胶体108亦可以有不同于上述实施例的描述。举例而言，请参考图1、图2与图3，封装胶体108形成于芯片102、芯片座101与引脚171上，以使封装胶体108实质上覆盖基部202的上表面212与侧表面218。封装胶体108也实质上覆盖于尖端208b上方的至少一部分的侧表面208与尖端308b上方的至少一部分的侧表面308。在此所述的“实质上”一词，部分是意指封装胶体108覆盖于具有芯片102配置于其上表面212的基部202，同时也意指封装胶体108覆盖芯片102、焊线104、基板202的上表面212、侧表面218、尖端208b上方的部分侧表面208与尖端308b上方的部分侧表面308，用以提供足够的保护来避免受到氧化、湿气以及其它环境条件的影响以符合封装需求。在本实施例中，尖端208b下方的至少部分侧表面208从封装胶体108的下表面160向外突出。同理，尖端308b上方的至少部分侧表面308从封装胶体108的下表面160向外突出。
请再参考图1，封装体100还包括一配置于周围边缘区域114的上表面151的金属镀层116，或者，金属镀层116亦可以配置于突出部213的上表面151上，请参考图2。封装体100还包括一配置于芯片座101的下表面153的金属镀层117，请参考图1，或者，金属镀层117亦可以配置于基部202的下表面153上，请参考图2。请再参考图1，封装体100也可以还包括一配置于引脚171的上表面155的金属镀层126以及一配置于引脚171的下表面157的金属镀层127。金属镀层116、117、126、127例如是利用有电电镀(electrolytic plating)或无电电镀(electroless plating)的方式所形成。由于芯片座101的表面与引脚171的表面贴附金属镀层116、117、126、127，因此可于打线接合工艺中有效提高焊线104的接合力，且亦可以保护芯片座101的下表面与引脚171的下表面，以避免受到氧化及其它环境条件的影响来以符合封装需求。于较佳实施例中，金属镀层116、117、126、127可包括一连接于芯片座101的表面151、153以及引脚171的表面155、157的镍层以及一覆盖镍层的金层或钯层。或者，金属镀层116、117、126、127可包括一镍合金以及一金层与一钯层两者之一或其组合。
请再同时参考图1、图2以及图3，一隔开距离148是指芯片座101的下倾斜部208a与/或引脚171的下倾斜部308a从封装胶体108的下表面160向外延伸的距离，于其它实施例中，此隔开距离148可以包括或省略金属镀层117、127的厚度。或者，隔开距离148可以参考尖端208b下方的部分侧表面208与/或尖端308b下方的部分侧表面308从封装胶体108的下表面160向外延伸的距离。芯片座101与/或引脚171从封装胶体108的下表面160向外延伸的突出部可由芯片座101与/或引脚171所暴露出的其它区域贴附焊料来提高芯片座101与引脚171于一电路板上的焊接性(solderability)。也就是说，可提高封装体100由表面黏着技术而接合于电路板上的可靠度。在一实施例中，尖端208b相对于突出部213的上表面151更接近于基板202的下表面153，尖端308b相对于引脚171的上表面155更接近于引脚171的下表面157。
于其它实施例中，隔开距离148是介于芯片座101的厚度142与/或至少一引脚171的厚度142的大约20％与大约50％之间或介于大约25％与大约45％之间，但并不以此为限。于其它实施例中，隔开距离148亦可以介于厚度142的大约5％与大约75％之间。芯片座101的厚度142可以计算从周围边缘区域114的上表面151至芯片座101的下表面153之间的距离。如果金属镀层116、117配置于芯片座101的表面151、153，厚度142可以计算从金属镀层116的上表面150至金属镀层117的下表面152之间的距离。同理，以引脚171来说，如果金属镀层126、127配置于引脚171的表面155、157，厚度142可以计算从金属镀层126的上表面154至金属镀层127的下表面156之间的距离。在此必须说明的是，许多距离是以金属镀层116、117、126、127的表面作为计算的基准。然而，如果没有金属镀层116、117、126、127的话，上述的这些距离可以以芯片座101的表面151、153或引脚171的表面155、157作为计算的基准来取得近似值。
在一实施例中，芯片座101包括金属镀层116、117的厚度142实质上等于至少一引脚171包括金属镀层126、127的厚度142，此厚度142大约为0.125毫米。在此实施例中，芯片座101与至少一引脚171突出于封装胶体108的下表面160的隔开距离148是介于大约0.025毫米与大约0.0625毫米之间或介于大约0.03毫米与大约0.05毫米之间。同样地，芯片座101的侧表面208的尖端208b实质上与引脚171的侧表面308的尖端308b等高。于其它实施例中，芯片座101的厚度142与/或至少一引脚171的厚度142可以大于或小于0.125毫米。
当隔开距离148在厚度142范围的大约20％与大约55％之间所占的百分比越大时，芯片座101与/或引脚171与封装胶体108的结合力会趋于减少，此时，封装体100由表面黏着技术而接合于一引刷电路板的可靠度会趋于增加。同时，底侧所需的蚀刻时间与蚀刻成本也会相对增加，请参考图6。也就是说，隔开距离148的选择如同一厚度142的一百分比，其可以做为上述这些因素之间取舍的交换程度。
一模盖厚度140可以参考封装胶体108的一上表面164至金属镀层116的上表面150之间的距离。同样地，以引脚171而言，模盖厚度140可以计算封装胶体108的上表面164至金属镀层126的上表面154之间的距离。如果模盖厚度140够大，芯片102与焊线104是可以被封装胶体108包覆于内。在一实施例中，模盖厚度140是介于大约0.4毫米与大约1毫米之间，例如是0.675毫米，虽然模盖厚度140在芯片102与焊线104仍然被封装胶体108包覆于内的情况下还可以更小一点。芯片102可以配置于具有凹穴111的芯片座101的凹穴底部112的中心部112a，请参考图1。或者，芯片102可以配置于基部202的上表面212的中心区域212a，请参考图2。
在图1与图2中，距离206是测量中心部112a(或中心区域212a)相对于金属镀层116的上表面150的一深度。距离204是测量凹陷部112b(或凹陷部212b)相对于金属镀层116的上表面150的一深度。在其它实施例中，距离206是介于距离204的大约55％与大约80％之间，但并不以此为限。在一实施例中，距离206大约是0.065毫米，距离204大约是0.095毫米。距离204与距离206可以大于或小于这些值，只要距离204与距离206在一极限内仍然小于芯片座101的厚度142，例如大约0.01毫米。较佳地，中心部112a(或中心区域212a)与凹陷部112b(或凹陷部212b)是蚀刻后的结果(请参考图5)，而不是利用电镀来形成周围边缘区域114(或中央突出部213)。电镀相对于后续的蚀刻工艺可能需花费成本与消耗更多时间，请参考图5。
当芯片102配置于凹穴底部112(或基部202的上表面212)时，芯片102的上表面会相对于金属镀层116的上表面150下降距离206，此时芯片102的上表面较邻近金属镀层116的上表面150，且金属镀层116的上表面150相对于芯片102的上表面较低，而每一引脚171的金属镀层126的上表面154也相对于芯片102的上表面较低。因此，模盖厚度140可以减小，以使封装体100具有较薄的封装厚度。此外，芯片102的下表面是相对邻近金属镀层117的下表面152。因此，可以提高传导芯片102所产生的热能通过芯片座101的扩散效率。
请再同时参考图1、图2与图3，一高度差146指的是通过中心部112a(或中心区域212a)的最高点的一平面166至封装胶体108的下表面160之间的距离。封装胶体108的下表面160至少大约对应于封装胶体108于凹陷部112b(或凹陷部212b)内的下表面。在本发明的一实施例中，高度差146是介于大约0.02毫米与大约0.04毫米之间，但并不以此为限。在本发明的另一实施例，金属镀层116的上表面150可配置介于距离平面116上方大约0.05毫米与大约0.08毫米之间，但并不以此为限。芯片座101的侧表面208的尖端208b与至少一引脚171的侧表面308的尖端308b可配置于平面116的下方。高度差146与尖端208b、308b相对于平面166的位置可以由蚀刻来控制，例如经由一上侧的蚀刻工艺，请参考图5。
距离144指的是封装胶体108的侧表面162至任何引脚171的侧表面308的最小距离。请参考图1，在图1中所显示的距离144如同从侧表面162至最左侧的外引脚171A的尖端308b的距离。在本发明的一实施例中，距离144是介于大约0.1毫米至大约0.3毫米之间，但本发明并不以此为限。部分的封装胶体108在左边最左侧的外引脚171A(与在右边最右侧的外引脚171B相同)可以避免于分离工艺(singulation)(请参考图6)与使用封装体100时外引脚171A、171B剥落(peeling)或分离的情形。
引脚间隔145指的是介于两相邻的引脚171中心的距离，也是指端子间距(terminal pitch)。在本发明的一实施例中，引脚间隔145是介于大约0.35毫米与0.55毫米之间，但并不以此为限。引脚间隔145可以由蚀刻来控制，例如经由一上侧的蚀刻工艺，请参考图5。
在图3中，一保护层310实质上覆盖至少这些引脚171的一的下倾斜部308a。在此所述的“实质上”一词是指保护层310覆盖至少一引脚171的下倾斜部308a来保护下方的金属以避免受到氧化、湿气以及其它环境条件的影响以符合封装需求。封装胶体108实质上覆盖引脚171的上倾斜部308c(或于尖端308b上方的部分侧表面308)，但是不完全覆盖引脚171的下倾斜部308a(或于尖端308b下方的部分侧表面308)或至少不覆盖引脚171从封装胶体108的下表面160向外延伸的下倾斜部308a。因此，保护层310是除了引脚171的下表面157上的保护的金属镀层127之外，可用来防止或减少下方金属的氧化与腐蚀作用，其中保护层310例如是一铜或一铜合金。类似的保护层也可以应用于芯片座101的下倾斜部208a(或于尖端208b下方的部分侧表面208)。在图2中，一保护层210实质上覆盖芯片座101的下倾斜部208a。保护层210与芯片座101的侧表面153上保护的金属镀层117一同保护芯片座101下方的金属，以符合封装需求。
在一实施例中，保护层210、310可以包括一金属镀层。此金属镀层可以包括至少一锡层、一镍层与一金层。或者，金属镀层可以包括一层二个或多个上述这些金属的合金。金属镀层例如是利用浸没法(immersion)、有电电镀法(electrolytic plating)、无电电镀法(electroless plating)或其它适合的方法而贴附于下倾斜部208a、308a。
在其它实施例中，保护层210、310可以包括一焊接材料。焊接材料可以包括一焊料膏。当保护的金属镀层117、127(无焊料膏)实质上覆盖于芯片座101的下表面153与至少一引脚171的下表面157时，焊料膏可以有选择地配置于下倾斜部208a、308a。在此所述的“实质上”一词是指保护的金属镀层117、127覆盖下表面153、157来保护在下方的金属以避免受到氧化、湿气以及其它环境条件的影响以符合封装需求。保护的金属镀层117、127也可以于蚀刻时保护下方的金属，请参考图5。或者，焊料膏可以同时配置于下倾斜部208a、308a与下表面153、157上。然后，烘干或硬化焊料膏。或者，焊料膏可以经由回焊而硬化成一焊料凸块。
在其它实施例中，保护层210、310可以包括一有机保焊层(organicsolderability preservative layer，OSP layer)。有机保焊层可由浸没法、一以有机材料为主的溶剂的漂洗法或其它适合的方法来贴附于下倾斜部208a、308a。有机材料可以是一以咪唑(imidazole)为主的材料。有机保焊层可以有选择地配置于下倾斜部208a、308a或配置于下倾斜部208a、308a二者择一、芯片座101的下表面153以及至少一引脚171的下表面157。如果有机保焊层配置于下表面153、157上，则去除有机保焊层另外的处理程序也许可以被省去。详细而言，因为当焊接芯片座101与至少一引脚171于一印刷电路板时，焊接时的温度会蒸发有机保焊层。
使用一焊接材料与/或一有机材料作为保护层210、310的一部分，至少有以下两个原因。第一，一般的焊接材料与有机材料相较于金属材料较为便宜，其中金属材料例如是镍、金与锡。第二，焊接材料与有机材料可无须使用有电电镀法或无电电镀法即可以被应用于芯片座101与至少一引脚171上，可简化保护层210、310的制作。
图4为本发明的一实施例的一种金属承载板的一部分的上视图。请参考图4，在本实施例中，金属承载板400的形成方式如图5所描述。金属承载板400包括一基部402，其中基部402具有一从基部402向上延伸的中心突出部404。在此所述的“中心”一词是指突出部404是大约位于部分金属承载板400的中心内，请参考图4。当然，图4中的部分金属承载板400可位于金属承载板400的任何位置，包括金属承载板400的接界边缘。于图4中，虽然中心突出部404是完全地延伸环绕基部402的一周长，但于其它实施例中，中心突出部404可以只有部分地延伸环绕基部402。多个周围突出部406环绕基部402配置。于图4中，虽然周围突出部406实质上完全地环绕基部402，但于其它实施例中，周围突出部406可以只有部分地延伸环绕基部402。一角落周围突出部408位于部分金属承载板400的一角落，且角落周围突出部408可以有不同于周围突出部408的外形与/或尺寸。在一封装体进行表面黏着工艺时，此角落周围突出部408可以作为一公认标记来帮助定位。
金属承载板400中画斜线的部分(404、406与408)是没有被蚀刻，也就是说，突出于金属承载板400的其它部分(包括402)是于上侧蚀刻(请参考图5)时被蚀刻。在一实施例中，周围突出部406配置至少三行在基部402的至少一侧。在下侧蚀刻(请参考图6)之后，基部402与周围突出部406彼此分开且形成芯片座101与引脚171，如同前述图1至图3所述。由于周围突出部406不需要连接至一导线架的一可抛弃部，意即周围突出部406如同一四方扁平无引脚封装(QFN)导线架的框，因此相对于习的四方扁平无引脚封装(QFN)的制作程序而言，利用图5与图6的制作程序可有效达成二行或多行的引脚171的设计。
在一实施例中，于下侧蚀刻(请参考图6)之后，中心突出部404可包括一接地段，其中一芯片(例如芯片102)由焊线(例如焊线104)电性连接至接地段。接地段可以是一包括完整中心突出部404的接地环。于其它实施例中，接地段可以是中心突出部404的一第一部分404a，一电源段可以是中心突出部404的一第二部分404b。在本实施例中，连接至接地段404a的基部402的一第一部分与连接至电源段404b的基部402的一第二部分是电性绝缘。由蚀刻法、分离法或其它适合的方式，例如沿着虚线410，来结构性地分开基部402的第一部分与基部402的第二部分，以达成电性绝缘。
在此必须了解的是，于图4所示的部分金属承载板400亦可以有以下的描述法。举例而言，金属层载板400包括一有一周围边缘区域404的一芯片放置区402。多个周围凸块406环绕芯片放置区402。
图5显示本发明的一实施例的一种金属承载板的工艺。一第一光阻层506形成于一铜板501的一上表面502上，一第二光阻层508形成铜板501的一下表面504上。第一光阻层506与第二光阻层508是利用涂布法、电镀法或其它适合的方法所形成。预先决定或选择部分的第一光阻层506与第二光阻层508来进行曝光与显影工艺，以于铜板501上形成一第一曝光部510与一第二曝光部512。第一光阻层506与第二光阻层508于曝光后所产生光化学反应，可定义为一光罩。
接着，一第一金属镀层514形成于第一曝光部510，一第二金属镀层516形成于第二曝光部512。第一金属镀层514与第二金属镀层516与前述所述的金属镀层116、117、126、127具有相同的特性，在此不再赘述。接着，掀离第一光阻层506与第二光阻层508。之后，铜板501的上表面502没有第一金属镀层514保护的区域518会被蚀刻，以形成金属承载板500。此金属承载板500包括前述所述的中心区域212a、中心突出部213与周围突出部406。或者，蚀刻后可以形成如前述的部分金属承载板500的芯片放置区402与周围凸块406。此种蚀刻操作方式指的是上侧蚀刻。
金属承载板500包括多个内连接部，例如内连接部500a、500b。每一内连接部500a(或500b)包括前述所述的中心区域212a、中心突出部213与周围突出部406。
图6显示本发明的一实施例的一种半导体封装的工艺。请参考图6，一芯片102贴附于一金属承载板500一部分的一中心区域212a(或芯片放置区402)，例如内连接部500a、500b，其中每一芯片102是利用如同前述所说明的一黏着层(未显示)来贴附。接着，每一芯片102由焊线104电性连接至周围突出部406(或周围凸块406)。接着，一封装胶体108形成于每一芯片102与每一周围突出部406上。封装胶体108材料例如是由人造树脂(synthetic resin)的所组成，且由注模成形法所形成，其中注模成形法例如是移转注模成形法(transfer molding)。接着，蚀刻金属承载板500的下表面没有保护的金属镀层516的区域620来分离周围突出部406与中心突出部213，以形成前述所述的引脚171与芯片座101。此种蚀刻操作方式指的是下侧蚀刻。引脚171与芯片座101形成于共享封装胶体108的多个连接封装体中之一，例如连接封装体600a、600b。连接封装体600a、600b可通过分离工艺来彼此分离成封装体100a、100b。分离工艺可由例如锯切处理来形成具有垂直侧表面的封装体100a、100b，请参考图6。
图7显示本发明的一实施例的一种具有多堆叠芯片的半导体封装的工艺。一第一芯片102a贴附于一金属承载板500的一部分的一中心区域212a(或芯片放置区402)，例如内连接部500a、500b，其中每一第一芯片102a是利用如同前述所说明的一黏着层(未显示)来贴附。然后，每一第一芯片102a由焊线104a电性连接至中心突出部213(或周围边缘区域114)至少一部分。在其它实施例中，每一第一芯片102a可以电性连接至一或多个周围突出部406。
接着，一连接层700配置于每一第一芯片102a的上表面。接着，一第二芯片102b由连接层700接合至每一第一芯片102a的上表面。每一第二芯片102b可由焊线104b电性连接至周围突出部406。于其它实施例中，每一第二芯片102b可以电性连接中心突出部213的至少一部份。第二芯片102b所连接的任何周围突出部406或部分中心突出部213是与对应的第一芯片102b所连接的周围突出部406或部分中心突出部213电性绝缘。
接着，封装胶体108形成于每一堆叠的第一芯片102a与第二芯片102b以及周围突出部406上。接着，蚀刻金属承载板500的下表面没有保护的金属镀层516的区域620来分离周围突出部406与中心突出部213，以形成前述所述的引脚171与芯片座101。引脚171与芯片座101形成于共享封装胶体108的多个连接封装体中之一，例如连接封装体600a、600b。连接封装体600a、600b可通过分离工艺来彼此分离成封装体100a、100b。
在一实施例中，连接层700包括一黏着层。黏着层的材质例如是导电黏着材料或非导电黏着材料，其中非导电黏着材料例如是非导电环氧树脂(epoxy)。黏着层可以是液体型态的黏着层或薄膜型态的黏着层，例如是一双面胶。黏着层亦可以是一焊在线薄膜(film-on-wire)型黏着层，此焊在线薄膜型黏着层的特性与薄膜型态黏着层的特性相似，但其厚度比薄膜型态黏着层的厚度较厚。
在一实施例中，第二芯片102b延伸超过第一芯片102a的周围。焊在线薄膜型黏着层的优点在于黏着层的厚度较厚，因此当第二芯片102b贴附于此黏着层时，仍然有间隙可以让焊线104a焊接至第一芯片102a。如果不是使用此焊在线薄膜型黏着层，连接层700除了液体型态的黏着层与/或薄膜型态的黏着层之外还必需包括一间隙。此间隙的目的在于隔开第一芯片102a与第二芯片102b，以使焊线104a可焊接至第一芯片102a。
随着上述工艺的描述，可由将芯片102配置于凹穴底部112(或基部202的上表面212)，而使所形成的封装体100具有较薄的厚度。以图7中的一具有堆叠芯片的封装体100来说，由凹穴111来提供放置的空间而使得封装体100具有较薄的厚度。此外，堆叠的顺序也是很重要的。举例来说，于图7中，第二芯片102b延伸超过凹穴111且部分覆盖于芯片座101的周围边缘区域114上，所以第二芯片102b不能放置于凹穴底部112。然而，第一芯片102a是按一定尺寸制作，所以第一芯片102a可于配置于凹穴底部112。在此实施例中，如果第一芯片102a的高度加上连接层700的高度够大且足够提供间隙于配置在周围边缘区域114上的金属镀层116的上表面150上方与焊线104a上方时，第二芯片102b可以堆叠于第一芯片102a的上表面。
图8显示本发明的一实施例的一种半导体封装进行表面黏着工艺的流程示意图。随着上述工艺的描述，引脚171与芯片座101形成于共享封装胶体108的多个连接封装体中之一，例如连接封装体600a、600b。在本实施例中，一焊料膏802实质上覆盖至少一引脚171的一倾斜蚀刻区域308a，且一金属镀层127的一下表面156配置于此引脚171的下表面157上。接着，固化焊料膏802来定义一焊接接口802，以作为后序表面黏着工艺用。焊料膏802也可以实质上覆盖芯片座101的一倾斜蚀刻区域208a与芯片座101的一金属镀层117的一下表面152。连接封装体600a、600b可通过分离工艺来彼此分离成封装体100a、100b。
就表面黏着型封装体100a而言，焊接接口800、802可以由回焊工艺而形成液化焊料块804、806。接着，一印刷电路板808与液化焊料块804、806相连接，之后，固化液化焊料块804、806。焊接接口800、802于回焊焊料进行表面黏着工艺时具有足够的焊料，因此焊料对所对应覆盖的倾斜蚀刻区域208a与308a而言，如同一保护层。
除了利用焊料作为一保护层之外，图8的表面黏着工艺的其它优点在于：可以由回焊焊接接口800、802来使封装体100a进行表面黏着工艺。焊接接口800、802经由回焊会产生液态的焊料，此液态的焊料会移动于印刷电路板808上来作为封装体100a进行表面黏着工艺用。
图9显示本发明的另一实施例的一种半导体封装进行表面黏着工艺的流程示意图。在此实施例中，首先，提供一无焊接接口800、802的封装体100来作为表面黏着工艺的用。一芯片座101的一倾斜蚀刻区域208a与至少一引脚171的一倾斜蚀刻区域308a可覆盖一保护层，例如是一有机保焊层，此有机保焊层如同前述所述。接着，焊料膏900配置于一准备用来给封装体100进行表面黏着工艺的印刷电路板908上。在封装体100与印刷电路板908相互接近后，先回焊焊料膏900后固化形成焊料块902，以使封装体100贴附于印刷电路板908上。
随着上述工艺的描述，印刷电板908上具有足够的焊料膏900，以便于回焊焊料膏900进行表面黏着工艺时具有足够的焊料，而焊料对所对应覆盖的倾斜蚀刻区域208a与308a而言，如同一保护层。
虽然本发明已以实施例描述如上，然其并非用以限定本发明，本领域技术人员在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围应当以申请的权利要求范围所界定的内容为准。

Claims (17)

1、一种半导体封装，包括：
芯片座，包括：
周围边缘区域，具有上表面，且以凹穴底部定义出凹穴，其中该凹穴底部具有中心部；
上倾斜部，配置邻接于该周围边缘区域的该上表面，且面向远离该凹穴；
下倾斜部，配置邻接于该上倾斜部，且面向远离该凹穴；
多个引脚，围绕该芯片座，其中各该引脚包括：
上表面；
下表面；
上倾斜部，配置邻接于各该引脚的该上表面；
下倾斜部，配置邻接于各该引脚的该下表面；
第一半导体芯片，配置于该凹穴底部的中心部且电性连接至该些引脚；以及
封装胶体，形成于该第一半导体芯片与该些引脚上，以实质上填充于该凹穴且实质上覆盖该芯片座的该上倾斜部与该些引脚的该些上倾斜部，该芯片座的该下倾斜部与该些引脚的该些下倾斜部至少部分从该封装胶体的下表面向外延伸.
2、如权利要求1所述的半导体封装，其中，该周围边缘区域包括配置邻近该周围边缘区域的该上表面且面向该凹穴的上倾斜部。
3、如权利要求1所述的半导体封装，其中，该芯片座的该周围边缘区域包括接地段，该第一半导体芯片电性连接至该接地段。
4、如权利要求3所述的半导体封装，其中，该芯片座的该周围边缘区域包括电源段，该第一半导体芯片电性连接至该电源段，且该电源段与该接地段电性绝缘。
5、如权利要求1所述的半导体封装，包括：
第一金属镀层，配置于该周围边缘区域的该上表面与该些引脚的该些上表面上；以及
第二金属镀层，配置于该芯片座的该下表面与该些引脚的该些下表面上。
6、如权利要求1所述的半导体封装，其中，该凹穴底部包括环绕该中心部的凹陷部。
7、如权利要求1所述的半导体封装，其中，该芯片座的该上倾斜部与该下倾斜部与该些引脚的该些上倾斜部与该些下倾斜部实质上皆具有凹陷的轮廓。
8、如权利要求1所述的半导体封装，其中，包括连接层与第二半导体芯片，该第二半导体芯片通过该连接层接合至该第一半导体芯片的上表面，其中封装胶体形成于该第二半导体芯片上，且该连接层包括黏着层。
9、如权利要求1所述的半导体封装，其中，包括连接层与第二半导体芯片，该第二半导体芯片通过该连接层接合至该第一半导体芯片的上表面，其中该第二半导体芯片延伸至该第一半导体芯片的周围边缘之外。
10、一种半导体封装工艺，包括：
提供金属承载板，该金属承载板包括：
基部，具有上表面与下表面；
中心突出部，具有上表面且从该基部向上延伸，该中心突出部定义该基部的该上表面的中心区域，且该中心区域具有中心部；
多个周围突出部，各该周围突出部具有上表面且从该基部向上延伸，并环绕该中心突出部；
第一金属镀层，形成于该中心突出部的该上表面上与该周围突出部的该上表面上；
第二金属镀层，形成于对应该中心区域下方、该中心突出部下方以及该些周围突出部下方的该金属承载板的该下表面上；
贴附第一半导体芯片于该中心突出部；
电性连接该第一半导体芯片至该些周围突出部至少一第一突出部上；
形成封装胶体于该第一半导体芯片与该些周围突出部上；以及
蚀刻该第二金属镀层之外的该金属承载板的该下表面的区域，以使该些周围突出部与该中心突出部分离而形成多个引脚与芯片座，其中该芯片座包括该中心突出部与该中心区域，各该引脚具有配置邻接各该引脚的下表面的下倾斜部，该芯片座具有配置邻接该芯片座的下表面的下倾斜部，该芯片座的该下倾斜部与各该引脚的该下倾斜部至少部分从该封装胶体的下表面向外延伸。
11、如权利要求10所述的半导体封装工艺，其中，形成该金属承载板的步骤，包括：
提供铜板，该铜板具有上表面与下表面；
涂布第一光阻层于该铜板的该上表面上以及第二光阻层与该铜板的该下表面上；
对该第一光阻层与该第二光阻层进行曝光与显影，以于该铜板的该上表面形成第一曝光部以及于该铜板的该下表面形成第二曝光部；
形成第一金属镀层于该第一曝光部以及第二金属镀层于该第二曝光部；
移除该第一光阻层；
蚀刻该第一金属镀层之外的该铜层的该上表面，以形成该中心区域、该中心突出部与该些周围突出部；以及
移除该第二光阻层。
12、如权利要求10所述的半导体封装工艺，其中，该中心区域具有环绕该中心部的凹陷部。
13、如权利要求10所述的半导体封装工艺，包括：
由连接层贴附第二半导体芯片于该第一半导体芯片的上表面上，该连接层包括间隙与黏着层，其中该第二半导体芯片延伸至该第一半导体芯片的周围边缘之外；以及
电性连接该第二半导体芯片至该些周围突出部至少一第二突出部上，其中该封装胶体形成于该第二半导体芯片上。
14、一种半导体封装，包括：
芯片座，包括：
基部，具有上表面与下表面；
突出部，从该基部向上延伸且配置邻接于该基部的周围边缘，其中该突出部具有上表面；
第一侧表面，延伸介于该突出部的该上表面与该基部的该下表面之间，其中该第一侧表面具有相较于该突出部的该上表面更接近该基部的该下表面的第一尖端；
多个引脚，环绕该芯片座，至少该些引脚之一包含第二尖端的第二侧表面；
第一半导体芯片，配置于该基部的该上表面，且电性连接至该些引脚；
封装胶体，形成于该第一半导体芯片与该些引脚上，以实质上覆盖该基部的该上表面、该第一尖端上方的该第一侧表面的至少一部分与该第二尖端上方的该第二侧表面的至少一部分，使得该第一尖端下方的该第一侧表面的至少一部分与该第二尖端下方的该第二侧表面的至少一部分突出于该封装胶体的下表面。
15、如权利要求14所述的半导体封装，其中，该基板的该上表面包括：
中心区域，该第一半导体芯片配置于该中心区域；以及
凹陷部，环绕该中心区域。
16、如权利要求15所述的半导体封装，其中，该中心区域定义为平面，且该第一尖端配置于该平面的下方。
17、如权利要求14所述的半导体封装，其中，包括连接层与第二半导体芯片，该第二半导体芯片通过该连接层接合至该第一半导体芯片的上表面，其中该第二半导体芯片延伸至该第一半导体芯片的周围边缘之外。
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US20090230526A1 (en) 2009-09-17
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