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TWI419290B - 四方扁平無引腳封裝及其製作方法 - Google Patents

四方扁平無引腳封裝及其製作方法 Download PDF

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TWI419290B
TWI419290B TW099137284A TW99137284A TWI419290B TW I419290 B TWI419290 B TW I419290B TW 099137284 A TW099137284 A TW 099137284A TW 99137284 A TW99137284 A TW 99137284A TW I419290 B TWI419290 B TW I419290B
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quad flat
pins
protective layer
wafer
lead
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TW099137284A
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TW201218339A (en
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Kuang Hsiung Chen
Sheng Ming Wang
Hsiang Ming Feng
Yu Ying Lee
Mei Lin Hsieh
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Advanced Semiconductor Eng
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Priority to TW099137284A priority Critical patent/TWI419290B/zh
Priority to US13/219,981 priority patent/US8592962B2/en
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Description

四方扁平無引腳封裝及其製作方法
本發明是有關於一種四方扁平封裝(Quad Flat Package,QFP)，且特別是有關於一種四方扁平無引腳封裝(Quad Flat Non-leaded package,QFN package)及其製作方法。
半導體封裝技術包含有許多封裝形態，其中屬於四方扁平封裝系列的四方扁平無引腳封裝具有較短的訊號傳遞路徑及相對較快的訊號傳遞速度，因此四方扁平無引腳封裝適用於高頻傳輸(例如射頻頻帶)之晶片封裝，且為低腳位(low pin count)封裝型態的主流之一。
在四方扁平無引腳封裝的製作方法中，先將多個晶片配置於引腳框架(leadframe)上。然後，藉由多條銲線使這些晶片電性連接至引腳框架。之後，藉由封裝膠體來包覆部份引腳框架、這些銲線以及這些晶片。最後，藉由切割(punching)或鋸切(sawing)單體化上述結構而得到多個四方扁平無引腳封裝。
本發明提供一種四方扁平無引腳封裝，其可減少生產成本且具有較佳的製作良率。
本發明提供一種四方扁平無引腳封裝的製作方法，其可減少生產成本且具有較佳的製作良率。
本發明提出一種四方扁平無引腳封裝，其包括一引腳框架、一晶片、一封裝膠體以及一保護層。引腳框架包括一晶片座及多個引腳，其中引腳圍繞晶片座配置，且每一引腳具有一下表面且下表面區分為一接觸區與一非接觸區。晶片配置於引腳框架上，且電性連接至引腳框架。封裝膠體包覆晶片及引腳，且填充於引腳之間，其中封裝膠體暴露出每一引腳的接觸區與非接觸區。保護層覆蓋每一引腳的非接觸區。
本發明提出一種四方扁平無引腳封裝的製作方法，其中製作方法包括下述步驟。提供一四方扁平無引腳封裝體，其中四方扁平無引腳封裝體的一底面具有多個接觸區與多個非接觸區。形成一保護層於非接觸區上，以覆蓋非接觸區。
基於上述，相較於習知透過半蝕刻來定義出引腳之接觸區，本發明之四方扁平無引腳封裝的設計是透過保護層覆蓋每一引腳之下表面的非接觸區來定義出引腳之接觸區。因此，本發明之保護層的設計可有效減少四方扁平無引腳封裝的生產成本且具有較佳的製作良率。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1為本發明之一實施例之一種四方扁平無引腳封裝的剖面示意圖。請參考圖1，在本實施例中，四方扁平無引腳封裝100a包括一引腳框架110、一晶片120、一封裝膠體130以及一保護層140a。
引腳框架110包括一晶片座112及多個引腳114，其中晶片座112是用以承載晶片120，而這些引腳114則是作為與晶片120與外界電性連接之接點使用。具體來說，這些引腳114圍繞晶片座112配置。每一引腳114具有一下表面114a，且下表面114a可區分為一接觸區114a’與一非接觸區114a”。
晶片120配置於引腳框架110的晶片座112上，且電性連接至引腳框架110的晶片座112與這些引腳114，其中晶片120是藉由一黏著層170而固定於晶片座112上。詳細來說，在本實施例中，四方扁平無引腳封裝100a可包括至少一第一銲線150(圖1中僅示意地繪示兩條)與至少一第二銲線160(圖1中僅示意地繪示兩條)，其中這些第一銲線150電性連接晶片120與所對應的引腳114，而這些第二銲線160電性連接晶片120與晶片座112。也就是說，晶片120是透過這些以打線接合技術所形成之第一銲線150與第二銲線160與引腳框架110之這些引腳114與晶片座112電性連接。
封裝膠體130包覆晶片120以及這些引腳114，且填充於這些引腳114之間，其中封裝膠體130暴露出每一引腳114的接觸區114a’與非接觸區114a”。詳細來說，在本實施例中，封裝膠體130與這些引腳114的下表面114a實質上切齊，即封裝膠體130的底面132與這些引腳114的下表面114a實質上共平面。然而，在其他實施例，引腳114的下表面114a亦可突出於封裝膠體130的底面132。
保護層140a覆蓋引腳框架110之每一引腳114的非接觸區114a”。換言之，每一引腳114的接觸區114a’並未被保護層140a所覆蓋，即可作為與外部電路(未繪示)電性連接之接點使用。特別是，在本實施例中，每一引腳114之接觸區114a’與非接觸區114a”的面積可由保護層140a覆蓋每一引腳114之下表面114a的面積來決定。在本實施例中，保護層140a覆蓋每一引腳114之下表面114a的面積約佔引腳114之下表面114a的百分之四十至百分之八十。此外，保護層140a可覆蓋部分填充於這些引腳114之間的封裝膠體130以及晶片座112的一底表面112a，其中保護層140a為一絕緣材料，例如是：環氧樹脂材料(Epoxy)。
簡言之，本實施例之四方扁平無引腳封裝100a的設計是透過保護層140a覆蓋每一引腳114之下表面114a的非接觸區114a”，來定義出引腳114之接觸區114a’。因此，相較於習知透過半蝕刻來定義出引腳之接觸區而言，本實施例之保護層140a的設計可有效減少四方扁平無引腳封裝100a的生產成本且具有較佳的製作良率。
值得一提的是，本發明並不限定保護層140a形態，雖然此處所提及的保護層140a具體化為塊狀圖案，即保護層140a完全覆蓋晶片座112的底表面112a、填充於這些引腳114之間的部分封裝膠體130以及這些引腳114的這些非接觸區114a”，但已知的其他能達到具有降低生產成本且具有較佳製作良率的結構設計，仍屬於本發明可採用的技術方案，不脫離本發明所欲保護的範圍。
舉例來說，圖2A為本發明之一實施例之一種四方扁平無引腳封裝的剖面示意圖。圖2B為圖2A之四方扁平無引腳封裝的仰視示意圖。請同時參考圖2A以及圖2B，在本實施例中，四方扁平無引腳封裝100b的保護層140b亦可具有一開口142，其中開口142暴露出引腳框架110之晶片座112的部分底表面112a。具體來說，本實施例之保護層140b具體化為一環狀圖案，且環狀圖案環繞晶片座112的底表面112a配置。由於保護層140b之開口142暴露出晶片座112的底表面112a，因此晶片120運作時所產生的熱能可直接由底表面112a散逸至外界。如此一來，本實施例之四方扁平無引腳封裝100b可具有較佳的散熱效果，且可以維持晶片120的正常運作。
以下將配合圖3A至圖3G來詳細說明這些四方扁平無引腳封裝100a、100b的製作方法。
圖3A至圖3G以剖面繪示本發明之一實施例之一種四方扁平無引腳封裝的製作方法。請參考圖3A，首先，提供一引腳框架110，其中引腳框架110包括一晶片座112及多個引腳114。在本實施例中，這些引腳114圍繞晶片座112配置。每一引腳114具有一下表面114a，且下表面114a可區分為一接觸區114a’與一非接觸區114a”。
接著，請參考圖3B，固定一晶片120於引腳框架110的晶片座112上，其中晶片120電性連接至引腳框架110的晶片座112與這些引腳114。為了增加晶片120與晶片座112之間的黏著性，更可於固定晶片120至晶片座112上之前，形成一黏著層170於晶片座112上，使晶片120可透過黏著層170而固定於晶片座112上。
接著，請再參考圖3B，進行打線接合，以形成這些第一銲線150以及這些第二銲線160，其中這些第一銲線150用以連接晶片120與所對應的引腳114之間，而這些第二銲線160用以連接於晶片120與晶片座112之間。也就是說，晶片120透過這些第一銲線150以及這些第二銲線160電性連接至引腳框架110的這些引腳114與晶片座112。
接著，請參考圖3C，貼附一膠帶180於晶片座112的一底表面112a以及這些引腳114的下表面114a上，亦即膠帶180覆蓋每一引腳114的接觸區114a’與非接觸區114a”。
接著，請參考圖3D，進行封膠動作(molding)，而形成一封裝膠體130以包覆晶片120、這些引腳114、這些第一銲線150以及這些第二銲線160，且填充於這些引腳114之間。
然後，請參考圖3E，移除膠帶180，以暴露出引腳框架110之晶片座112的底表面112a以及這些引腳114的下表面114a，亦即暴露出每一引腳114的接觸區114a’與非接觸區114a”以及晶片座112的底表面112a。特別是，膠帶180的設置可讓封裝膠體130與這些引腳114的下表面114a實質上切齊，即封裝膠體130的底面與這些引腳114的下表面114a實質上共平面。至此，以完成一四方扁平無引腳封裝體100的製作。
接著，為了增加後續步驟的可靠度，可先對每一引腳114的非接觸區114a”進行一表面化學清潔處理，以清潔這些引腳114的這些非接觸區114a”。同理，亦可對填充於這些引腳114之間的部分封裝膠體130進行一表面氫氧焰清潔處理，以清潔封裝膠體130的底面132。
然後，請參考圖3F，形成一保護層140a於這些引腳114的這些非接觸區114a”上，以覆蓋這些引腳114的這些非接觸區114a”。換言之，保護層140a並未覆蓋這些引腳114的這些接觸區114a’，即可作為與外部電路(未繪示)電性連接之接點使用。特別是，在本實施例中，每一引腳114之接觸區114a’與非接觸區114a”的面積可由保護層140a覆蓋每一引腳114之下表面114a的面積來決定。
此外，本實施例之保護層140a亦可覆蓋部分填充於這些引腳114之間的封裝膠體130以及晶片座112的底表面112a，其中保護層140a為一絕緣材料，例如：環氧樹脂材料(Epoxy)，而形成保護層140a的方法例如是使用噴墨印刷法、網版印刷法、移印印刷法或是其他轉印的方法。
之後，對保護層140a進行一固化處理，以固化保護層140a，其中固化處理包括一紅外光固化(IR curing)。最後，於進行固化處理之後，對封裝膠體130進行一後段烘烤固化(Post Mold Curing,PMC)處理，以固化封裝膠體130。至此，已完成四方扁平無引腳封裝100a的製作方法。
當然，於其他實施例中，請參考圖3G，可形成具有一開口142的保護層140b，其中開口142暴露出引腳框架110之晶片座112的底表面112a，以作為與外界電性連接或散熱用途。
簡言之，由於本實施例是透過保護層140a、140b覆蓋每一引腳114之下表面114a的非接觸區114a”，來定義出引腳114之接觸區114a’。因此，相較於習知透過半蝕刻來定義出引腳之接觸區而言，本實施例之保護層140a、140b的設計可有效減少四方扁平無引腳封裝100a、100b的生產成本且具有較佳的製作良率。再者，由於本實施例之無需採用習知之半蝕刻來形成具有這些接觸區114a’的引腳框架110，因此於進行打線接合時，引腳框架110可提供第一銲線150與第二銲線160較大的支撐力，故可避免打線不良或產生引腳框架110破裂的情形。
綜上所述，由於本發明之四方扁平無引腳封裝的設計，是透過保護層覆蓋每一引腳之下表面的面積，來定義出引腳之接觸區與非接觸區的面積。因此，相較於習知透過半蝕刻來直接形成引腳之接觸區的面積而言，本發明之保護層的設計可有效減少四方扁平無引腳封裝的生產成本且具有較佳的製作良率。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．四方扁平無引腳封裝體
100a、100b．．．四方扁平無引腳封裝
110．．．引腳框架
112．．．晶片座
112a．．．底表面
114．．．引腳
114a．．．下表面
114a’．．．接觸區
114a”．．．非接觸區
120．．．晶片
130．．．封裝膠體
132．．．底面
140a、140b．．．保護層
142．．．開口
150．．．第一銲線
160．．．第二銲線
170．．．黏著層
180．．．膠帶
圖1為本發明之一實施例之一種四方扁平無引腳封裝的剖面示意圖。
圖2A為本發明之一實施例之一種四方扁平無引腳封裝的剖面示意圖。
圖2B為圖2A之四方扁平無引腳封裝的仰視示意圖。
圖3A至圖3G以剖面繪示本發明之一實施例之一種四方扁平無引腳封裝的製作方法。
100a．．．四方扁平無引腳封裝
110．．．引腳框架
112．．．晶片座
112a．．．底表面
114．．．引腳
114a．．．下表面
114a’．．．接觸區
114a”．．．非接觸區
120．．．晶片
130．．．封裝膠體
132．．．底面
140a．．．保護層
150．．．第一銲線
160．．．第二銲線
170．．．黏著層

Claims (15)

  1. 一種四方扁平無引腳封裝，包括：一引腳框架，包括多個引腳，其中各該引腳具有一下表面且該下表面區分為一接觸區與一非接觸區，而該接觸區與該非接觸區位於同一平面上；一晶片，配置於該引腳框架上，且電性連接至該引腳框架；一封裝膠體，包覆該晶片及該些引腳，且填充於該些引腳之間，其中該封裝膠體暴露出各該引腳的該接觸區與該非接觸區；以及一保護層，覆蓋各該引腳的該非接觸區。
  2. 如申請專利範圍第1項所述之四方扁平無引腳封裝，其中該引腳框架更包括一晶片座，該些引腳環繞該晶片座配置，且該晶片位於該晶片座上。
  3. 如申請專利範圍第2項所述之四方扁平無引腳封裝，其中該保護層具有一開口，該開口暴露出該晶片座的一底表面。
  4. 如申請專利範圍第2項所述之四方扁平無引腳封裝，更包括至少一第一銲線與至少一第二銲線，其中該第一銲線電性連接該晶片與所對應的該引腳，而該第二銲線電性連接該晶片與該晶片座。
  5. 如申請專利範圍第1項所述之四方扁平無引腳封裝，其中該保護層更覆蓋部分填充於該些引腳之間的該封裝膠體。
  6. 如申請專利範圍第1項所述之四方扁平無引腳封裝，其中該保護層的材質為絕緣材料。
  7. 如申請專利範圍第1項所述之四方扁平無引腳封裝，其中該保護層的材質為環氧樹脂材料。
  8. 一種四方扁平無引腳封裝的製作方法，包括：提供一四方扁平無引腳封裝體，其中該四方扁平無引腳封裝體的一底面具有多個接觸區與多個非接觸區，而該接觸區與該非接觸區位於同一平面上；以及形成一保護層於該些非接觸區上，以覆蓋該些非接觸區。
  9. 如申請專利範圍第8項所述之四方扁平無引腳封裝的製作方法，其中形成該保護層的方法包括噴墨印刷法、網版印刷法或移印印刷法。
  10. 如申請專利範圍第8項所述之四方扁平無引腳封裝的製作方法，其中該保護層的材質為絕緣材料。
  11. 如申請專利範圍第8項所述之四方扁平無引腳封裝的製作方法，其中該四方扁平無引腳封裝體的形成步驟，包括：提供一引腳框架，該引腳框架包括多個引腳，其中各該引腳具有一下表面且該下表面定義出該接觸區與該非接觸區；固定一晶片於該引腳框架上，其中該晶片電性連接至該引腳框架；以及形成一封裝膠體，以包覆該晶片及該些引腳，且填充 於該些引腳之間，其中該封裝膠體暴露出各該引腳的該接觸區與該非接觸區。
  12. 如申請專利範圍第11項所述之四方扁平無引腳封裝的製作方法，其中該引腳框架更包括一晶片座，該些引腳環繞該晶片座配置，且該晶片位於該晶片座上。
  13. 如申請專利範圍第12項所述之四方扁平無引腳封裝的製作方法，其中該保護層具有一開口，且該開口暴露出該晶片座的一底表面。
  14. 如申請專利範圍第11項所述之四方扁平無引腳封裝的製作方法，更包括：於形成該保護層之前，對各該引腳的該接觸區進行一表面化學清潔處理；於形成該保護層之前，對填充於該些引腳之間的部分該封裝膠體進行一表面氫氧焰清潔處理；以及於形成該保護層之後，對該保護層進行一固化處理。
  15. 如申請專利範圍第14項所述之四方扁平無引腳封裝的製作方法，更包括：於進行該固化處理之後，對該封裝膠體進行一後段烘烤固化處理。
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