JP5195647B2 - リードフレームの製造方法及び半導体装置の製造方法 - Google Patents
リードフレームの製造方法及び半導体装置の製造方法 Download PDFInfo
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- JP5195647B2 JP5195647B2 JP2009131961A JP2009131961A JP5195647B2 JP 5195647 B2 JP5195647 B2 JP 5195647B2 JP 2009131961 A JP2009131961 A JP 2009131961A JP 2009131961 A JP2009131961 A JP 2009131961A JP 5195647 B2 JP5195647 B2 JP 5195647B2
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- lead frame
- manufacturing
- resist film
- convex portion
- metal layer
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- 238000000034 method Methods 0.000 claims description 69
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- 239000010949 copper Substances 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
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- 229910052737 gold Inorganic materials 0.000 description 3
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
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- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- Lead Frames For Integrated Circuits (AREA)
Description
上記製造工程をさらに詳しく説明すると、図23(a)では、まず始めに、金属基板201(以下、リードフレーム201ともいう。)の上にパターニングされた金属層202(以下、メッキ層202ともいう。)を形成する。次に、図23(b)に示すように、金属層202をマスクとしてエッチングする。このエッチングの際には、金属基板201の厚さ方向の途中に保持部203を設けるようにする。そして、図23(c)に示すように、IC(Integrated Circuit)素子204等の電子部品を、金属層202を介して金属基板201の上に搭載し、IC素子204と隣接する金属層202とを金線205等を用いて電気的に接続する(即ち、ワイヤーボンディングする)。
また、その他の先行技術は、例えば特許文献2から特許文献4に開示されている。
ここで、上記2つのウェットエッチングの課題を以下に示す。
図24(a)〜(d)は、メッキ層202をマスクとして用いたウェットエッチングした場合における課題の一例を図示したものである。図に示すように、メッキ層202をマスクとして用いたウェットエッチングの場合には、例えば折れや変形といったメッキ層202の形状不良、またはメッキ層202の外周部202aにおける剛性の低さが課題となる可能性があった。以下、これらの課題を、図を用いて具体的に説明する。
こうした状態において、図24(c)に示すように、外周部202a上にワイヤーボンディングが施されると、図24(d)に示すように、その強度不足に起因して外周部202aの一部分が機械的に破壊され、ワイヤーの結線不良が起こる可能性があった。
そこで、本発明はこのような事情に鑑みてなされたものであって、半導体の製造工程における不良、特にワイヤーボンディングの結線不良、の発生を低減させて、製品の歩留まりと信頼性とを向上させるリードフレーム及びその製造方法、並びに、そのリードフレームを用いた半導体装置及びその製造方法の提供を目的とする。
また、上記リードフレームの製造方法において、前記基板を形成する工程は、金属基板が有する面に前記金属層を形成し、前記金属層をマスクとして前記金属基板をウェットエッチングすることにより、前記凸部を形成する、ことを特徴としても良い。
上記リードフレームの製造方法によれば、レジスト膜をマスクとして金属基板をウェットエッチングし、その後金属層を形成しているので、凸部に含まれる第1の面から突出した部分を有する金属層を形成することができる。さらに、上記リードフレームの製造方法によれば、形成した金属層のうち、凸部に含まれる第1の面から突出した部分を折り曲げているので、下記の半導体装置の製造工程においてワイヤーボンディングを施す際に、金属層の一部分が機械的に破壊される危険性を低減することができる。従って、製品の歩留まり及び信頼性を高めることができるリードフレームを安定して提供することが可能となる。
また、本発明の別の態様に係るリードフレームは、凸部と、前記凸部の第1の面とオーバーラップする第1の部分及び前記第1の部分から延びて前記第1の面とオーバーラップしない第2の部分とを有する金属層と、を備える基板、を含み、前記金属層の前記第2の部分は、前記凸部に含まれる前記第1の面と交わる第2の面とオーバーラップしていることを特徴とするものである。
上記リードフレームによれば、凸部に含まれる第1の面に形成された金属層は突出した部分を含んでいないので、下記の半導体装置の製造工程においてワイヤーボンディングを施す際、前記金属層の一部分が機械的に破壊される危険性を低減することができる。従って、歩留まり及び信頼性を高めた半導体装置を提供することができる。
上記半導体装置によれば、前記のリードフレームが適用できるので、下記の半導体装置の製造工程においてワイヤーボンディングを施す際、凸部に含まれる第1の面に形成された金属層の一部分が機械的に破壊される危険性を低減することができる。従って、歩留まり及び信頼性を高めた半導体装置を提供することができるとともに、低コストで製品を提供することができる。
(1)第一の実施形態
図1(a)〜図16(b)は、本発明の第一の実施形態に係るリードフレーム100の製造方法を示す工程図である。なお、各図の(a)は平面図であり、各図の(b)は断面図である。
第一の実施形態では、第1のリードフレームの製造方法を、図1(a)〜図9(b)を用いて説明する。次いで第2のリードフレームの製造方法を、図10(a)〜図16(b)を用いて説明する。
まず、図1(a)及び(b)に示すように、金属基板11に含まれる第1の面12と、第1の面12とは反対側を向いた第2の面13とにレジスト膜14を塗布する。なお、リードフレーム100の母材(即ち、金属基板11)としては、例えば銅(Cu)材が好適である。さらに、Cu材の場合、その厚みは例えば0.10mmから0.30mmの範囲内である。
そして、図3(a)及び(b)に示すように、露出させた金属基板11の表面にメッキ層15を形成し、その後、図4(a)及び(b)に示すように、第1の面12に残存するレジスト膜14を除去する。このとき、メッキ層15としては、銀(Ag)、ニッケル(Ni)、金(Au)、パラジウム(Pd)層のいずれかの単層で形成されてもよいし、これらを適宜積層させた複数層で形成されてもよい。例えば、ニッケル(Ni)層、パラジウム(Pd)層、金(Au)層からなる複数の層でメッキ層15が形成されてもよい。なお、金属基板11上にメッキ層15を形成する際、電解メッキを用いて形成してもよい。また、メッキ層15を形成する際には、例えば「電着」による方法を用いることができる。なお、「電着」とは、電気分解によって電極表面に物質が付着して生成することを指す。
ウェットエッチングで金属基板11に凹部16を形成した後(つまり、凸部17を形成した後)、この外周部15aに物理的な力を加えることで、この外周部15aを折り曲げる。なお、図6(a)及び(b)は外周部15aの折り曲げ加工前の様子を、また、図7(a)及び(b)は外周部15aの折り曲げ加工後の様子をそれぞれ示したものである。
さらに、液体に限定されず、気体であっても構わない。押し出す物体が気体の場合は、加圧された気体を例えば0.1mm〜1mm程の小さい穴などを通して押し出すことで得られる細い気流を用いることで折り曲げ加工を実施することができる。また、押し出す物体の温度を高めることで、効果的に折り曲げ加工を実施することができる。
さらに、上記の方法に加えて、例えば外周部15aに「熱」を加えることで外周部15aを折り曲げることもできる。ここで、リードフレーム100の母材としてCu材を、メッキ層15としてAgをそれぞれ選択した場合について考える。各金属の融点に着目すると、Cuの融点は1357.6Kであるのに対して、Agの融点は1234.9Kである。このため、加熱温度を調節することで、メッキ層15に含まれる外周部15aを折り曲げることもできる。
最後に、図9(a)及び(b)に示すように、露出させた金属基板11にメッキ層15を形成し、その後、第2の面13に残存するレジスト膜14を除去する。なお、図9(a)及び(b)に示したメッキ層15を設ける工程は、例えば図3及び図4に示した工程と同様にしてもよい。
また、外周部15aの折り曲げ工程を、ウォータージェットやサンドブラスト等の方法を用いて実施することで、メッキ層15表面上に残存していた汚染物質も取り除くことができるので、メッキ層15表面自体の改質も行うことができる。なお、汚染物質とは、例えばメッキ層15形成工程において、メッキ層15表面に付着した物質等を指す。
次に、第2のリードフレームの製造法について説明する。
まず、図10(a)及び(b)に示すように、金属基板11に含まれる第1の面12と、第1の面12とは反対側を向いた第2の面13とに第1のレジスト膜14を塗布する。次に、第1の面12に塗布された第1のレジスト膜14をパターニングして、第1のレジスト膜14下から金属基板11の一部分(つまり、第1の面12の一部分)を露出させる。
従来技術では、エッチングした箇所に高い正確性で、再びレジスト膜を塗布することが困難となる場合が多かったが、本発明では、第2のレジスト膜19の塗布工程後、図13(a)及び(b)に示すように、凸部17に含まれる第1の面12上にメッキ層15を形成する。なお、この工程で形成するメッキ層15は、凸部17に含まれる第1の面12の面積よりも大きな面積を有するものとし、さらに、凸部17に含まれる第1の面12の全域を覆うようにするものとする。なお、このメッキ層15の材料、形成方法については、図3(a)及び(b)の工程で説明した内容を用いることができる。
以降の工程(即ち、第2の面13にメッキ層15を形成する工程)は、例えば図8及び図9に示した工程と同様にしても良い。前記図8及び図9の工程を経ることで、第2の面13にメッキ層15を形成することができる。そのため、図16(a)及び(b)に示すリードフレーム100を形成することができる。
また、第2のリードフレームの製造法においても、第1のリードフレームの製造法と同様に、外周部15aの折り曲げ工程において、ウォータージェットやサンドブラスト等の方法を用いることで、メッキ層15表面上に残存する汚染物質も取り除くことができる。このため、メッキ層15表面自体の改質も行うことができる。
さらに、形成した複数の凸部17を、平面視で縦方向及び横方向に並ぶように形成しても良い。
さらに、形成した複数の凸部17を、一定の距離を隔てて並ぶように形成しても良い。
さらに、形成した複数の凸部17を、同一の形状、同一の大きさになるように形成しても良い。
図18(a)〜図21(b)は、第二の実施形態に係る半導体装置の製造方法を示す工程図である。まず初めに、図18(a)及び(b)に示すように、第一の実施形態において説明したリードフレーム100(即ち、第1または第2のリードフレームの製造法により製造されたリードフレーム100)に含まれる凸部17に形成されたメッキ層15上に、認識マーク20を設ける。この認識マーク20を設ける場所に関しては、製造する機種に応じて、所望の位置に配置することができる。なお、この認識マーク20を設けるための方法は、例えばインクジェット工法、印刷工法、ディスペンス工法、レーザーマーク工法等を用いることができる。
ダイアタッチ工程後、IC素子21の電極(即ち、パット端子)と、メッキ層15が形成された凸部17bとを、例えば金線等の線材22を用いて電気的に接続する(即ち、ワイヤーボンディング工程)。線材22の材料としては、金の他、アルミニウムや銅などを用いても良い。
最後に、図21(a)及び(b)に示すように、第2の面13の側から連結部18をエッチングして樹脂24を露出させる(即ち、裏面貫通エッチング工程)。これにより、図21(b)に示すように、ワイヤーボンディングされた凸部17bは、他のワイヤーボンディングされていない凸部、例えばIC素子21が搭載された凸部17aと電気的に分離される。
つまり、半導体装置200は、例えば第一の実施形態により製造されたリードフレームに設けられた凸部17と、凸部17を、第1の凸部17aまたは第2の凸部17bとした場合、 第1の凸部17aに含まれる第1の面12に、金属層15を介して固定されたIC素子21と、第2の凸部17bに含まれる第1の面12に形成された金属層15と、IC素子21のパッド端子とを電気的に接続した金線22と、IC素子21及び金線22と、複数の凸部17に含まれる第1の面12側の部位の一部とを封止した樹脂と、を含むものである。
なお、第一及び第二の実施形態における「外周部15a」は本発明の「第2の部分」に対応し、メッキ層15に含まれる部分であって「外周部15a」以外の場所は本発明の「第1の部分」に対応する。さらに、第一及び第二の実施形態における凸部17の側面16aは本発明の「第2の面」に対応する。
Claims (2)
- 凸部と、前記凸部の第1の面とオーバーラップする第1の部分及び前記第1の部分から延びて前記第1の面とオーバーラップしない第2の部分とを有する金属層と、を備える基板を形成する工程と、
前記金属層の前記第2の部分が、前記第1の面と交わる前記凸部の第2の面とオーバー
ラップするように、前記金属層を折り曲げる工程と、
を含み、
前記基板を形成する工程は、
金属基板が有する面に第1のレジスト膜を塗布し、
前記第1のレジスト膜をマスクとして、前記金属基板をウェットエッチングし、
前記ウェットエッチング後に、前記第1のレジスト膜を除去し、
前記第1のレジスト膜を除去した後に、前記ウェットエッチングで形成された凹部に第
2のレジスト膜を塗布し、
前記第2のレジスト膜を塗布した後に、前記第2のレジスト膜から露出している前記金
属基板上に前記金属層を形成し、
前記金属層を形成した後に、前記第2のレジスト膜を除去する、ことを特徴とするリードフレームの製造方法。
- 凸部と、前記凸部の第1の面とオーバーラップする第1の部分及び前記第1の部分から延びて前記第1の面とオーバーラップしない第2の部分とを有する金属層と、を備える基板を形成する工程と、
前記金属層の前記第2の部分が、前記第1の面と交わる前記凸部の第2の面とオーバー
ラップするように、前記金属層を折り曲げる工程と、
前記基板に、電極を有するIC素子を固定する工程と、
前記金属層と、前記電極とを、導電部材を用いて接続する工程と、
前記IC素子及び前記導電部材を、樹脂を用いて封止する工程と、を含むことを特徴と
する半導体装置の製造方法。
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US7807498B2 (en) | 2007-07-31 | 2010-10-05 | Seiko Epson Corporation | Substrate, substrate fabrication, semiconductor device, and semiconductor device fabrication |
JP4483969B2 (ja) | 2008-03-31 | 2010-06-16 | セイコーエプソン株式会社 | 基板及びその製造方法、半導体装置の製造方法 |
JP4821803B2 (ja) | 2008-05-23 | 2011-11-24 | セイコーエプソン株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2009302095A (ja) | 2008-06-10 | 2009-12-24 | Seiko Epson Corp | 半導体装置及び半導体装置の製造方法 |
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US20100301465A1 (en) | 2010-12-02 |
US8125062B2 (en) | 2012-02-28 |
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