Chisel: A Modern Hardware Design Language

Rocket Chip Generator

SonicBOOM: The Berkeley Out-of-Order Machine

Scala based HDL

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Simple RISC-V 3-stage Pipeline in Chisel

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

A Chisel RTL generator for network-on-chip interconnects

SoC based on VexRiscv and ICE40 UP5K

high-performance RTL simulator

[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning

SpinalHDL - Cryptography libraries

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

🌳 A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

Chisel Things for OFDM

Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program

Chisel library for Unum Type-III Posit Arithmetic

Quasar 2.0: Chisel equivalent of SweRV-EL2

BOOM's Simulation Accelerator.

A 32-bit CPU being developed in SpinalHDL