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117 Open 619 Closed
117 Open 619 Closed
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Issues list

simPublic() doesn't work when using XSim backend feature ✨ Feature idea with clear API defined
#1583 opened Oct 30, 2024 by Pyromuffin
2
Empty module name in generated verilog
#1582 opened Oct 29, 2024 by petrmikheev
3
DfiControllerTester randomly fail
#1579 opened Oct 28, 2024 by Dolu1990
1
4
Failed to run simulation using verilator on Windows
#1572 opened Oct 22, 2024 by du33169
6
Verilog of blackbox with inout mapped to tristate port renaming issue
#1570 opened Oct 15, 2024 by louiecaulfield
3
Master/Slave property of TriStateArray don't propagate to TriState elements
#1569 opened Oct 15, 2024 by louiecaulfield
SpinalHDL's test with cocotb could be failed while using cocotb 1.9.0 and later.
#1568 opened Oct 15, 2024 by Readon
9
PackedBundle inside Union?
#1534 opened Sep 11, 2024 by KireinaHoro
13
Outer FSM whenIsActive statements always win vs. nested FSM onEntry statements for combinational logic
#1528 opened Sep 7, 2024 by thajohns
1
2
regif's html doc not support setname function
#1523 opened Sep 5, 2024 by laodao01
Add support for AMBA5 CHI？
#1513 opened Aug 24, 2024 by tanhongze
1
Assign bits (BigInt) back to Bundle/Union/Enum in SpinalSim
#1510 opened Aug 21, 2024 by KireinaHoro
8
XSim in spinalhdl fail to simulate IPs like FFT or complex multiplier, but works fine in Vivado
#1509 opened Aug 20, 2024 by aureoleday
4
switch SInt support
#1499 opened Aug 2, 2024 by DoubiZhizun
SystemVerilog Generation
#1497 opened Aug 1, 2024 by digee-bytes
Running doSim more than once causes an error and will hang Verilator simulation indefinitely
#1483 opened Jul 16, 2024 by rpls
3
file miss
#1481 opened Jul 12, 2024 by ICJJ
2
[feature request] Option to use SystemVerilog unpacked arrays for Vecs in IO ports
#1478 opened Jul 11, 2024 by thajohns
1
Observations about AFix
#1476 opened Jul 11, 2024 by thajohns
3
Possible pull request: PipelinedMemoryBusToApbBridge for APB4
#1469 opened Jun 28, 2024 by juliaazziz
1
testbench of USB device
#1467 opened Jun 25, 2024 by Mina-Lrh
6
formal: GlobalClock() produces invalid VHDL
#1463 opened Jun 21, 2024 by NikLeberg
6
AhbLite3OnChipRam (and Rom) do not support aligned access less than word size
#1449 opened Jun 11, 2024 by robotman2412
Support for AMBA ACE4
#1445 opened Jun 10, 2024 by KireinaHoro
9
Could you please advise if there is any method to generate a port in the format of [lsb:msb]?
#1431 opened Jun 2, 2024 by hhucchenyixiao
6
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