Network on Chip Simulator
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Updated
Jan 22, 2024 - C++
Network on Chip Simulator
A Chisel RTL generator for network-on-chip interconnects
Network on Chip Implementation written in SytemVerilog
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
Official read only mirror for
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
HLS for Networks-on-Chip
cycle accurate Network-on-Chip Simulator
System-on-Chip Interconnection Network - Simulation Environment (front-end)
Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research
External Network Operations Center for EPFL SI ISAS-FSD
Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
experiments in the vector field
Python modules/classes for easy analysis of Network on Chips
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