An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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Updated
Aug 26, 2024 - Scala
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
BOOM's Simulation Accelerator.
This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.
A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs
An online viewer for Chipyard output files
This Github repository serves as a User Guide (UG) for new Chipyard users.
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