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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 3.9k 583

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.1k 1.1k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.3k 198

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 989 322

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 799 217

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 716 176

Repositories

Showing 10 of 104 repositories
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 107 Apache-2.0 21 15 17 Updated Aug 26, 2024
  • rvdecoderdb Public

    The Scala parser to parse riscv/riscv-opcodes generate

    chipsalliance/rvdecoderdb’s past year of commit activity
    Scala 5 0 0 1 Updated Aug 26, 2024
  • synlig-logs Public
    chipsalliance/synlig-logs’s past year of commit activity
    0 0 0 0 Updated Aug 26, 2024
  • synlig Public

    SystemVerilog support for Yosys

    chipsalliance/synlig’s past year of commit activity
    Verilog 151 Apache-2.0 20 64 8 Updated Aug 26, 2024
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 1 0 0 Updated Aug 26, 2024
  • VeeRwolf Public

    FuseSoC-based SoC for VeeR EH1 and EL2

    chipsalliance/VeeRwolf’s past year of commit activity
    Verilog 275 64 21 0 Updated Aug 24, 2024
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 50 Apache-2.0 37 75 47 Updated Aug 24, 2024
  • verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    chipsalliance/verible’s past year of commit activity
    C++ 1,296 198 462 (15 issues need help) 27 Updated Aug 24, 2024
  • firrtl-spec Public

    The specification for the FIRRTL language

    chipsalliance/firrtl-spec’s past year of commit activity
    TeX 37 27 23 17 Updated Aug 24, 2024
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 3,880 Apache-2.0 583 309 (1 issue needs help) 152 Updated Aug 24, 2024
View all repositories