rtl

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

Updated Sep 15, 2023
Verilog

seldridge / verilog

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Repository for basic (and not so basic) Verilog blocks with high re-use potential

fpga hardware rtl verilog

Updated Mar 15, 2018
Verilog

The-OpenROAD-Project / OpenROAD-flow-scripts

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OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Aug 26, 2024
Verilog

lastweek / fpga_readings

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Recipe for FPGA cooking

fpga hls rtl verilog xilinx vivado-hls

Updated Jul 14, 2021
Verilog

WangXuan95 / FPGA-ftdi245fifo

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FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

fpga usb rtl verilog systemverilog ft232h ipcore ft601 ft600

Updated May 21, 2024
Verilog

WangXuan95 / FPGA-SDcard-Reader

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An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

fpga rtl verilog file-system systemverilog sd-card sdcard sdio

Updated Sep 14, 2023
Verilog

openasic-org / xkISP

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xkISP：Xinkai ISP IP Core (HLS)

fpga hls rtl isp

Updated Mar 14, 2023
Verilog

WangXuan95 / FPGA-CAN

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An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

fpga controller rtl can verilog systemverilog can-bus control-area-network

Updated Sep 15, 2023
Verilog

WangXuan95 / FPGA-JPEG-LS-encoder

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An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

fpga rtl verilog image-compression systemverilog image-encoder jpeg-ls jpegls jls

Updated Nov 13, 2023
Verilog

KASIRGA-KIZIL / tekno-kizil

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KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

asic cpu fpga processor llvm verification clang riscv rtl verilog computer-architecture pipeline-processor in-order risc-v coremark rv32imc teknofest openlane

Updated Jul 20, 2023
Verilog

WangXuan95 / FPGA-DDR-SDRAM

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An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

fpga controller rtl verilog soft-core axi4 ddr-sdram ddr1

Updated Sep 15, 2023
Verilog

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

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IC implementation of Systolic Array for TPU

asic fpga rtl verilog asic-verification asic-design

Updated Mar 4, 2024
Verilog

WangXuan95 / FPGA-FixedPoint

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A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

pipeline rtl arithmetic verilog systemverilog fixedpoint