SN54HC148, SN74HC148

SCLS109H – APRIL 2004 – REVISED MARCH 2022

SNx4HC148 8-Line to 3-Line Priority Encoders

1 Features 3 Description
• Wide operating voltage range of 2V to 6V The SNx4HC148 is an 8-input priority encoder. Added
• Outputs can drive up to 10 LSTTL loads input enable (EI) and output enable (EO) signals allow
• Low power consumption, 80-μA max ICC for cascading multiple stages without added external
• Typical tpd = 16ns circuitry.
• ±4-mA output drive at 5V (1)
Device Information
• Low input current of 1μA max
PART NUMBER PACKAGE BODY SIZE (NOM)
• Encode eight data lines to 3-line binary (Octal)
SN74HC148D SOIC (16) 9.90 mm × 3.90 mm
2 Applications SN74HC148N PDIP (16) 19.31 mm × 6.35 mm
• N-Bit encoding SN74HC148NS SO (16) 10.20 mm × 5.30 mm
• Code converters and generators SN54HC148J CDIP (16) 21.34 mm × 6.92 mm
SNJ54HC148FK LCCC (20) 8.89 mm × 8.45 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC148, SN74HC148
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Table of Contents
1 Features............................................................................1 8.2 Functional Block Diagram........................................... 8
2 Applications..................................................................... 1 8.3 Device Functional Modes............................................9
3 Description.......................................................................1 9 Application Information................................................ 10
4 Revision History.............................................................. 2 10 Power Supply Recommendations..............................11
5 Pin Configuration and Functions...................................3 11 Layout........................................................................... 11
6 Specifications.................................................................. 4 11.1 Layout Guidelines....................................................11
6.1 Absolute Maximum Ratings........................................ 4 12 Device and Documentation Support..........................12
(1)
6.2 Recommended Operating Conditions ..................... 4 12.1 Documentation Support.......................................... 12
6.3 Thermal Information....................................................4 12.2 Receiving Notification of Documentation Updates..12
6.4 Electrical Characteristics.............................................5 12.3 Support Resources................................................. 12
6.5 Switching Characteristics ...........................................5 12.4 Trademarks............................................................. 12
6.6 Operating Characteristics........................................... 6 12.5 Electrostatic Discharge Caution..............................12
7 Parameter Measurement Information............................ 7 12.6 Glossary..................................................................12
8 Detailed Description........................................................8 13 Mechanical, Packaging, and Orderable
8.1 Overview..................................................................... 8 Information.................................................................... 12

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (April 2004) to Revision H (March 2022) Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern datasheet standards.............................................................................................................................. 1

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5 Pin Configuration and Functions

J, D, N or NS Package
16-Pin CDIP, SOIC, PDIP, SO
Top View FK Package
20-Pin LCCC
Top View

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6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range -0.5 7 V
IIK Input clamp current (VI < 0 or VI > VCC )(2) ±20 mA
IOK Output clamp current (VO < 0 or VO > VCC)(2) ±20 mA
IO Continuous output current (VO = 0 to VCC) ±25 mA
VCC or GND Continuous current through ±50 mA
TJ Junction temperature 150 °C
Tstg Storage temperature -65 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

(1)
6.2 Recommended Operating Conditions
SN54HC148 SN74HC148
UNIT
MIN NOM MIN NOM MAX
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2V 1.5 1.5
VIH High-level input voltage VCC = 4.5V 3.15 3.15 V
VCC = 6V 4.2 4.2
VCC = 2V 0.5 0.5
VIL Low-level input voltage VCC = 4.5V 1.35 1.35 V
VCC = 6V 1.8 1.8
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
VCC = 2V 1000 1000
Δt/ΔVCC Input transition rise/fall time VCC = 4.5V 500 500 ns
VCC = 6V 400 400
TA Operating free-air temperature -55 125 -40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating SMOS Inputs, literature number SCBA004.

6.3 Thermal Information

D (SOIC) DW (SOIC) N (PDIP) NS (SO)
THERMAL METRIC 16 PINS 16 PINS 16 PINS 16 PINS UNIT
R θJA Junction-to-ambient thermal
73 57 67 64 °C/W
resistance(1)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

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6.4 Electrical Characteristics

TA = 25°C SN54HC148 SN74HC148
PARAMETER TEST CONDITIONS(1) VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2 1.9 1.998 1.9 1.9
IOH = – 20 μA 4.5 4.4 4.499 4.4 4.4
VOH High-level output voltage 6 5.9 5.999 5.9 5.9 V
IOH = – 4 mA 4.5 3.98 4.3 3.7 3.84
IOH = – 5.2 mA 6 5.48 5.8 5.2 5.34
2 0.002 0.1 0.1 0.1
IOL = 20 μA 4.5 0.001 0.1 0.1 0.1
VOL Low-level output voltage 6 0.001 0.1 0.1 0.1 V
IOL = 4 mA 4.5 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 0.15 0.26 0.4 0.33
II Input hold current VI = VCC or 0 6 ±0.1 ±100 ±1000 ±1000 nA
ICC Supply current VI = VCC or 0. IO = 0 6 8 160 80 μA
Ci Input capacitance 2 to 6 3 10 10 10 pF

(1) VI = VIH or VIL, unless otherwise noted.

6.5 Switching Characteristics

CL = 50pF, unless otherwise specified. See (Parameter Measurement Information)
FROM TO TA = 25°C SN54HC148 SN74HC148
PARAMETER (OUTPUT) VCC UNIT
(INPUT) MIN TYP MAX MIN MAX MIN MAX
2 69 180 270 225
1-7 A0, A1, A2 4.5 23 36 54 45
6 21 31 46 38
2 60 150 225 190
EO 4.5 20 30 45 38
6 17 26 38 33
0-7
2 75 190 285 240
GS 4.5 25 38 57 48
6 21 32 48 41
tpd Propagation Dealy ns
2 78 195 295 245
A0, A1, A2 4.5 26 39 59 49
6 22 33 50 42
2 57 145 220 180
EI GS 4.5 19 29 44 36
6 16 25 38 31
2 66 165 250 205
EO 4.5 22 33 50 41
6 19 28 43 35
2 28 75 110 95
tt Transition time Any 4.5 8 15 22 19 ns
6 6 13 19 16

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6.6 Operating Characteristics

TA = 25°C
Test Conditions TYP UNIT
Cpd Power dissipation capacitance No load 35 pF

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7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.

Test
Point

From Output
Under Test
CL(1)

(1) CL includes probe and test-fixture capacitance.

Figure 7-1. Load Circuit for Push-Pull Outputs

VCC VCC
90% 90%
Input 50% 50% Input
10% 10%
0V 0V
(1) (1)
tr(1) tf(1)
tPLH tPHL
VOH VOH
90% 90%
Output 50% 50% Output
10% 10%
VOL VOL
tr(1) tf(1)
tPHL(1) tPLH(1)
(1) The greater between tr and tf is the same as tt.
VOH
Figure 7-3. Voltage Waveforms, Input and Output
Output 50% 50% Transition Times for Standard CMOS Inputs
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-2. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs

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8 Detailed Description
8.1 Overview
The ’HC148 devices feature priority decoding of the inputs to ensure that only the highest-order data line is
encoded. These devices encode eight data lines to 3-line (4-2-1) binary (octal). Cascading circuitry (enable input
EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry.
Data inputs and outputs are active at the low logic level.
8.2 Functional Block Diagram

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8.3 Device Functional Modes

Table 8-1. Function Table
INPUTS OUTPUTS
EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO
H X X X X X X X X H H H H H
L H H H H H H H H H H H H L
L X X X X X X X L L L L L H
L X X X X X X L H L L H L H
L X X X X X L H H L H L L H
L X X X X L H H H L H H L H
L X X X L H H H H H L L L H
L X X L H H H H H H L H L H
L X L H H H H H H H H L L H
L L H H H H H H H H H H L H

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9 Application Information

Figure 9-1. Priority Encoder for 16 Bits

Because the ’HC148 devices are combinational logic circuits, wrong addresses can appear during input
transients. Moreover, a change from high to low at EI can cause a transient low on GS when all inputs are
high. This must be considered when strobing the outputs.

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.

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12 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN54HC148J ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54HC148J Samples
& Green
SN74HC148DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC148 Samples

SN74HC148DRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 Samples

SN74HC148DRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 Samples

SN74HC148N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC148N Samples

SN74HC148NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC148 Samples

SNJ54HC148FK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SNJ54HC Samples
& Green 148FK
SNJ54HC148J ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SNJ54HC148J Samples
& Green

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2024

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC148, SN74HC148 :

• Catalog : SN74HC148
• Military : SN54HC148

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Apr-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC148DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC148DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC148NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74HC148NSR SO NS 16 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Apr-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC148DR SOIC D 16 2500 356.0 356.0 35.0
SN74HC148DRG4 SOIC D 16 2500 340.5 336.1 32.0
SN74HC148NSR SO NS 16 2000 356.0 356.0 35.0
SN74HC148NSR SO NS 16 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Apr-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74HC148N N PDIP 16 25 506 13.97 11230 4.32
SN74HC148N N PDIP 16 25 506 13.97 11230 4.32
SNJ54HC148FK FK LCCC 20 55 506.98 12.06 2030 NA

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

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 PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP

8.2 SEATING PLANE

TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1

10.4 2X
10.0 8.89
NOTE 3

8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4

0.15 TYP

SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1

0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

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 EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP

(7)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP (7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

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