CD74HCT14, CD54HCT14

SCHS402 – AUGUST 2019 – REVISED JUNE 2021

CDx4HCT14 Hex Inverters with Schmitt-Trigger Inputs

1 Features 3 Description
• LSTTL input logic compatible This device contains six independent inverters
– VIL(max) = 0.8 V, VIH(min) = 2 V with Schmitt-trigger inputs. Each gate performs the
• CMOS input logic compatible Boolean function Y = A in positive logic.
– II ≤ 1 µA at VOL, VOH Device Information(1)
• Buffered inputs PART NUMBER PACKAGE BODY SIZE (NOM)
• 4.5 V to 5.5 V operation
CD74HCT14M SOIC (14) 8.70 mm × 3.90 mm
• Wide operating temperature range:
CD74HCT14E PDIP (14) 19.30 mm × 6.40 mm
-55°C to +125°C
• Supports fanout up to 10 LSTTL loads CD74HCT14PW TSSOP (14) 5.00 mm × 4.40 mm
• Significant power reduction compared to LSTTL CD54HCT14F CDIP (14) 21.30 mm × 7.60 mm
logic ICs
(1) For all available packages, see the orderable addendum at
2 Applications the end of the data sheet.

• Synchronize inverted clock inputs

• Debounce a switch
• Invert a digital signal
1A 1 14 VCC
1Y 2 13 6A
2A 3 12 6Y
4 11
2Y 5A
3A 5 10 5Y
3Y 6 9 4A
7 8
GND 4Y

Functional pinout

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.3 Feature Description.....................................................8
2 Applications..................................................................... 1 8.4 Device Functional Modes............................................9
3 Description.......................................................................1 9 Application and Implementation.................................. 10
4 Revision History.............................................................. 2 9.1 Application Information............................................. 10
5 Pin Configuration and Functions...................................3 9.2 Typical Application.................................................... 10
Pin Functions.................................................................... 3 10 Power Supply Recommendations..............................12
6 Specifications.................................................................. 4 11 Layout........................................................................... 13
6.1 Absolute Maximum Ratings........................................ 4 11.1 Layout Guidelines................................................... 13
6.2 Recommended Operating Conditions.........................4 11.2 Layout Example...................................................... 13
6.3 Thermal Information....................................................4 12 Device and Documentation Support..........................14
6.4 Electrical Characteristics.............................................5 12.1 Documentation Support.......................................... 14
6.5 Switching Characteristics............................................5 12.2 Support Resources................................................. 14
6.6 Operating Characteristics........................................... 5 12.3 Trademarks............................................................. 14
6.7 Typical Characteristics................................................ 5 12.4 Electrostatic Discharge Caution..............................14
7 Parameter Measurement Information............................ 7 12.5 Glossary..................................................................14
8 Detailed Description........................................................8 13 Mechanical, Packaging, and Orderable
8.1 Overview..................................................................... 8 Information.................................................................... 14
8.2 Functional Block Diagram........................................... 8

4 Revision History
DATE REVISION NOTES
Initial release. Moved the HCT devices from
June 2020 *
the SCHS129 to a standalone data sheet.

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5 Pin Configuration and Functions

1A 1 14 VCC
1Y 2 13 6A
2A 3 12 6Y
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
GND 7 8 4Y

Figure 5-1. D, N, PW, or J Package 14-Pin SOIC, PDIP, TSSOP, or CDIP Top View

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
1A 1 Input Channel 1, Input A
1Y 2 Output Channel 1, Output Y
2A 3 Input Channel 2, Input A
2Y 4 Output Channel 2, Output Y
3A 5 Input Channel 3, Input A
3Y 6 Output Channel 3, Output Y
GND 7 — Ground
4Y 8 Output Channel 4, Output Y
4A 9 Input Channel 4, Input A
5Y 10 Output Channel 5, Output Y
5A 11 Input Channel 5, Input A
6Y 12 Output Channel 6, Output Y
6A 13 Input Channel 6, Input A
VCC 14 — Positive Supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
VI < –0.5 V or VI > VCC +
IIK Input clamp current(2) ±20 mA
0.5 V
VO < –0.5 V or VO > VCC +
IOK Output clamp current(2) ±20 mA
0.5 V
VO > –0.5 V or VO < VCC +
IO Continuous output current ±25 mA
0.5 V
Continuous current through VCC or GND ±50 mA
Plastic package 150
TJ Junction temperature(3) °C
Hermetic package or die 175
Lead temperature (soldering 10s) SOIC - lead tips only 300 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.

6.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 V
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 4.5 V 500
tt Input transition time ns
VCC = 5.5 V 400
TA Operating free-air temperature –55 125 °C

6.3 Thermal Information

CD74HCT14
THERMAL METRIC(1) N (PDIP) D (SOIC) PW (TSSOP) UNIT
14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 62.9 95.5 119.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50.7 49.9 42.5 °C/W
RθJB Junction-to-board thermal resistance 42.7 51.7 64.5 °C/W
Junction-to-top characterization
ΨJT 30.3 12.8 4.5 °C/W
parameter
Junction-to-board characterization
ΨJB 42.4 51.3 63.7 °C/W
parameter
Junction-to-case (bottom) thermal
RθJC(bot) N/A N/A N/A °C/W
resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.4 Electrical Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Positive 4.5 V 1.2 1.9 1.2 1.9 1.2 1.9
V
VT+ switching
threshold 5.5 V 1.4 2.1 1.4 2.1 1.4 2.1

Negative 4.5 V 0.5 1.2 0.5 1.2 0.5 1.2

VT- switching V
threshold 5.5 V 0.6 1.4 0.6 1.4 0.6 1.4

Hysteresis (VT+ 4.5 V 0.4 1.4 0.4 1.4 0.4 1.4

ΔVT V
- VT-) 5.5 V 0.4 1.5 0.4 1.5 0.4 1.5
IOH = –20
4.5 V 4.4 4.4 4.4
High-level VI = VIH or µA
VOH V
output voltage VIL IOH = –4
4.5 V 3.98 3.84 3.7
mA
IOL = 20
Low-level output VI = VIH or µA 4.5 V 0.1 0.1 0.1
VOL V
voltage VIL
IOL = 4 mA 4.5 V 0.26 0.33 0.4
Input leakage VI = VCC
II IO = 0 5.5 V ±0.1 ±1 ±1 µA
current and GND
VI = VCC or
ICC Supply current IO = 0 5.5 V 2 20 40 µA
GND
Additional
4.5 V
ΔICC Quiescent VI = VCC –
(1) to 5.5 360 450 490 µA
Device Current 2.1
V
Per Input Pin.
Input
Ci 5V 10 10 10 pF
capacitance

(1) For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.

6.5 Switching Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
TEST
PARAMETER FROM TO CONDITIO VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
NS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
CL = 50 pF 4.5 V 38 48 57
tpd Propagation delay A Y ns
CL = 15 pF 5V 16
tt Transition-time Y CL = 50 pF 4.5 V 15 19 22 ns

6.6 Operating Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Power dissipation capacitance
Cpd No load 5V 20 pF
per gate

6.7 Typical Characteristics

TA = 25°C

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7 0.3
2-V
6 4.5-V
0.25 6-V
VOH Output High Voltage (V)

VOL Output Low Voltage (V)

5
0.2
4
0.15
3
0.1
2

2-V 0.05
1 4.5-V
6-V
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
IOH Output High Current (mA) IOL Output Low Current (mA)
Figure 6-1. Typical output voltage in the high state Figure 6-2. Typical output voltage in the low state
(VOH) (VOL)

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7 Parameter Measurement Information

• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
• The outputs are measured one at a time, with one input transition per measurement.

Test VCC
90% 90%
Point
Input
10% 10%
0V
From Output tr(1) tf(1)
Under Test
VOH
CL(1) 90% 90%
Output
10% 10%
VOL
A. CL= 50 pF and includes probe and jig capacitance. tr(1) tf(1)

Figure 7-1. Load Circuit A. tt is the greater of tr and tf.

Figure 7-2. Voltage Waveforms Transition Times
VCC
Input 50% 50%
0V
tPLH(1) tPHL(1)
VOH
Output 50% 50%
VOL
tPHL(1) tPLH(1)
VOH
Output 50% 50%
VOL
A. The maximum between tPLH and tPHL is used for tpd.
Figure 7-3. Voltage Waveforms Propagation Delays

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8 Detailed Description
8.1 Overview
This device contains six independent inverters with Schmitt-trigger inputs. Each gate performs the Boolean
function Y = A in positive logic.
8.2 Functional Block Diagram

xA xY

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device
may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
over-current. The electrical and thermal limits defined in the Section 6.1 must be followed at all times.
The CD74HCT14 can drive a load with a total capacitance less than or equal to the maximum load listed in the
Section 6.5 connected to a high-impedance CMOS input while still meeting all of the datasheet specifications.
Larger capacitive loads can be applied, however it is not recommended to exceed the provided load value. If
larger capacitive loads are required, it is recommended to add a series resistor between the output and the
capacitor to limit output current to the values given in the Section 6.1.
8.3.2 TTL-Compatible Schmitt-Trigger CMOS Inputs
TTL-Compatible Schmitt-trigger CMOS inputs are high impedance and are typically modeled as a resistor from
the input to ground in parallel with the input capacitance given in the Section 6.4. The worst case resistance is
calculated with the maximum input voltage, given in the Section 6.1, and the maximum input leakage current,
given in the Section 6.4, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Section 6.4, which makes
this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower than standard
CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly will also
increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs,
please see Understanding Schmitt Triggers.
TTL-Compatible CMOS inputs have a lower threshold voltage than standard CMOS inputs to allow for
compatibility with older bipolar logic devices. See the Section 6.2 for the valid input voltages for the
CD74HCT14.

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8.3.3 Clamp Diode Structure

The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1.

CAUTION
Voltages beyond the values specified in the Section 6.1 table can cause damage to the device.
The recommended input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.

VCC
Device

+IIK +IOK

Input Logic Output

-IIK -IOK

GND

Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.4 Device Functional Modes

Table 8-1. Function Table
INPUT OUTPUT
A Y
L H
H L

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

This device can be used to add an additional stage to a counter with an external flip-flop. Because counters
use a negative edge trigger, the flip-flop's clock input must be inverted to provide this function. This function
only requires one of the six available inverters in the device, so the remaining channels can be used for other
applications needing an inverted signal or improved signal integrity. Unused inputs must be terminated at VCC or
GND. Unused outputs can be left floating.
9.2 Typical Application
Counter 20
21
Clear CLR
22
Input 23

CLR Q 24

D-Typ e
Flip-Flop

D Q

Figure 9-1. Typical application schematic

9.2.1 Design Requirements

9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Section 6.2. The supply voltage sets the
device's electrical characteristics as described in the Section 6.4.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
CD74HCT14 plus the maximum supply current, ICC, listed in the Section 6.4. The logic device can only source
or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the
maximum total current through GND or VCC listed in the Section 6.1.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.

CAUTION
The maximum junction temperature, TJ(max) listed in the Section 6.1, is an additional limitation to
prevent damage to the device. Do not violate any values listed in the Section 6.1. These limits are
provided to prevent damage to the device.

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9.2.1.2 Input Considerations

Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Section 6.1.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
CD74HCT14, as specified in the Section 6.4, and the desired input transition rate. A 10-kΩ resistor value is often
used due to these factors.
The CD74HCT14 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Section 6.4.
This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Section 6.7.
Refer to the Section 8.3 for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Section 6.4. Similarly, the ground voltage
is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as
specified by the VOL specification in the Section 6.4.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Section 8.3 for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Section 11.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the CD74HCT14
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Section 6.1 is not violated. Most CMOS inputs have a resistive load measured in
megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves

23 Input ± 32 kHz
24 ± 1 kHz
3
2

24

Figure 9-2. Typical application timing diagram

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Section 6.2. Each VCC terminal should have a bypass capacitor to prevent power disturbance. A 0.1-μF
capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different
frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results, as shown in Figure 11-1.

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11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of
a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
11.2 Layout Example
GND VCC

Recommend GND flood fill for

improved signal isolation, noise Bypass capacitor
reduction, and thermal dissipation placed close to
0.1 F the device

Unused input
1A 1 14 VCC Unused input
tied to GND
1Y 2 13 6A tied to VCC
Unused output
2A 3 12 6Y
left floating
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
Avoid 90°
corners for GND 7 8 4Y
signal lines

Figure 11-1. Example layout for the CD74HCT14

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12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CD54HCT14F ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HCT14F Samples
& Green
CD54HCT14F3A ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8689001CA Samples
& Green CD54HCT14F3A
CD74HCT14E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT14E Samples

CD74HCT14M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HCT14M Samples

CD74HCT14PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HK14 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

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Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HCT14, CD74HCT14 :

• Catalog : CD74HCT14
• Military : CD54HCT14

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HCT14M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HCT14M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HCT14M96 SOIC D 14 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1
CD74HCT14PWR TSSOP PW 14 2000 330.0 12.4 6.85 5.45 1.6 8.0 12.0 Q1
CD74HCT14PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT14PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HCT14M96 SOIC D 14 2500 356.0 356.0 35.0
CD74HCT14M96 SOIC D 14 2500 356.0 356.0 35.0
CD74HCT14M96 SOIC D 14 2500 366.0 364.0 50.0
CD74HCT14PWR TSSOP PW 14 2000 366.0 364.0 50.0
CD74HCT14PWR TSSOP PW 14 2000 356.0 356.0 35.0
CD74HCT14PWR TSSOP PW 14 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jul-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HCT14E N PDIP 14 25 506 13.97 11230 4.32
CD74HCT14E N PDIP 14 25 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
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