Metal Oxide Semiconductor Field Effect Transistor

This paper proposes simulation of fuzzy logic based current controlled nonisolated bidirectional DC - DC converter with DC drive. The converter has operates in continuous current mode and wide conversion ratio. The proposed DC-DC converter topology has switched coupled-inductor and cascaded circuit. The converter has less voltage stress across the switches. The results shows that fuzzy logic based current controller gives fast response and good transient performance compared to PI controller based speed control

ical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low- CDO for high-performance dense logic is presented. Strained silicon is used to increase satu-rated n-type and p-type metal–oxide–semiconductor field-effect transistors (MOSFETs) drive currents by 10 % and 25%, respec-tively. Using selective epitaxial Si 1 Ge in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by 50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility en-hancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain ( 5) is needed for a given PMOS mobility enh...

Understanding how the structure of the unit-cell affects the cryogenic performance of a Si power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is an important step toward optimizing of the device for cryogenic operations. In this paper, numerical simulations of the Si power Double Diffused MOSFET’ (DMOS) are performed at room temperature and cryogenic temperatures. Physically based models for temperature

ABSTRACT The authors have demonstrated a n-type GaAs depletion-mode metal-oxide-semiconductor field-effect Transistor with normalized transconductance gm of 266 mS/mm, peak electron mobility of 1124 cm2 V−1 s−1, and low hysteresis. The good device characteristics are attributed to the use of amorphous silicon interface passivation layer and HfO2 gate dielectric. The pulse Id-Vg characteristics show that even higher channel mobility (>2000 cm2 V−1 s−1) can be achieved by reducing the interfacial and bulk traps in the gate stack.

One-dimensional (1D) and two-dimensional (2D) metal-oxide-semiconductor field-effect transistors are compared using an approach based on the top-of-the-barrier ballistic transport model. The results for model devices show that 1D and 2D transistors behave quite similarly if the electrostatics is assumed to be perfect. Distinctive features of 1D transport are difficult to observe at room temperature. The effects of band structure on IV and CV characteristics of Si and InAs nanowire transistors are also examined using the sp 3 d 5 s* ...

ABSTRACT In this paper, we present the unique features exhibited by a novel step doping channel technique in nanoscale silicon carbide metal-oxide-semiconductor field-effect transistors (SDC-MOSFETs) for reaching a suitable threshold voltage upon device scaling and reliability improvement. The device demonstrates large enhancements in performance areas such as output resistance, hot-electron reliability, and threshold voltage upon channel-length or drain-voltage variation. Also, we describe an optimization technique in SDC-MOSFET for improving the threshold-voltage characterization. It was also found that the device performance is very much dependent upon the SDC region parameters. Results show that the most difficult problem of using silicon carbide in VLSI circuits could be solved and that the proposed silicon carbide MOSFETs can work very well in the nanoscale regime.

This paper proposes simulation of fuzzy logic based current controlled non-isolated bidirectional DC-DC converter with DC drive. The converter has operates in continuous current mode and wide conversion ratio. The proposed DC-DC converter topology has switched coupled-inductor and cascaded circuit. The converter has less voltage stress across the switches. The results shows that fuzzy logic based current controller gives fast response and good transient performance compared to PI controller based speed control.

Recent attention has been given to metal-oxide-semiconductor field-effect transistor (MOSFET) device designs that utilize stress to achieve performance gain in both n-type MOSFETs (NMOS) and p-type MOSFETs (PMOS). The physics behind NMOS gain is better understood than that of PMOS gain, which has received less attention. In this letter, we describe the warping phenomena which is responsible for the gain seen in [110] uniaxially stressed PMOS devices on [100] orientated wafers. We also demonstrate that shear uniaxial stress in PMOS is better suited to MOSFET applications than biaxial stress as it is able to maintain gain at high vertical and lateral fields.

In this work, the time-dependence of Si/SiO2 interface trap formation is considered by solving an improved set of Si-H defect kinetics equations that take into account interface disorder and the Si-H bond activation energy evolution as the bonds are broken. This model is applied to the simulation of metal oxide semiconductor field effect transistor (MOSFET) high field and hot carrier

... Effect Transistors. Authors: Putra, Arifin Tamsir; Nishida, Akio; Kamohara, Shiro; Hiramoto, Toshiro. Affiliation ... autoregressive model. W c is extracted from the gate line-edge shape depicted in a scanning electron microscope (SEM) image. This ...

SrTiO3 has been grown epitaxially by molecular beam epitaxy on Si. The capacitance of this 110 Å dielectric film is electrically equivalent to less than 10 Å of SiO2. This structure has been used to make capacitors and metal oxide semiconductor field effect transistors. The interface trap density between the SrTiO3 and the Si is 6.4×1010 states/cm2 eV and the

... Xiang-Dong Wang, Chun-li Liu, Aaron Thean, Erika Duda, Ran Liu, Qianghua Xie, Shifeng Lu, Alex Barr, Ted White, Bich-yen Nguyen ... MT Currie, CW Leitz, TA Langdo, G. Taraschi, EA Fitzgerald, and D. A Antoniadis, “Carrier mobilities and process stability of strained Si n-and p ...

In this paper, for the first time, we propose a partial silicon-on-insulator (P-SOI) lateral double-diffused metal-oxide-semiconductor-field-effect-transistor (LDMOSFET) with a modified buried layer in order to improve breakdown voltage (BV) and self-heating effects (SHEs). The main idea of this work is to control the electric field by shaping the buried layer. With two steps introduced in the buried layer, the electric field distribution is modified. Also a P-type window introduced makes the substrate share the vertical voltage drop, leading to a high vertical BV. Moreover, four interface electric field peaks are introduced by the buried P-layer, the Si window and two steps, which modulate the electric field in the SOI layer and the substrate. Hence, a more uniform electric field is obtained; consequently, a high BV is achieved. Furthermore, the Si window creates a conduction path between the active layer and substrate and alleviates the SHE. Two-dimensional simulations show that t...

We have observed significant instability in the threshold voltage of 4H-SiC metal-oxide-semiconductor field-effect transistors due to gate-bias stressing. This effect has a strong measurement time dependence. For example, a 20-mus-long gate ramp used to measure the I-V characteristic and extract a threshold voltage was found to result in a instability three to four times greater than that measured with a

In this study, we analyzed the impact of gate overlap on the performance of Schottky barrier metal-oxide-semiconductor field-effect transistors (SB MOSFETs) including the gate induced barrier lowering (GIBL) effect by two-dimensional (2D) full-band self-consistent ensemble Monte Carlo (EMC) simulation. Results show that the GIBL effect and gate overlap affect drive current significantly. The GIBL effect relieves the degradation of current

Characterization of a metal-oxide-semiconductor field effect transistor incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE) is demonstrated by using numerical simulation. An analysis of different uniform body doping from 1017 cm-3 to 1019 cm-3 of 50 nm channel length (Lg) with DP incorporated between the channel and source/drain has been done successfully. The DP has suppressed short channel effect (SCE) without the needs of decreasing the junction depth. A reduction of leakage current (IOFF) was obtained in MOSFET with DP without altering the drive current (ION). A very low leakage current is obtained for DP device with drain voltage (VDS) of 0.1 V. Consequently, the threshold voltage (VT) is increase accordingly with the increasing of body doping. A better control of VT roll-off was also demonstrated better for MOSFET with DP compare to conventional MOSFET. Thus, the incorporation of DP will enhance the electrical performance and give a very good con...