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WO2022246593A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2022246593A1
WO2022246593A1 PCT/CN2021/095450 CN2021095450W WO2022246593A1 WO 2022246593 A1 WO2022246593 A1 WO 2022246593A1 CN 2021095450 W CN2021095450 W CN 2021095450W WO 2022246593 A1 WO2022246593 A1 WO 2022246593A1
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WO
WIPO (PCT)
Prior art keywords
node
coupled
transistor
line
initialization
Prior art date
Application number
PCT/CN2021/095450
Other languages
English (en)
French (fr)
Inventor
于子阳
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/764,547 priority Critical patent/US20240054951A1/en
Priority to PCT/CN2021/095450 priority patent/WO2022246593A1/zh
Priority to GB2305793.8A priority patent/GB2615665A/en
Priority to CN202180001240.1A priority patent/CN115943753A/zh
Publication of WO2022246593A1 publication Critical patent/WO2022246593A1/zh

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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • H—ELECTRICITY
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Definitions

  • This article relates to but not limited to the field of display technology, especially a pixel circuit, a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • PM Passive Matrix
  • AM Active Matrix
  • AMOLED is a current drive device, using independent thin film transistors (TFT, Thin Film Transistor) controls each sub-pixel, and each sub-pixel can be continuously and independently driven to emit light.
  • Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display device.
  • an embodiment of the present disclosure provides a pixel circuit for driving a light emitting element to emit light, including: a driving subcircuit, a data writing subcircuit, a threshold compensation subcircuit, a storage subcircuit, a light emission control subcircuit, a first initializer circuit and a second initialization subcircuit.
  • the driving sub-circuit is coupled to the first node, the second node and the third node, and is configured to provide a driving current to the third node under the control of the first node.
  • the data writing sub-circuit is coupled to the data line, the scan line and the third node, and configured to transmit the data signal provided by the data line to the third node under the control of the scan line.
  • the threshold compensation subcircuit is coupled to the scan line, the first node and the second node, and is configured to turn on the first node and the second node under the control of the scan line, so that the threshold value of the driving subcircuit A voltage is written to the storage subcircuit.
  • the storage sub-circuit is coupled to the first node and the fourth node.
  • the lighting control sub-circuit is coupled to the lighting control line, the first power line, the second node, the third node and the fourth node, and is configured to connect the first power line and the second node under the control of the lighting control line is turned on, and the third node and the fourth node are turned on.
  • the first initialization sub-circuit is coupled to the reset line, the first power line and the first node, and is configured to conduct the first power line and the first node under the control of the reset line.
  • the second initialization subcircuit is coupled to the scan line, the reset line, the reference voltage line and the fourth node, configured to conduct the reference voltage line and the fourth node under the control of the reset line, and Under control, the reference voltage line and the fourth node are turned on.
  • the first pole of the light emitting element is coupled to the fourth node, and the second pole of the light emitting element is coupled to the second power line.
  • the reset line coupled to the pixel circuit in the nth row is coupled to the scan line driving the pixel circuit in the n-1th row, where n is a positive integer.
  • the pixel circuit further includes: a voltage stabilizing subcircuit coupled to the scan line and the fourth node.
  • the voltage stabilizing sub-circuit includes: a voltage stabilizing capacitor; a first end of the voltage stabilizing capacitor is coupled to the fourth node, and a second end of the voltage stabilizing capacitor is coupled to the scan line .
  • the driving sub-circuit includes: a driving transistor; the control electrode of the driving transistor is coupled to the first node, the first electrode of the driving transistor is coupled to the second node, and the The second pole of the driving transistor is coupled to the third node.
  • the first initialization sub-circuit includes: a first initialization transistor; the control electrode of the first initialization transistor is coupled to the reset line, and the first electrode of the first initialization transistor is connected to the first initialization transistor.
  • a power line is coupled, and the second pole of the first initialization transistor is coupled to the first node.
  • the second initialization subcircuit includes: a second initialization transistor and a third initialization transistor.
  • the control electrode of the second initialization transistor is coupled to the reset line, the first electrode of the second initialization transistor is coupled to the reference voltage line, and the second electrode of the second initialization transistor is coupled to the fourth node.
  • the control electrode of the third initialization transistor is coupled to the scan line, the first electrode of the third initialization transistor is coupled to the reference voltage line, and the second electrode of the third initialization transistor is coupled to the fourth node.
  • the threshold compensation sub-circuit includes: a threshold compensation transistor; the control electrode of the threshold compensation transistor is coupled to the scan line, and the first electrode of the threshold compensation transistor is coupled to the first node , the second pole of the threshold compensation transistor is coupled to the second node.
  • the light emission control sub-circuit includes: a first light emission control transistor and a second light emission control transistor.
  • the control pole of the first light emission control transistor is coupled to the light emission control line, the first pole of the first light emission control transistor is coupled to the first power supply line, and the second pole of the first light emission control transistor is coupled to the second power supply line. Node coupling.
  • the control pole of the second light emission control transistor is coupled to the light emission control line, the first pole of the second light emission control transistor is coupled to the third node, the second pole of the second light emission control transistor is coupled to the fourth node coupling.
  • the data writing sub-circuit includes: a data writing transistor; the control electrode of the data writing transistor is coupled to the scan line, and the first electrode of the data writing transistor is connected to the data line coupled, the second pole of the data writing transistor is coupled to the third node.
  • the storage sub-circuit includes: a storage capacitor; a first end of the storage capacitor is coupled to a first node, and a second end of the storage capacitor is coupled to a fourth node.
  • the driving subcircuit includes: a driving transistor; the first initialization subcircuit includes: a first initialization transistor; the second initialization subcircuit includes: a second initialization transistor and a first initialization transistor. Three initialization transistors; the threshold compensation subcircuit includes: a threshold compensation transistor; the light emission control subcircuit includes: a first light emission control transistor and a second light emission control transistor; the data writing subcircuit includes: data writing The transistor; the storage sub-circuit includes: a storage capacitor. The control pole of the driving transistor is coupled to the first node, the first pole of the driving transistor is coupled to the second node, and the second pole of the driving transistor is coupled to the third node.
  • the control electrode of the first initialization transistor is coupled to the reset line, the first electrode of the first initialization transistor is coupled to the first power line, and the second electrode of the first initialization transistor is coupled to the first node.
  • the control electrode of the second initialization transistor is coupled to the reset line, the first electrode of the second initialization transistor is coupled to the reference voltage line, and the second electrode of the second initialization transistor is coupled to the fourth node.
  • the control electrode of the third initialization transistor is coupled to the scan line, the first electrode of the third initialization transistor is coupled to the reference voltage line, and the second electrode of the third initialization transistor is coupled to the fourth node.
  • the control electrode of the threshold compensation transistor is coupled to the scan line, the first electrode of the threshold compensation transistor is coupled to the first node, and the second electrode of the threshold compensation transistor is coupled to the second node.
  • the control pole of the first light emission control transistor is coupled to the light emission control line, the first pole of the first light emission control transistor is coupled to the first power supply line, and the second pole of the first light emission control transistor is coupled to the second power supply line. Node coupling.
  • the control pole of the second light emission control transistor is coupled to the light emission control line, the first pole of the second light emission control transistor is coupled to the third node, the second pole of the second light emission control transistor is coupled to the fourth node coupling.
  • the control pole of the data writing transistor is coupled to the scan line, the first pole of the data writing transistor is coupled to the data line, and the second pole of the data writing transistor is coupled to the third node.
  • the first end of the storage capacitor is coupled to the first node, and the second end of the storage capacitor is coupled to the fourth node.
  • the driving transistor, the first initialization transistor, the second initialization transistor, the third initialization transistor, the threshold compensation transistor, the first light emission control transistor, the second light emission control transistor and the data writing transistor are all N-type transistor.
  • the first initialization transistor and the threshold compensation transistor are double-gate transistors.
  • an embodiment of the present disclosure provides a driving method for a pixel circuit, which is applied to the above-mentioned pixel circuit, including: in the initialization phase, under the control of the reset line, the first initialization sub-circuit connects the first power line and The first node is turned on, and the second initialization sub-circuit conducts the reference voltage line and the fourth node; in the writing phase, under the control of the scanning line, the data writing sub-circuit transmits the data signal provided by the data line to the third node, the threshold compensation subcircuit conducts the first node and the second node to write the threshold voltage of the driving subcircuit into the storage subcircuit, and the second initialization subcircuit conducts the reference voltage line and the fourth node; stage, under the control of the luminescence control line, the luminescence control subcircuit conducts the first power supply line and the second node, and conducts the third node and the fourth node, so as to transmit the driving current output by the driving subcircuit to the luminescence
  • an embodiment of the present disclosure provides a display device, including the above-mentioned pixel circuit.
  • the display device further includes: a gate driving circuit.
  • the gate drive circuit includes: a plurality of cascaded first shift register units and a plurality of cascaded second shift register units.
  • the output end of the first shift register unit of the nth stage is coupled to the scan line driving the pixel circuit in the nth row; the output end of the first shift register unit in the n-1th stage is coupled to the reset line driving the pixel circuit in the nth row connected; the output terminal of the second shift register unit of the nth stage is coupled to the light-emitting control line driving the pixel circuit in the nth row; wherein, n is a positive integer.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 2 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 3 is an equivalent circuit diagram of a driving subcircuit of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 4 is an equivalent circuit diagram of a first initialization subcircuit of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 5 is an equivalent circuit diagram of a second initialization subcircuit of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 6 is an equivalent circuit diagram of a threshold compensation subcircuit of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 7 is an equivalent circuit diagram of a light emission control subcircuit of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 8 is an equivalent circuit diagram of a data writing sub-circuit of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 9 is an equivalent circuit diagram of a storage sub-circuit of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 10 is an equivalent circuit diagram of a voltage stabilizing subcircuit of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 11 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 12 is a working timing diagram of the pixel circuit provided in FIG. 11;
  • FIG. 13 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 14 is a flowchart of a driving method of a pixel circuit according to at least one embodiment of the present disclosure
  • FIG. 15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • FIG. 16 is another schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and contents can be changed into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
  • connection should be interpreted in a broad sense unless otherwise specified and limited.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • electrically connected includes the situation that the constituent elements are connected together through an element having some kind of electrical function.
  • the “element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components. Examples of “elements having some kind of electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • one of the electrodes is called the first pole, and the other electrode is called the second pole.
  • the first pole can be the source electrode or the drain electrode
  • the second pole can be A drain electrode or a source electrode
  • a gate electrode of a transistor is called a gate electrode.
  • parallel means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus may include a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state in which the angle formed by two straight lines is 80° to 100°, and therefore, an angle of 85° to 95° may be included.
  • the OLED light-emitting element adopts the current driving method to realize light emission, therefore, the current stability requirements of the driving transistor (DTFT, Driving TFT) and the OLED light-emitting element are relatively high.
  • the output current of the driving transistor is not stable, and the threshold voltage Vth of the driving transistor will shift under the influence of factors such as temperature, thereby affecting the display effect and life of the display device.
  • Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display device, so as to realize compensation of a threshold voltage of a driving sub-circuit, avoid the influence of the threshold voltage on a driving current of a light-emitting element, and thereby improve a display effect.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit provided in this exemplary embodiment is used to drive a light emitting element to emit light.
  • the pixel circuit in this embodiment includes: a driving subcircuit, a data writing subcircuit, a threshold compensation subcircuit, a storage subcircuit, a light emission control subcircuit, a first initialization subcircuit and a second initialization subcircuit.
  • the driving sub-circuit is coupled with the first node N1, the second node N2 and the third node N3, and is configured to provide a driving current to the third node N3 under the control of the first node N1.
  • the data writing sub-circuit is coupled to the data line DL, the scan line GL and the third node N3, configured to transmit the data signal provided by the data line DL to the third node N3 under the control of the scan line GL.
  • the threshold compensation subcircuit is coupled to the scanning line GL, the first node N1 and the second node N2, and is configured to conduct the first node N1 and the second node N2 under the control of the scanning line GL, so as to drive the subcircuit
  • the threshold voltage is written into the storage subcircuit.
  • the storage subcircuit is coupled to the first node N1 and the fourth node N4.
  • the light emission control subcircuit is coupled to the light emission control line EML, the first power line PL1, the second node N2, the third node N3 and the fourth node N4, and is configured to turn the first power line PL1 is turned on to the second node N2, and turns on the third node N3 to the fourth node N4.
  • the first initialization subcircuit is coupled to the reset line RST, the first power line PL1 and the first node N1, and is configured to conduct the first power line PL1 and the first node N1 under the control of the reset line RST.
  • the second initialization subcircuit is coupled to the scan line GL, the reset line RST, the reference voltage line REF and the fourth node N4, and is configured to conduct the reference voltage line REF and the fourth node N4 under the control of the reset line RST, And under the control of the scanning line GL, the reference voltage line REF and the fourth node N4 are turned on.
  • the first pole of the light emitting element is coupled to the fourth node N4, and the second pole of the light emitting element is coupled to the second power line PL2.
  • the light emitting element may be an organic light emitting diode (OLED).
  • OLED organic light emitting diode
  • the first pole of the light emitting element may be an anode, and the second pole may be a cathode.
  • this embodiment does not limit it.
  • the first power line PL1 can continuously provide a high level signal, for example, the first power line PL1 provides the first power signal ELVDD.
  • the second power line PL2 can continuously provide a low level signal, for example, the second power line PL2 provides the second power signal ELVSS.
  • the pixel circuit provided by this embodiment can realize internal real-time compensation for the threshold voltage of the driving sub-circuit, thereby avoiding poor display caused by the drift of the threshold voltage of the driving sub-circuit.
  • the reset line coupled to the pixel circuit in the nth row is coupled to the scan line driving the pixel circuit in the n-1th row, where n is a positive integer.
  • the scanning line driving the pixel circuit in the n-1th row may be multiplexed as the reset line driving the pixel circuit in the nth row to provide a reset signal to the pixel circuit in the nth row.
  • the gate drive circuit only needs to provide two different gate drive signals (ie, the scanning signal and the light emission control signal) to the pixel circuit, which is beneficial to simplify the structure of the gate drive circuit, improve signal stability, and facilitate A narrow frame of the display device is realized.
  • FIG. 2 is another structural schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the pixel circuit provided in this exemplary embodiment further includes: a voltage stabilizing sub-circuit.
  • the voltage stabilizing sub-circuit is coupled to the scan line GL and the fourth node N4.
  • the voltage stabilizing sub-circuit is configured to maintain the voltage of the fourth node N4 and prevent the leakage current of the transistor from affecting the compensation effect of the threshold voltage.
  • FIG. 3 is an equivalent circuit diagram of a driving subcircuit of a pixel circuit according to at least one embodiment of the present disclosure.
  • the driving sub-circuit in the pixel circuit includes: a driving transistor M8.
  • the control electrode of the driving transistor M8 is coupled to the first node N1, the first electrode of the driving transistor M8 is coupled to the second node N2, and the second electrode of the driving transistor M8 is coupled to the third node N3.
  • the driving transistor M8 is configured to provide a driving current to the third node N3 under the control of the first node N1.
  • FIG. 3 shows an exemplary structure of the driving sub-circuit. Those skilled in the art can easily understand that the implementation of the driving sub-circuit is not limited thereto, as long as its functions can be realized.
  • FIG. 4 is an equivalent circuit diagram of a first initialization sub-circuit of a pixel circuit according to at least one embodiment of the present disclosure.
  • the first initialization sub-circuit in the pixel circuit includes: a first initialization transistor M1.
  • the control electrode of the first initialization transistor M1 is coupled to the reset line RST, the first electrode of the first initialization transistor M1 is coupled to the first power line PL1 , and the second electrode of the first initialization transistor M1 is coupled to the first node N1.
  • FIG. 4 shows an exemplary structure of the first initialization sub-circuit, and those skilled in the art can easily understand that the implementation of the first initialization sub-circuit is not limited thereto, as long as its functions can be realized.
  • FIG. 5 is an equivalent circuit diagram of a second initialization subcircuit of a pixel circuit according to at least one embodiment of the present disclosure.
  • the second initialization subcircuit in the pixel circuit includes: a second initialization transistor M3 and a third initialization transistor M4 .
  • the control electrode of the second initialization transistor M3 is coupled to the reset line RST, the first electrode of the second initialization transistor M3 is coupled to the reference voltage line REF, and the second electrode of the second initialization transistor M3 is coupled to the fourth node N4.
  • the control electrode of the third initialization transistor M4 is coupled to the scan line GL, the first electrode of the third initialization transistor M4 is coupled to the reference voltage line REF, and the second electrode of the third initialization transistor M4 is coupled to the fourth node N4.
  • FIG. 5 shows an exemplary structure of the second initialization subcircuit, and those skilled in the art can easily understand that the implementation of the second initialization subcircuit is not limited thereto, as long as its functions can be realized.
  • FIG. 6 is an equivalent circuit diagram of a threshold compensation subcircuit of a pixel circuit according to at least one embodiment of the present disclosure.
  • the threshold compensation sub-circuit in the pixel circuit includes: a threshold compensation transistor M2.
  • the control electrode of the threshold compensation transistor M2 is coupled to the scan line GL
  • the first electrode of the threshold compensation transistor M2 is coupled to the first node N1
  • the second electrode of the threshold compensation transistor M2 is coupled to the second node N2.
  • FIG. 6 shows an exemplary structure of the threshold compensation sub-circuit. Those skilled in the art can easily understand that the implementation of the threshold compensation sub-circuit is not limited thereto, as long as its functions can be realized.
  • FIG. 7 is an equivalent circuit diagram of a light emission control subcircuit of a pixel circuit according to at least one embodiment of the present disclosure.
  • the light emission control subcircuit in the pixel circuit includes: a first light emission control transistor M5 and a second light emission control transistor M6 .
  • the control electrode of the first light emission control transistor M5 is coupled to the light emission control line EML
  • the first electrode of the first light emission control transistor M5 is coupled to the first power line PL1
  • the second electrode of the first light emission control transistor M5 is connected to the second node N2 coupling.
  • the control electrode of the second light emission control transistor M6 is coupled to the light emission control line EML, the first electrode of the second light emission control transistor M6 is coupled to the third node N3, the second electrode of the second light emission control transistor M6 is connected to the fourth node N4 coupling.
  • FIG. 7 shows an exemplary structure of the light emission control subcircuit. Those skilled in the art can easily understand that the implementation of the light emission control subcircuit is not limited thereto, as long as its functions can be realized.
  • FIG. 8 is an equivalent circuit diagram of a data writing sub-circuit of a pixel circuit according to at least one embodiment of the present disclosure.
  • the data writing sub-circuit in the pixel circuit includes: a data writing transistor M7.
  • the control electrode of the data writing transistor M7 is coupled to the scan line GL
  • the first electrode of the data writing transistor M7 is coupled to the data line DL
  • the second electrode of the data writing transistor M7 is coupled to the third node N3.
  • Figure 8 shows an exemplary structure of the data writing sub-circuit, and those skilled in the art can easily understand that the implementation of the data writing sub-circuit is not limited thereto, as long as its function can be realized.
  • FIG. 9 is an equivalent circuit diagram of a storage sub-circuit of a pixel circuit according to at least one embodiment of the present disclosure.
  • the storage sub-circuit in the pixel circuit includes: a storage capacitor C1. A first end of the storage capacitor C1 is coupled to the first node N1, and a second end of the storage capacitor C1 is coupled to the fourth node N4.
  • FIG. 9 shows an exemplary structure of the storage sub-circuit. Those skilled in the art can easily understand that the implementation of the storage sub-circuit is not limited thereto, as long as its function can be realized.
  • FIG. 10 is an equivalent circuit diagram of a voltage stabilizing subcircuit of a pixel circuit according to at least one embodiment of the present disclosure.
  • the voltage stabilizing sub-circuit in the pixel circuit includes: a voltage stabilizing capacitor C2.
  • a first end of the voltage stabilizing capacitor C2 is coupled to the fourth node N4, and a second end of the voltage stabilizing capacitor C2 is coupled to the scan line GL.
  • FIG. 10 shows an exemplary structure of the voltage stabilizing sub-circuit. Those skilled in the art can easily understand that the implementation of the voltage stabilizing sub-circuit is not limited thereto, as long as its functions can be realized.
  • FIG. 11 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the driving subcircuit includes: a driving transistor M8; the first initialization subcircuit includes: a first initialization transistor M1; the threshold compensation subcircuit includes: a threshold compensation transistor M2; the second initialization The subcircuit includes: a second initialization transistor M3 and a third initialization transistor M4; the light emission control subcircuit includes: a first light emission control transistor M5 and a second light emission control transistor M6; the data write subcircuit includes: a data write transistor M7;
  • the sub-circuit includes: storage capacitor C1; the voltage stabilizing sub-circuit includes: voltage stabilizing capacitor C2.
  • the control electrode of the driving transistor M8 is coupled to the first node N1, the first electrode of the driving transistor M8 is coupled to the second node N2, and the second electrode of the driving transistor M8 coupled with the third node N3.
  • the control electrode of the first initialization transistor M1 is coupled to the reset line RST, the first electrode of the first initialization transistor M1 is coupled to the first power line PL1 , and the second electrode of the first initialization transistor M1 is coupled to the first node N1.
  • the control electrode of the second initialization transistor M3 is coupled to the reset line RST, the first electrode of the second initialization transistor M3 is coupled to the reference voltage line REF, and the second electrode of the second initialization transistor M3 is coupled to the fourth node N4.
  • the control electrode of the third initialization transistor M4 is coupled to the scan line GL, the first electrode of the third initialization transistor M4 is coupled to the reference voltage line REF, and the second electrode of the third initialization transistor M4 is coupled to the fourth node N4.
  • the control electrode of the threshold compensation transistor M2 is coupled to the scan line GL, the first electrode of the threshold compensation transistor M2 is coupled to the first node N1, and the second electrode of the threshold compensation transistor M2 is coupled to the second node N2.
  • the control electrode of the first light emission control transistor M5 is coupled to the light emission control line EML, the first electrode of the first light emission control transistor M5 is coupled to the first power line PL1, the second electrode of the first light emission control transistor M5 is connected to the second node N2 coupling.
  • the control electrode of the second light emission control transistor M6 is coupled to the light emission control line EML, the first electrode of the second light emission control transistor M6 is coupled to the third node N3, the second electrode of the second light emission control transistor M6 is connected to the fourth node N4 coupling.
  • the control electrode of the data writing transistor M7 is coupled to the scan line GL, the first electrode of the data writing transistor M7 is coupled to the data line DL, and the second electrode of the data writing transistor M7 is coupled to the third node N3.
  • a first end of the storage capacitor C1 is coupled to the first node N1, and a second end of the storage capacitor C1 is coupled to the fourth node N4.
  • a first end of the voltage stabilizing capacitor C2 is coupled to the fourth node N4, and a second end of the voltage stabilizing capacitor C2 is coupled to the scan line GL.
  • the first pole of the light emitting element EL is coupled to the fourth node N4, and the second pole of the light emitting element EL is coupled to the second power line PL2.
  • the transistors M1 to M8 in the pixel circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield rate of the product.
  • the plurality of transistors in the pixel circuit may include P-type transistors and N-type transistors. This embodiment does not limit it.
  • the transistors M1 to M8 in the pixel circuit may be low temperature polysilicon thin film transistors, or may be oxide thin film transistors, or may be low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO) , Low Temperature Polycrystalline Oxide) display substrate, can take advantage of the advantages of both, can achieve low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • Low Temperature Polycrystalline Oxide Low Temperature Polycrystalline Oxide
  • FIG. 12 is a working timing diagram of the pixel circuit shown in FIG. 11 .
  • the pixel circuit involved in this exemplary embodiment includes: 8 transistor units (namely transistors M1 to M8), 2 capacitor units (ie storage capacitor C1 and voltage stabilizing capacitor C2), 5 input terminals ( That is, the data line DL, the scanning line GL, the reset line RST, the light emission control line EML, the reference voltage line REF), and two power terminals (ie, the first power line PL1 and the second power line PL2 ).
  • the first power line PL1 continuously provides a high-level signal, for example, the first power signal ELVDD
  • the second power line PL2 continuously provides a low-level signal, for example, the second power signal ELVSS.
  • the scan line GL(n) driving the n-th row of pixel circuits is configured to supply the scan signal G(n).
  • the scan line GL(n-1) for driving the pixel circuit in the n-1 row can be multiplexed as the reset line RST for driving the pixel circuit in the n-th row, and is configured to provide a reset signal for the pixel circuit in the n-th row. That is, the reset signal provided by the reset line RST of the nth row of pixel circuits is the scan signal G(n ⁇ 1).
  • n is a positive integer.
  • the working process of the pixel circuit includes the following stages: an initialization stage T1 , a writing stage T2 and a light emitting stage T3 .
  • the light emission control signal EM provided by the light emission control line EML is at a low level, and the first light emission control transistor M5 and the second light emission control transistor M6 are disconnected;
  • the scanning line GL provides The scan signal G(n) is low level, the threshold compensation transistor M2, the data writing transistor M7 and the third initialization transistor M4 are disconnected;
  • the reset signal provided by the reset line RST ie scan signal G(n-1) is High level, the first initialization transistor M1 and the second initialization transistor M3 are turned on.
  • the first initialization transistor M1 and the second initialization transistor M3 are turned on to initialize both ends of the storage capacitor C1 (ie, the first node N1 and the fourth node N4 ).
  • the light emission control signal EM provided by the light emission control line EML is at a low level, and the first light emission control transistor M5 and the second light emission control transistor M6 are disconnected; the reset line RST The provided reset signal (that is, the scanning signal G(n-1)) is low level, the first initialization transistor M1 and the second initialization transistor M3 are disconnected; the scanning signal G(n) provided by the scanning line GL is high level, The threshold compensation transistor M2, the third initialization transistor M4, and the data writing transistor M7 are turned on.
  • the threshold compensation transistor M2 and the data writing transistor M7 are turned on, so that the data line DL establishes a path with the first node N1 through the data writing transistor M7 , the driving transistor M5 and the threshold compensation transistor M2 .
  • the threshold compensation transistor M2 conducts the first node N1 and the second node N2 , and the driving transistor M8 forms a diode structure.
  • the driving transistor M8 is turned on to generate a driving current
  • the second light emission control transistor M6 since the second light emission control transistor M6 is turned off, the driving current cannot flow into the light emitting element EL, and the light emitting element EL does not emit light.
  • the reset signal provided by the reset line RST (that is, the scan signal G(n-1)) is at a low level, and the first initialization transistor M1 and the second initialization transistor M3 are turned off. open; the scan signal G(n) provided by the scan line GL is low level, the threshold compensation transistor M2, the third initialization transistor M4 and the data writing transistor M7 are disconnected; the light emission control signal EM provided by the light emission control line EML is high level level, the first light emission control transistor M5 and the second light emission control transistor M6 are turned on.
  • the driving current generated by the driving transistor M8 flows into the light emitting element EL through the second light emitting control transistor M6.
  • the driving current Id output by the driving transistor M8 can be obtained by the following formula:
  • ⁇ is the channel mobility of the drive transistor
  • W and L are the channel width and channel length of the drive transistor, respectively
  • C ox is the channel capacitance per unit area of the drive transistor.
  • Vgs is the gate-source voltage difference of the driving transistor.
  • Vth is the threshold voltage of the driving transistor.
  • Vdata is the voltage of the data signal DA transmitted by the data line DL.
  • Vref is a reference voltage provided by the reference voltage line REF.
  • the driving current has nothing to do with the threshold voltage Vth of the driving transistor, but only depends on the voltage of the data signal DA provided by the data line DL and the reference voltage Vref provided by the reference voltage line REF, thereby eliminating the impact of the threshold voltage of the driving transistor on The influence of the driving current ensures uniform display brightness of the display device and improves the display effect.
  • the storage and compensation functions of the threshold voltage of the driving transistor can be realized by using the pixel circuit including eight transistors and two capacitors, thereby eliminating the influence of the threshold voltage of the driving transistor on the driving current.
  • both ends of the voltage stabilizing capacitor C2 are respectively connected to the fourth node N2 and the scanning line GL, which can stabilize the potential of the fourth node N4 and prevent the leakage current of the transistor from affecting the compensation effect.
  • the voltage of the data signal DA transmitted by the data line DL may be approximately 0V to 5V, and the threshold voltage Vth of the driving transistor may be approximately ⁇ 1V to 1V.
  • this embodiment does not limit it.
  • the pixel circuit of this exemplary embodiment can realize the internal compensation of the threshold voltage, thereby improving the display effect. Moreover, by multiplexing the scanning signal as the reset signal, the structure of the gate driving circuit can be simplified, which is beneficial to realize the narrow frame design. In addition, the pixel circuit of this exemplary embodiment adopts N-type thin film transistors, which can improve problems such as short-term afterimages caused by hysteresis of P-type transistors.
  • FIG. 13 is another equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the first initialization transistor M1 and the threshold compensation transistor M2 may be double-gate transistors.
  • the first initialization transistor M1 includes two first sub-transistors M1_1 and M1_2.
  • the control electrode of the first sub-transistor M1_1 is coupled to the control electrode of the first sub-transistor M1_2, and is coupled to the reset line RST; the first electrode of the first sub-transistor M1_1 is coupled to the first node N1, and the first sub-transistor M1_1
  • the second pole of the first sub-transistor M1_2 is coupled to the first pole of the first sub-transistor M1_2, and the second pole of the first sub-transistor M1_2 is coupled to the first power line PL1.
  • the threshold compensation transistor M2 includes two second sub-transistors M2_1 and M2_2.
  • the control electrode of the second sub-transistor M2_1 is coupled to the control electrode of the second sub-transistor M2_2, and is coupled to the scanning line GL; the first electrode of the second sub-transistor M2_1 is coupled to the first node N1, and the second sub-transistor M2_1
  • the second pole of the second sub-transistor M2_2 is coupled to the first pole of the second sub-transistor M2_2, and the second pole of the second sub-transistor M2_2 is coupled to the second node N2.
  • the leakage of the threshold compensation transistor to the first node can be reduced during the initialization phase and the light emitting phase, and the leakage of the threshold compensation transistor to the first node can be reduced during the writing phase and the light emitting phase.
  • a leakage current of the initialization transistor to the first node is used to prevent the leakage current of the transistor from affecting the compensation effect.
  • FIG. 14 is a flowchart of a driving method of a pixel circuit according to at least one embodiment of the present disclosure. As shown in FIG. 14, the driving method of the pixel circuit in this exemplary embodiment includes the following steps:
  • Step 100 in the initialization phase, under the control of the reset line, the first initialization subcircuit conducts the first power supply line and the first node, and the second initialization subcircuit conducts the reference voltage line and the fourth node;
  • Step 200 in the writing stage, under the control of the scanning line, the data writing sub-circuit transmits the data signal provided by the data line to the third node, and the threshold compensation sub-circuit conducts the first node and the second node to connect The threshold voltage of the driving subcircuit is written into the storage subcircuit, and the second initialization subcircuit conducts the reference voltage line and the fourth node;
  • Step 300 in the lighting stage, under the control of the lighting control line, the lighting control subcircuit conducts the first power supply line and the second node, and conducts the third node and the fourth node, so as to output the output of the driving subcircuit
  • the driving current is transmitted to the light emitting element.
  • the pixel circuit driving method provided in this exemplary embodiment is used in the pixel circuit provided in the foregoing embodiments, and its implementation principle and effect are similar, so details will not be repeated here.
  • At least one embodiment of the present disclosure further provides a display device, including: a pixel circuit.
  • a display device including: a pixel circuit.
  • the implementation principles and effects of the pixel circuit are similar to those of the foregoing embodiments, so details will not be repeated here.
  • a display device may include a display substrate, and a pixel circuit may be disposed on the display substrate.
  • the display substrate may be an OLED display substrate.
  • the display device can be any product or component with a display function, such as an OLED display device, a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. However, this embodiment does not limit it.
  • the display device further includes: a gate driving circuit.
  • the gate drive circuit includes: a plurality of cascaded first shift register units and a plurality of cascaded second shift register units.
  • the output end of the first shift register unit of the nth stage is coupled to the scan line driving the pixel circuit in the nth row; the output end of the first shift register unit in the n-1th stage is coupled to the reset line driving the pixel circuit in the nth row connected; the output terminal of the second shift register unit of the nth stage is coupled to the light-emitting control line driving the pixel circuit in the nth row; wherein, n is a positive integer.
  • FIG. 15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the display device includes: a plurality of pixel circuits 10, a plurality of scanning lines (for example, scanning lines GL(0) to GL(n)), a plurality of light emission control lines ( For example, light emission control lines EML(1) to EML(n)), a plurality of data lines (for example, data lines DL(1) to DL(m)), gate drive circuits 12a and 12b, data drivers, and a timing controller .
  • n and m are both positive integers.
  • a plurality of pixel circuits 10 are located in the display area of the display device, the gate drive circuit 12a and the gate drive circuit 12b are located on opposite sides of the display area, for example, the gate drive circuit 12a is located on the left side of the display area, The gate drive circuit 12b is located on the right side of the display area.
  • the gate drive circuit 12a is taken as an example for description.
  • the gate driving circuit 12a includes: a plurality of cascaded first shift register units G_GOA, and a plurality of cascaded second shift register units EM_GOA.
  • the output terminal of the first shift register unit G_GOA(n) of the nth stage is coupled to the scanning line GL(n) driving the pixel circuit of the nth row; the first shift register unit G_GOA(n-1) of the n-1st stage The output terminal of is coupled to the reset line driving the nth row of pixel circuits.
  • the output end of the nth stage second shift register unit EM_GOA(n) is coupled to the light emission control line EML(n) driving the nth row of pixel circuits.
  • the timing controller may provide grayscale values and control signals suitable for the specification of the data driver to the data driver, and may provide a clock signal suitable for the specification of the gate driving circuit, a scan start signal, An emission stop signal and the like are supplied to the gate drive circuit.
  • the data driver may generate data voltages to be supplied to the data lines DL( 1 ) to DL(m) using gray values and control signals received from the timing controller. For example, the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data lines DL( 1 ) to DL(m) in units of pixel rows.
  • a plurality of cascaded first shift register units of the gate driving circuit may generate scan signals to be supplied to the scan lines GL(0) to GL(n) by receiving a clock signal, a scan start signal, etc. from the timing controller .
  • a plurality of cascaded second shift register units of the gate drive circuit can generate light emission control to be supplied to the light emission control lines EML(1) to EML(n) by receiving a clock signal, an emission stop signal, etc. from the timing controller. Signal.
  • the gate driving circuit only needs to provide the scanning signal and the light emitting control signal to the pixel circuit, which has a simple structure and good signal stability, which is conducive to realizing a narrow border design.
  • FIG. 16 is another schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • the gate driving circuit includes: a first group of shift register units 121 and a second group of shift register units 122 .
  • the first group of shift register units 121 includes a plurality of cascaded first shift register units G_GOA configured to generate scan signals;
  • the second group of shift register units 122 includes a plurality of cascaded second shift register units EM_GOA, Configured to generate a light control signal.
  • the first set of shift register units 121 and the second set of shift register units 122 may be located on opposite sides of the display area.

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Abstract

一种像素电路，包括：驱动子电路、数据写入子电路、阈值补偿子电路、存储子电路、发光控制子电路、第一初始化子电路和第二初始化子电路。数据写入子电路配置为在扫描线的控制下，将数据线提供的数据信号传输到第三节点。阈值补偿子电路配置为在扫描线的控制下，将第一节点和第二节点导通，以将驱动子电路的阈值电压写入存储子电路。发光控制子电路配置为在发光控制线的控制下，将第一电源线和第二节点导通，以及将第三节点和第四节点导通。第一初始化子电路配置为在复位线的控制下，将第一电源线和第一节点导通。第二初始化子电路配置为在复位线的控制下，将参考电压线和第四节点导通，以及在扫描线的控制下，将参考电压线和第四节点导通。

Description

像素电路及其驱动方法、显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种像素电路及其驱动方法、显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)具有超薄、大视角、主动发光、高亮度、发光颜色连续可调、成本低、响应速度快、低功耗、工作温度范围宽及可柔性显示等优点，已逐渐成为极具发展前景的下一代显示技术，并且受到越来越多的关注。依据驱动方式的不同，OLED可以分为无源矩阵驱动(PM，Passive Matrix)型和有源矩阵驱动(AM，Active Matrix)型两种，AMOLED是电流驱动器件，采用独立的薄膜晶体管(TFT，Thin Film Transistor)控制每个子像素，每个子像素皆可以连续且独立的驱动发光。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种像素电路及其驱动方法、显示装置。
一方面，本公开实施例提供一种像素电路，用于驱动发光元件发光，包括：驱动子电路、数据写入子电路、阈值补偿子电路、存储子电路、发光控制子电路、第一初始化子电路和第二初始化子电路。所述驱动子电路，与第一节点、第二节点和第三节点耦接，配置为在第一节点的控制下，向第三节点提供驱动电流。所述数据写入子电路，与数据线、扫描线和第三节点耦接，配置为在扫描线的控制下，将数据线提供的数据信号传输到第三节点。所述阈值补偿子电路，与扫描线、第一节点和第二节点耦接，配置为在扫描线的控制下，将第一节点和第二节点导通，以将所述驱动子电路的阈值电压写入 所述存储子电路。所述存储子电路，与第一节点和第四节点耦接。所述发光控制子电路，与发光控制线、第一电源线、第二节点、第三节点和第四节点耦接，配置为在发光控制线的控制下，将第一电源线和第二节点导通，以及将第三节点和第四节点导通。所述第一初始化子电路，与复位线、第一电源线和第一节点耦接，配置为在复位线的控制下，将第一电源线和第一节点导通。所述第二初始化子电路，与扫描线、复位线、参考电压线和第四节点耦接，配置为在复位线的控制下，将参考电压线和第四节点导通，以及在扫描线的控制下，将参考电压线和第四节点导通。所述发光元件的第一极与第四节点耦接，发光元件的第二极与第二电源线耦接。
在一些示例性实施方式中，位于第n行的像素电路耦接的复位线与驱动第n-1行像素电路的扫描线耦接，其中，n为正整数。
在一些示例性实施方式中，像素电路还包括：稳压子电路，与扫描线和第四节点耦接。
在一些示例性实施方式中，所述稳压子电路包括：稳压电容；所述稳压电容的第一端与第四节点耦接，所述稳压电容的第二端与扫描线耦接。
在一些示例性实施方式中，所述驱动子电路，包括：驱动晶体管；所述驱动晶体管的控制极与第一节点耦接，所述驱动晶体管的第一极与第二节点耦接，所述驱动晶体管的第二极与第三节点耦接。
在一些示例性实施方式中，所述第一初始化子电路，包括：第一初始化晶体管；所述第一初始化晶体管的控制极与复位线耦接，所述第一初始化晶体管的第一极与第一电源线耦接，所述第一初始化晶体管的第二极与第一节点耦接。
在一些示例性实施方式中，所述第二初始化子电路，包括：第二初始化晶体管和第三初始化晶体管。所述第二初始化晶体管的控制极与复位线耦接，所述第二初始化晶体管的第一极与参考电压线耦接，所述第二初始化晶体管的第二极与第四节点耦接。所述第三初始化晶体管的控制极与扫描线耦接，所述第三初始化晶体管的第一极与参考电压线耦接，所述第三初始化晶体管的第二极与第四节点耦接。
在一些示例性实施方式中，所述阈值补偿子电路，包括：阈值补偿晶体管；所述阈值补偿晶体管的控制极与扫描线耦接，所述阈值补偿晶体管的第一极与第一节点耦接，所述阈值补偿晶体管的第二极与第二节点耦接。
在一些示例性实施方式中，所述发光控制子电路，包括：第一发光控制晶体管和第二发光控制晶体管。所述第一发光控制晶体管的控制极与发光控制线耦接，所述第一发光控制晶体管的第一极与第一电源线耦接，所述第一发光控制晶体管的第二极与第二节点耦接。所述第二发光控制晶体管的控制极与发光控制线耦接，所述第二发光控制晶体管的第一极与第三节点耦接，所述第二发光控制晶体管的第二极与第四节点耦接。
在一些示例性实施方式中，所述数据写入子电路包括：数据写入晶体管；所述数据写入晶体管的控制极与扫描线耦接，所述数据写入晶体管的第一极与数据线耦接，所述数据写入晶体管的第二极与第三节点耦接。
在一些示例性实施方式中，所述存储子电路，包括：存储电容；所述存储电容的第一端与第一节点耦接，所述存储电容的第二端与第四节点耦接。
在一些示例性实施方式中，所述驱动子电路，包括：驱动晶体管；所述第一初始化子电路，包括：第一初始化晶体管；所述第二初始化子电路，包括：第二初始化晶体管和第三初始化晶体管；所述阈值补偿子电路，包括：阈值补偿晶体管；所述发光控制子电路，包括：第一发光控制晶体管和第二发光控制晶体管；所述数据写入子电路包括：数据写入晶体管；所述存储子电路，包括：存储电容。所述驱动晶体管的控制极与第一节点耦接，所述驱动晶体管的第一极与第二节点耦接，所述驱动晶体管的第二极与第三节点耦接。所述第一初始化晶体管的控制极与复位线耦接，所述第一初始化晶体管的第一极与第一电源线耦接，所述第一初始化晶体管的第二极与第一节点耦接。所述第二初始化晶体管的控制极与复位线耦接，所述第二初始化晶体管的第一极与参考电压线耦接，所述第二初始化晶体管的第二极与第四节点耦接。所述第三初始化晶体管的控制极与扫描线耦接，所述第三初始化晶体管的第一极与参考电压线耦接，所述第三初始化晶体管的第二极与第四节点耦接。所述阈值补偿晶体管的控制极与扫描线耦接，所述阈值补偿晶体管的第一极与第一节点耦接，所述阈值补偿晶体管的第二极与第二节点耦接。所述 第一发光控制晶体管的控制极与发光控制线耦接，所述第一发光控制晶体管的第一极与第一电源线耦接，所述第一发光控制晶体管的第二极与第二节点耦接。所述第二发光控制晶体管的控制极与发光控制线耦接，所述第二发光控制晶体管的第一极与第三节点耦接，所述第二发光控制晶体管的第二极与第四节点耦接。所述数据写入晶体管的控制极与扫描线耦接，所述数据写入晶体管的第一极与数据线耦接，所述数据写入晶体管的第二极与第三节点耦接。所述存储电容的第一端与第一节点耦接，所述存储电容的第二端与第四节点耦接。
在一些示例性实施方式中，所述驱动晶体管、第一初始化晶体管、第二初始化晶体管、第三初始化晶体管、阈值补偿晶体管、第一发光控制晶体管、第二发光控制晶体管和数据写入晶体管均为N型晶体管。
在一些示例性实施方式中，所述第一初始化晶体管和阈值补偿晶体管为双栅晶体管。
另一方面，本公开实施例提供一种像素电路的驱动方法，应用于如上所述的像素电路，包括：在初始化阶段，在复位线的控制下，第一初始化子电路将第一电源线和第一节点导通，第二初始化子电路将参考电压线和第四节点导通；在写入阶段，在扫描线的控制下，数据写入子电路将数据线提供的数据信号传输到第三节点，阈值补偿子电路将第一节点和第二节点导通，以将驱动子电路的阈值电压写入存储子电路，以及第二初始化子电路将参考电压线和第四节点导通；在发光阶段，在发光控制线的控制下，发光控制子电路将第一电源线和第二节点导通，并将第三节点和第四节点导通，以将驱动子电路输出的驱动电流传输至发光元件。
另一方面，本公开实施例提供一种显示装置，包括如上所述的像素电路。
在一些示例性实施方式中，显示装置还包括：栅极驱动电路。所述栅极驱动电路包括：多个级联的第一移位寄存器单元和多个级联的第二移位寄存器单元。第n级第一移位寄存器单元的输出端与驱动第n行像素电路的扫描线耦接；第n-1级第一移位寄存器单元的输出端与驱动第n行像素电路的复位线耦接；第n级第二移位寄存器单元的输出端与驱动第n行像素电路的发光控制线耦接；其中，n为正整数。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的像素电路的结构示意图；
图2为本公开至少一实施例的像素电路的另一结构示意图；
图3为本公开至少一实施例的像素电路的驱动子电路的等效电路图；
图4为本公开至少一实施例的像素电路的第一初始化子电路的等效电路图；
图5为本公开至少一实施例的像素电路的第二初始化子电路的等效电路图；
图6为本公开至少一实施例的像素电路的阈值补偿子电路的等效电路图；
图7为本公开至少一实施例的像素电路的发光控制子电路的等效电路图；
图8为本公开至少一实施例的像素电路的数据写入子电路的等效电路图；
图9为本公开至少一实施例的像素电路的存储子电路的等效电路图；
图10为本公开至少一实施例的像素电路的稳压子电路的等效电路图；
图11为本公开至少一实施例的像素电路的等效电路图；
图12为图11提供的像素电路的工作时序图；
图13为本公开至少一实施例的像素电路的另一等效电路图；
图14为本公开至少一实施例的像素电路的驱动方法的流程图；
图15为本公开至少一实施例的显示装置的示意图；
图16为本公开至少一实施例的显示装置的另一示意图。
具体实施方式
下文将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“耦接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。其中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管 等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏极)与源电极(源电极端子、源区域或源极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，为区分晶体管除栅电极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源电极或者漏电极，第二极可以为漏电极或源电极，另外，将晶体管的栅电极称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，可以包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，可以包括85°以上且95°以下的角度的状态。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
OLED发光元件采用电流驱动方式实现发光，因此，对驱动晶体管(DTFT，Driving TFT)和OLED发光元件的电流稳定性要求较高。然而，受到制备工艺的影响，驱动晶体管输出的电流稳定性不佳，而且在温度等因素作用下，驱动晶体管的阈值电压Vth会发生偏移，从而影响显示装置的显示效果和寿命。
本公开实施例提供一种像素电路及其驱动方法、显示装置，实现对驱动子电路的阈值电压进行补偿，避免阈值电压对发光元件的驱动电流的影响，从而提高显示效果。
图1为本公开至少一实施例的像素电路的结构示意图。如图1所示，本示例性实施例提供的像素电路用于驱动发光元件发光。本实施例的像素电路包括：驱动子电路、数据写入子电路、阈值补偿子电路、存储子电路、发光 控制子电路、第一初始化子电路以及第二初始化子电路。其中，驱动子电路，与第一节点N1、第二节点N2和第三节点N3耦接，配置为在第一节点N1的控制下，向第三节点N3提供驱动电流。数据写入子电路，与数据线DL、扫描线GL和第三节点N3耦接，配置为在扫描线GL的控制下，将数据线DL提供的数据信号传输到第三节点N3。阈值补偿子电路，与扫描线GL、第一节点N1和第二节点N2耦接，配置为在扫描线GL的控制下，将第一节点N1和第二节点N2导通，以将驱动子电路的阈值电压写入存储子电路。存储子电路与第一节点N1和第四节点N4耦接。发光控制子电路，与发光控制线EML、第一电源线PL1、第二节点N2、第三节点N3和第四节点N4耦接，配置为在发光控制线EML的控制下，将第一电源线PL1和第二节点N2导通，并将第三节点N3和第四节点N4导通。第一初始化子电路，与复位线RST、第一电源线PL1和第一节点N1耦接，配置为在复位线RST的控制下，将第一电源线PL1和第一节点N1导通。第二初始化子电路，与扫描线GL、复位线RST、参考电压线REF和第四节点N4耦接，配置为在复位线RST的控制下，将参考电压线REF和第四节点N4导通，以及在扫描线GL的控制下，将参考电压线REF和第四节点N4导通。发光元件的第一极与第四节点N4耦接，发光元件的第二极与第二电源线PL2耦接。
在一些示例性实施方式中，发光元件可以为有机发光二极管(OLED)。发光元件的第一极可以为阳极，第二极可以为阴极。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一电源线PL1可以持续提供高电平信号，例如，第一电源线PL1提供第一电源信号ELVDD。第二电源线PL2可以持续提供低电平信号，例如，第二电源线PL2提供第二电源信号ELVSS。
本实施例提供的像素电路可以实现对驱动子电路的阈值电压的内部实时补偿，从而避免驱动子电路的阈值电压漂移导致的显示不良。
在一些示例性实施方式中，位于第n行的像素电路耦接的复位线与驱动第n-1行像素电路的扫描线耦接，其中，n为正整数。在本示例性实施方式中，驱动第n-1行像素电路的扫描线可以复用为驱动第n行像素电路的复位线，给第n行像素电路提供复位信号。如此一来，栅极驱动电路只需向像素 电路提供两种不同的栅极驱动信号(即扫描信号和发光控制信号)，有利于简化栅极驱动电路的结构，提高信号稳定性，并有利于实现显示装置的窄边框。
图2为本公开至少一实施例的像素电路的另一结构示意图。在一些示例性实施方式中，如图2所示，本示例性实施例提供的像素电路还包括：稳压子电路。稳压子电路与扫描线GL和第四节点N4耦接。稳压子电路配置为维持第四节点N4的电压，防止晶体管的漏电流影响阈值电压的补偿效果。
图3为本公开至少一实施例的像素电路的驱动子电路的等效电路图。在一些示例性实施方式中，如图3所示，像素电路中的驱动子电路包括：驱动晶体管M8。驱动晶体管M8的控制极与第一节点N1耦接，驱动晶体管M8的第一极与第二节点N2耦接，驱动晶体管M8的第二极与第三节点N3耦接。驱动晶体管M8配置为在第一节点N1的控制下，向第三节点N3提供驱动电流。
图3示出了驱动子电路的示例性结构，本领域技术人员容易理解的是，驱动子电路的实现方式并不限定于此，只要能够实现其功能即可。
图4为本公开至少一实施例的像素电路的第一初始化子电路的等效电路图。在一些示例性实施方式中，如图4所示，像素电路中的第一初始化子电路包括：第一初始化晶体管M1。第一初始化晶体管M1的控制极与复位线RST耦接，第一初始化晶体管M1的第一极与第一电源线PL1耦接，第一初始化晶体管M1的第二极与第一节点N1耦接。
图4示出了第一初始化子电路的示例性结构，本领域技术人员容易理解的是，第一初始化子电路的实现方式并不限定于此，只要能够实现其功能即可。
图5为本公开至少一实施例的像素电路的第二初始化子电路的等效电路图。在一些示例性实施方式中，如图5所示，像素电路中的第二初始化子电路包括：第二初始化晶体管M3和第三初始化晶体管M4。第二初始化晶体管M3的控制极与复位线RST耦接，第二初始化晶体管M3的第一极与参考电压线REF耦接，第二初始化晶体管M3的第二极与第四节点N4耦接。第三初始化晶体管M4的控制极与扫描线GL耦接，第三初始化晶体管M4的 第一极与参考电压线REF耦接，第三初始化晶体管M4的第二极与第四节点N4耦接。
图5示出了第二初始化子电路的示例性结构，本领域技术人员容易理解的是，第二初始化子电路的实现方式并不限定于此，只要能够实现其功能即可。
图6为本公开至少一实施例的像素电路的阈值补偿子电路的等效电路图。在一些示例性实施方式中，如图6所示，像素电路中的阈值补偿子电路包括：阈值补偿晶体管M2。阈值补偿晶体管M2的控制极与扫描线GL耦接，阈值补偿晶体管M2的第一极与第一节点N1耦接，阈值补偿晶体管M2的第二极与第二节点N2耦接。
图6示出了阈值补偿子电路的示例性结构，本领域技术人员容易理解的是，阈值补偿子电路的实现方式并不限定于此，只要能够实现其功能即可。
图7为本公开至少一实施例的像素电路的发光控制子电路的等效电路图。在一些示例性实施方式中，如图7所示，像素电路中的发光控制子电路包括：第一发光控制晶体管M5和第二发光控制晶体管M6。第一发光控制晶体管M5的控制极与发光控制线EML耦接，第一发光控制晶体管M5的第一极与第一电源线PL1耦接，第一发光控制晶体管M5的第二极与第二节点N2耦接。第二发光控制晶体管M6的控制极与发光控制线EML耦接，第二发光控制晶体管M6的第一极与第三节点N3耦接，第二发光控制晶体管M6的第二极与第四节点N4耦接。
图7示出了发光控制子电路的示例性结构，本领域技术人员容易理解的是，发光控制子电路的实现方式并不限定于此，只要能够实现其功能即可。
图8为本公开至少一实施例的像素电路的数据写入子电路的等效电路图。在一些示例性实施方式中，如图8所示，像素电路中的数据写入子电路包括：数据写入晶体管M7。数据写入晶体管M7的控制极与扫描线GL耦接，数据写入晶体管M7的第一极与数据线DL耦接，数据写入晶体管M7的第二极与第三节点N3耦接。
图8示出了数据写入子电路的示例性结构，本领域技术人员容易理解的 是，数据写入子电路的实现方式并不限定于此，只要能够实现其功能即可。
图9为本公开至少一实施例的像素电路的存储子电路的等效电路图。在一些示例性实施方式中，如图9所示，像素电路中的存储子电路包括：存储电容C1。存储电容C1的第一端与第一节点N1耦接，存储电容C1的第二端与第四节点N4耦接。
图9示出了存储子电路的示例性结构，本领域技术人员容易理解的是，存储子电路的实现方式并不限定于此，只要能够实现其功能即可。
图10为本公开至少一实施例的像素电路的稳压子电路的等效电路图。在一些示例性实施方式中，如图10所示，像素电路中的稳压子电路包括：稳压电容C2。稳压电容C2的第一端与第四节点N4耦接，稳压电容C2的第二端与扫描线GL耦接。
图10示出了稳压子电路的示例性结构，本领域技术人员容易理解的是，稳压子电路的实现方式并不限定于此，只要能够实现其功能即可。
图11为本公开至少一实施例的像素电路的等效电路图。在一些示例性实施方式中，如图11所示，驱动子电路包括：驱动晶体管M8；第一初始化子电路包括：第一初始化晶体管M1；阈值补偿子电路包括：阈值补偿晶体管M2；第二初始化子电路包括：第二初始化晶体管M3和第三初始化晶体管M4；发光控制子电路包括：第一发光控制晶体管M5和第二发光控制晶体管M6；数据写入子电路包括：数据写入晶体管M7；存储子电路包括：存储电容C1；稳压子电路包括：稳压电容C2。
在一些示例性实施方式中，如图11所示，驱动晶体管M8的控制极与第一节点N1耦接，驱动晶体管M8的第一极与第二节点N2耦接，驱动晶体管M8的第二极与第三节点N3耦接。第一初始化晶体管M1的控制极与复位线RST耦接，第一初始化晶体管M1的第一极与第一电源线PL1耦接，第一初始化晶体管M1的第二极与第一节点N1耦接。第二初始化晶体管M3的控制极与复位线RST耦接，第二初始化晶体管M3的第一极与参考电压线REF耦接，第二初始化晶体管M3的第二极与第四节点N4耦接。第三初始化晶体管M4的控制极与扫描线GL耦接，第三初始化晶体管M4的第一极与参考电压线REF耦接，第三初始化晶体管M4的第二极与第四节点N4耦接。 阈值补偿晶体管M2的控制极与扫描线GL耦接，阈值补偿晶体管M2的第一极与第一节点N1耦接，阈值补偿晶体管M2的第二极与第二节点N2耦接。第一发光控制晶体管M5的控制极与发光控制线EML耦接，第一发光控制晶体管M5的第一极与第一电源线PL1耦接，第一发光控制晶体管M5的第二极与第二节点N2耦接。第二发光控制晶体管M6的控制极与发光控制线EML耦接，第二发光控制晶体管M6的第一极与第三节点N3耦接，第二发光控制晶体管M6的第二极与第四节点N4耦接。数据写入晶体管M7的控制极与扫描线GL耦接，数据写入晶体管M7的第一极与数据线DL耦接，数据写入晶体管M7的第二极与第三节点N3耦接。存储电容C1的第一端与第一节点N1耦接，存储电容C1的第二端与第四节点N4耦接。稳压电容C2的第一端与第四节点N4耦接，稳压电容C2的第二端与扫描线GL耦接。发光元件EL的第一极与第四节点N4耦接，发光元件EL的第二极与第二电源线PL2耦接。
在一些示例性实施方式中，像素电路中的晶体管M1至M8可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，像素电路中的多个晶体管可以包括P型晶体管和N型晶体管。本实施例对此并不限定。
在一些示例性实施方式中，像素电路中的晶体管M1至M8可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
下面通过图11提供的像素电路的工作过程进一步说明本实施例的方案。
以图11提供的像素电路中的晶体管均为N型薄膜晶体管为例，对图11 所示的像素电路的工作过程进行示例性说明。图12为图11所示的像素电路的工作时序图。如图11所示，本示例性实施例涉及的像素电路包括：8个晶体管单元(即晶体管M1至M8)、2个电容单元(即存储电容C1和稳压电容C2)、5个输入端(即数据线DL、扫描线GL、复位线RST、发光控制线EML、参考电压线REF)、2个电源端(即第一电源线PL1和第二电源线PL2)。其中，第一电源线PL1持续提供高电平信号，例如，第一电源信号ELVDD，第二电源线PL2持续提供低电平信号，例如，第二电源信号ELVSS。
在本示例性实施方式中，驱动第n行像素电路的扫描线GL(n)配置为提供扫描信号G(n)。驱动第n-1行像素电路的扫描线GL(n-1)可以复用为驱动第n行像素电路的复位线RST，配置为给第n行像素电路提供复位信号。即，第n行像素电路的复位线RST提供的复位信号即为扫描信号G(n-1)。其中，n为正整数。
如图12所示，在一帧时间段内，像素电路的工作过程包括以下阶段：初始化阶段T1、写入阶段T2和发光阶段T3。
第一阶段T1，即初始化阶段，如图12所示，发光控制线EML提供的发光控制信号EM为低电平，第一发光控制晶体管M5和第二发光控制晶体管M6断开；扫描线GL提供的扫描信号G(n)为低电平，阈值补偿晶体管M2、数据写入晶体管M7和第三初始化晶体管M4断开；复位线RST提供的复位信号(即扫描信号G(n-1))为高电平，第一初始化晶体管M1和第二初始化晶体管M3导通。第一初始化晶体管M1和第二初始化晶体管M3导通，对存储电容C1的两端(即第一节点N1和第四节点N4)进行初始化。第一初始化晶体管M1将第一节点N1与第一电源线PL1导通，使得第一节点N1的电压V N1＝ELVDD，ELVDD为第一电源线PL1提供的第一电源信号；第二初始化晶体管M3将第四节点N4和参考电压线REF导通，使得第四节点N4的电压V N4＝Vref，Vref为参考电压线REF提供的参考电压。
第二阶段T2，即写入阶段，如图12所示，发光控制线EML提供的发光控制信号EM为低电平，第一发光控制晶体管M5和第二发光控制晶体管M6断开；复位线RST提供的复位信号(即扫描信号G(n-1))为低电平，第一初始化晶体管M1和第二初始化晶体管M3断开；扫描线GL提供的扫 描信号G(n)为高电平，阈值补偿晶体管M2、第三初始化晶体管M4和数据写入晶体管M7导通。阈值补偿晶体管M2和数据写入晶体管M7导通，使得数据线DL通过数据写入晶体管M7、驱动晶体管M5和阈值补偿晶体管M2与第一节点N1建立通路。阈值补偿晶体管M2使得第一节点N1与第二节点N2导通，驱动晶体管M8形成二极管结构。第一节点N1的电荷经过阈值补偿晶体管M2、驱动晶体管M3和数据写入晶体管M7向数据线DL流动，直至第一节点N1的电压V N1＝Vdata+Vth，其中，Vth为驱动晶体管M8的阈值电压，Vdata为数据线DL传输的数据信号DA的电压。第三初始化晶体管M4导通，将参考电压线REF与第四节点N4导通，使得第四节点N4的电压维持为参考电压Vref，即V N4＝Vref。
在本阶段中，虽然驱动晶体管M8会导通并产生驱动电流，由于第二发光控制晶体管M6断开，因此，该驱动电流无法流入发光元件EL，发光元件EL不发光。
第三阶段T3，即发光阶段，如图12所示，复位线RST提供的复位信号(即扫描信号G(n-1))为低电平，第一初始化晶体管M1和第二初始化晶体管M3断开；扫描线GL提供的扫描信号G(n)为低电平，阈值补偿晶体管M2、第三初始化晶体管M4和数据写入晶体管M7断开；发光控制线EML提供的发光控制信号EM为高电平，第一发光控制晶体管M5和第二发光控制晶体管M6导通。在存储电容C1的电压保持作用下，驱动晶体管M8的栅源电压Vgs＝V N1-V N4＝Vdata+Vth-Vref。驱动晶体管M8产生的驱动电流经过第二发光控制晶体管M6流入发光元件EL。驱动晶体管M8输出的驱动电流Id可以通过以下式子得到：
Figure PCTCN2021095450-appb-000001
其中，
Figure PCTCN2021095450-appb-000002
μ为驱动晶体管的沟道迁移率，W和L分别为驱动晶体管的沟道宽度和沟道长度，C ox为驱动晶体管单位面积的沟道电容。Vgs为驱动晶体管的栅源电压差。Vth为驱动晶体管的阈值电压。Vdata为数据线DL传输的数据信号DA的电压。Vref为参考电压线REF提供的参考电压。
由上述式子可见，驱动电流与驱动晶体管的阈值电压Vth无关，只取决 于数据线DL提供的数据信号DA的电压和参考电压线REF提供的参考电压Vref，从而消除了驱动晶体管的阈值电压对驱动电流的影响，进而确保了显示装置的显示亮度均匀，提高了显示效果。
在本示例性实施方式中，利用包括八个晶体管和两个电容的像素电路可以实现驱动晶体管的阈值电压的存储和补偿功能，从而消除了驱动晶体管的阈值电压对驱动电流的影响。
在本示例性实施方式中，稳压电容C2的两端分别连接第四节点N2和扫描线GL，可以起到稳定第四节点N4电位的作用，防止晶体管的漏电流影响补偿效果。
在一些示例性实施方式中，数据线DL传输的数据信号DA的电压可以约为0V至5V，驱动晶体管的阈值电压Vth可以约为-1V至1V。然而，本实施例对此并不限定。
本示例性实施例的像素电路可以实现阈值电压内部补偿，从而提高显示效果。而且，通过复用扫描信号作为复位信号，可以简化栅极驱动电路的结构，有利于实现窄边框设计。另外，本示例性实施方式的像素电路采用N型薄膜晶体管，可以改善由于P型晶体管迟滞导致的短期残像等问题。
图13为本公开至少一实施例的像素电路的另一等效电路图。在一些示例性实施方式中，如图13所示，第一初始化晶体管M1和阈值补偿晶体管M2可以为双栅晶体管。在本示例中，第一初始化晶体管M1包括两个第一子晶体管M1_1和M1_2。第一子晶体管M1_1的控制极和第一子晶体管M1_2的控制极耦接，并与复位线RST耦接；第一子晶体管M1_1的第一极与第一节点N1耦接，第一子晶体管M1_1的第二极与第一子晶体管M1_2的第一极耦接，第一子晶体管M1_2的第二极与第一电源线PL1耦接。阈值补偿晶体管M2包括两个第二子晶体管M2_1和M2_2。第二子晶体管M2_1的控制极和第二子晶体管M2_2的控制极耦接，并与扫描线GL耦接；第二子晶体管M2_1的第一极与第一节点N1耦接，第二子晶体管M2_1的第二极与第二子晶体管M2_2的第一极耦接，第二子晶体管M2_2的第二极与第二节点N2耦接。
本示例性实施例通过将第一初始化晶体管和阈值补偿晶体管采用双栅结构，可以降低在初始化阶段和发光阶段，阈值补偿晶体管对第一节点的漏电， 以及降低在写入阶段和发光阶段，第一初始化晶体管对第一节点的漏电，防止晶体管的漏电流影响补偿效果。
关于本实施例的像素电路的其余结构和工作时序可以参照前述实施例的说明，故于此不再赘述。
本公开至少一实施例还提供一种像素电路的驱动方法。图14为本公开至少一实施例的像素电路的驱动方法的流程图。如图14所示，本示例性实施例的像素电路的驱动方法包括以下步骤：
步骤100、在初始化阶段，在复位线的控制下，第一初始化子电路将第一电源线和第一节点导通，第二初始化子电路将参考电压线和第四节点导通；
步骤200、在写入阶段，在扫描线的控制下，数据写入子电路将数据线提供的数据信号传输到第三节点，阈值补偿子电路将第一节点和第二节点导通，以将驱动子电路的阈值电压写入存储子电路，以及第二初始化子电路将参考电压线和第四节点导通；
步骤300、在发光阶段，在发光控制线的控制下，发光控制子电路将第一电源线和第二节点导通，并将第三节点和第四节点导通，以将驱动子电路输出的驱动电流传输至发光元件。
本示例性实施例提供的像素电路的驱动方法用于前述实施例提供的像素电路中，其实现原理和效果类似，故在此不再赘述。
本公开至少一实施例还提供一种显示装置，包括：像素电路。关于像素电路的实现原理和效果与前述实施例类似，故在此不再赘述。
在一些示例性实施方式中，显示装置可以包括显示基板，像素电路可以设置于显示基板上。显示基板可以为OLED显示基板。显示装置可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
在一些示例性实施方式中，显示装置还包括：栅极驱动电路。栅极驱动电路包括：多个级联的第一移位寄存器单元和多个级联的第二移位寄存器单元。第n级第一移位寄存器单元的输出端与驱动第n行像素电路的扫描线耦 接；第n-1级第一移位寄存器单元的输出端与驱动第n行像素电路的复位线耦接；第n级第二移位寄存器单元的输出端与驱动第n行像素电路的发光控制线耦接；其中，n为正整数。
图15为本公开至少一实施例的显示装置的示意图。在一些示例性实施方式中，如图15所示，显示装置包括：多个像素电路10、多条扫描线(例如，扫描线GL(0)至GL(n))、多条发光控制线(例如，发光控制线EML(1)至EML(n))、多条数据线(例如，数据线DL(1)至DL(m))、栅极驱动电路12a和12b、数据驱动器以及时序控制器。其中，n和m均为正整数。
在一些示例中，多个像素电路10位于显示装置的显示区域，栅极驱动电路12a和栅极驱动电路12b位于显示区域的相对两侧，例如，栅极驱动电路12a位于显示区域的左侧，栅极驱动电路12b位于显示区域的右侧。以栅极驱动电路12a为例进行说明。栅极驱动电路12a包括：多个级联的第一移位寄存器单元G_GOA、多个级联的第二移位寄存器单元EM_GOA。第n级第一移位寄存器单元G_GOA(n)的输出端与驱动第n行像素电路的扫描线GL(n)耦接；第n-1级第一移位寄存器单元G_GOA(n-1)的输出端与驱动第n行像素电路的复位线耦接。第n级第二移位寄存器单元EM_GOA(n)的输出端与驱动第n行像素电路的发光控制线EML(n)耦接。关于栅极驱动电路12b的结构可以参照栅极驱动电路12a的结构，故于此不再赘述。
在一些示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于栅极驱动电路的规格的时钟信号、扫描起始信号、发射停止信号等提供到栅极驱动电路。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据线DL(1)至DL(m)的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据线DL(1)至DL(m)。栅极驱动电路的多个级联的第一移位寄存器单元可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描线GL(0)至GL(n)的扫描信号。栅极驱动电路的多个级联的第二移位寄存器单元可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供 到发光控制线EML(1)至EML(n)的发光控制信号。
在本示例性实施方式中，栅极驱动电路只需提供扫描信号和发光控制信号给像素电路，结构简单，信号稳定性好，有利于实现窄边框设计。
图16为本公开至少一实施例的显示装置的另一示意图。在一些示例性实施方式中，如图16所示，栅极驱动电路包括：第一组移位寄存器单元121和第二组移位寄存器单元122。第一组移位寄存器单元121包括多个级联的第一移位寄存器单元G_GOA，配置为产生扫描信号；第二组移位寄存器单元122包括多个级联的第二移位寄存器单元EM_GOA，配置为产生发光控制信号。第一组移位寄存器单元121和第二组移位寄存器单元122可以位于显示区域的相对两侧。
关于本实施例的显示装置的其余结构可以参照图15所示实施例的描述，故于此不再赘述。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (17)

  1. 一种像素电路，用于驱动发光元件发光，所述像素电路包括：
    驱动子电路、数据写入子电路、阈值补偿子电路、存储子电路、发光控制子电路、第一初始化子电路和第二初始化子电路；
    所述驱动子电路，与第一节点、第二节点和第三节点耦接，配置为在第一节点的控制下，向第三节点提供驱动电流；
    所述数据写入子电路，与数据线、扫描线和第三节点耦接，配置为在扫描线的控制下，将数据线提供的数据信号传输到第三节点；
    所述阈值补偿子电路，与扫描线、第一节点和第二节点耦接，配置为在扫描线的控制下，将第一节点和第二节点导通，以将所述驱动子电路的阈值电压写入所述存储子电路；
    所述存储子电路，与第一节点和第四节点耦接；
    所述发光控制子电路，与发光控制线、第一电源线、第二节点、第三节点和第四节点耦接，配置为在发光控制线的控制下，将第一电源线和第二节点导通，以及将第三节点和第四节点导通；
    所述第一初始化子电路，与复位线、第一电源线和第一节点耦接，配置为在复位线的控制下，将第一电源线和第一节点导通；
    所述第二初始化子电路，与扫描线、复位线、参考电压线和第四节点耦接，配置为在复位线的控制下，将参考电压线和第四节点导通，以及在扫描线的控制下，将参考电压线和第四节点导通；
    所述发光元件的第一极与第四节点耦接，发光元件的第二极与第二电源线耦接。
  2. 根据权利要求1所述的像素电路，其中，位于第n行的像素电路耦接的复位线与驱动第n-1行像素电路的扫描线耦接，其中，n为正整数。
  3. 根据权利要求1或2所述的像素电路，还包括：稳压子电路，与扫描线和第四节点耦接。
  4. 根据权利要求3所述的像素电路，其中，所述稳压子电路包括：稳压 电容；所述稳压电容的第一端与第四节点耦接，所述稳压电容的第二端与扫描线耦接。
  5. 根据权利要求1至4中任一项所述的像素电路，其中，所述驱动子电路，包括：驱动晶体管；所述驱动晶体管的控制极与第一节点耦接，所述驱动晶体管的第一极与第二节点耦接，所述驱动晶体管的第二极与第三节点耦接。
  6. 根据权利要求1至4中任一项所述的像素电路，其中，所述第一初始化子电路，包括：第一初始化晶体管；所述第一初始化晶体管的控制极与复位线耦接，所述第一初始化晶体管的第一极与第一电源线耦接，所述第一初始化晶体管的第二极与第一节点耦接。
  7. 根据权利要求1至4中任一项所述的像素电路，其中，所述第二初始化子电路，包括：第二初始化晶体管和第三初始化晶体管；
    所述第二初始化晶体管的控制极与复位线耦接，所述第二初始化晶体管的第一极与参考电压线耦接，所述第二初始化晶体管的第二极与第四节点耦接；
    所述第三初始化晶体管的控制极与扫描线耦接，所述第三初始化晶体管的第一极与参考电压线耦接，所述第三初始化晶体管的第二极与第四节点耦接。
  8. 根据权利要求1至4中任一项所述的像素电路，其中，所述阈值补偿子电路，包括：阈值补偿晶体管；所述阈值补偿晶体管的控制极与扫描线耦接，所述阈值补偿晶体管的第一极与第一节点耦接，所述阈值补偿晶体管的第二极与第二节点耦接。
  9. 根据权利要求1至4中任一项所述的像素电路，其中，所述发光控制子电路，包括：第一发光控制晶体管和第二发光控制晶体管；
    所述第一发光控制晶体管的控制极与发光控制线耦接，所述第一发光控制晶体管的第一极与第一电源线耦接，所述第一发光控制晶体管的第二极与第二节点耦接；
    所述第二发光控制晶体管的控制极与发光控制线耦接，所述第二发光控 制晶体管的第一极与第三节点耦接，所述第二发光控制晶体管的第二极与第四节点耦接。
  10. 根据权利要求1至4中任一项所述的像素电路，其中，所述数据写入子电路包括：数据写入晶体管；所述数据写入晶体管的控制极与扫描线耦接，所述数据写入晶体管的第一极与数据线耦接，所述数据写入晶体管的第二极与第三节点耦接。
  11. 根据权利要求1至4中任一项所述的像素电路，其中，所述存储子电路，包括：存储电容；所述存储电容的第一端与第一节点耦接，所述存储电容的第二端与第四节点耦接。
  12. 根据权利要求1至4中任一项所述的像素电路，其中，所述驱动子电路，包括：驱动晶体管；所述第一初始化子电路，包括：第一初始化晶体管；所述第二初始化子电路，包括：第二初始化晶体管和第三初始化晶体管；所述阈值补偿子电路，包括：阈值补偿晶体管；所述发光控制子电路，包括：第一发光控制晶体管和第二发光控制晶体管；所述数据写入子电路包括：数据写入晶体管；所述存储子电路，包括：存储电容；
    所述驱动晶体管的控制极与第一节点耦接，所述驱动晶体管的第一极与第二节点耦接，所述驱动晶体管的第二极与第三节点耦接；
    所述第一初始化晶体管的控制极与复位线耦接，所述第一初始化晶体管的第一极与第一电源线耦接，所述第一初始化晶体管的第二极与第一节点耦接；
    所述第二初始化晶体管的控制极与复位线耦接，所述第二初始化晶体管的第一极与参考电压线耦接，所述第二初始化晶体管的第二极与第四节点耦接；
    所述第三初始化晶体管的控制极与扫描线耦接，所述第三初始化晶体管的第一极与参考电压线耦接，所述第三初始化晶体管的第二极与第四节点耦接；
    所述阈值补偿晶体管的控制极与扫描线耦接，所述阈值补偿晶体管的第一极与第一节点耦接，所述阈值补偿晶体管的第二极与第二节点耦接；
    所述第一发光控制晶体管的控制极与发光控制线耦接，所述第一发光控制晶体管的第一极与第一电源线耦接，所述第一发光控制晶体管的第二极与第二节点耦接；
    所述第二发光控制晶体管的控制极与发光控制线耦接，所述第二发光控制晶体管的第一极与第三节点耦接，所述第二发光控制晶体管的第二极与第四节点耦接；
    所述数据写入晶体管的控制极与扫描线耦接，所述数据写入晶体管的第一极与数据线耦接，所述数据写入晶体管的第二极与第三节点耦接；
    所述存储电容的第一端与第一节点耦接，所述存储电容的第二端与第四节点耦接。
  13. 根据权利要求12所述的像素电路，其中，所述驱动晶体管、第一初始化晶体管、第二初始化晶体管、第三初始化晶体管、阈值补偿晶体管、第一发光控制晶体管、第二发光控制晶体管和数据写入晶体管均为N型晶体管。
  14. 根据权利要求12或13所述的像素电路，其中，所述第一初始化晶体管和阈值补偿晶体管为双栅晶体管。
  15. 一种像素电路的驱动方法，应用于如权利要求1至14中任一项所述的像素电路，所述驱动方法包括：
    在初始化阶段，在复位线的控制下，第一初始化子电路将第一电源线和第一节点导通，第二初始化子电路将参考电压线和第四节点导通；
    在写入阶段，在扫描线的控制下，数据写入子电路将数据线提供的数据信号传输到第三节点，阈值补偿子电路将第一节点和第二节点导通，以将驱动子电路的阈值电压写入存储子电路，以及第二初始化子电路将参考电压线和第四节点导通；
    在发光阶段，在发光控制线的控制下，发光控制子电路将第一电源线和第二节点导通，并将第三节点和第四节点导通，以将驱动子电路输出的驱动电流传输至发光元件。
  16. 一种显示装置，包括：如权利要求1至14中任一项所述的像素电路。
  17. 根据权利要求16所述的显示装置，还包括：栅极驱动电路；
    所述栅极驱动电路包括：多个级联的第一移位寄存器单元和多个级联的第二移位寄存器单元；
    第n级第一移位寄存器单元的输出端与驱动第n行像素电路的扫描线耦接；第n-1级第一移位寄存器单元的输出端与驱动第n行像素电路的复位线耦接；第n级第二移位寄存器单元的输出端与驱动第n行像素电路的发光控制线耦接；其中，n为正整数。
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