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WO2023005621A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2023005621A1
WO2023005621A1 PCT/CN2022/103892 CN2022103892W WO2023005621A1 WO 2023005621 A1 WO2023005621 A1 WO 2023005621A1 CN 2022103892 W CN2022103892 W CN 2022103892W WO 2023005621 A1 WO2023005621 A1 WO 2023005621A1
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WO
WIPO (PCT)
Prior art keywords
circuit
transistor
voltage
reset
terminal
Prior art date
Application number
PCT/CN2022/103892
Other languages
English (en)
French (fr)
Inventor
张振华
杨栋芳
曹席磊
郝学光
刘烺
冯靖伊
袁长龙
李小鑫
朱莉
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/273,239 priority Critical patent/US12300172B2/en
Priority to GB2314967.7A priority patent/GB2620507A/en
Publication of WO2023005621A1 publication Critical patent/WO2023005621A1/zh

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Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a driving method thereof, and a display panel.
  • Organic light-emitting diode Organic Light-Emitting Diode (Organic Light-Emitting Diode, OLED) display panel has thin, light, wide viewing angle, active light emission, continuously adjustable light color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range , simple production process, high luminous efficiency and flexible display, etc., are more and more widely used in display fields such as mobile phones, tablet computers, and digital cameras.
  • At least some embodiments of the present disclosure provide a pixel circuit, including a driving circuit, a data writing circuit, a storage circuit, and a first reset circuit; wherein, the driving circuit includes a control terminal, a first terminal, and a second terminal, and is configured In order to control the driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light; the data writing circuit is configured to write a data signal into the driving device under the control of the first scanning signal The control terminal of the circuit; the storage circuit is configured to store the data signal; the first reset circuit is configured to apply a first initialization voltage to the control terminal of the drive circuit under the control of a first reset control signal ; Wherein, each of the driving circuit and the data writing circuit includes an N-type thin film transistor, and the first reset circuit includes an N-type oxide thin film transistor.
  • the N-type thin film transistor included in the driving circuit is a first transistor; the gate of the first transistor serves as the control terminal of the driving circuit, and the The first pole of the first transistor serves as the first terminal of the driving circuit, and the second pole of the first transistor serves as the second terminal of the driving circuit.
  • the N-type thin film transistor included in the data writing circuit is a second transistor; the gate of the second transistor is connected to the first scanning signal terminal to receive For the first scanning signal, the first pole of the second transistor is connected to the data signal terminal to receive the data signal, and the second pole of the second transistor is connected to the control terminal of the driving circuit.
  • the storage circuit includes a storage capacitor, the first pole of the storage capacitor is connected to the control terminal of the driving circuit, and the second pole of the storage capacitor is connected to the The second end of the driving circuit is connected.
  • the N-type oxide thin film transistor included in the first reset circuit is a third transistor; the gate of the third transistor and the first reset control signal terminal connected to receive the first reset control signal, the first pole of the third transistor is connected to the first initialization voltage terminal to receive the first initialization voltage, the second pole of the seventh transistor is connected to the drive circuit control terminal connection.
  • the pixel circuit provided in some embodiments of the present disclosure further includes a second reset circuit, wherein the second reset circuit is configured to apply a second initialization voltage to the The second terminal of the drive circuit.
  • the second reset circuit includes a fourth transistor, the fourth transistor is an N-type thin film transistor, and the gate of the fourth transistor and the second reset control signal The terminal is connected to receive the second reset control signal, the first pole of the fourth transistor is connected to the second initialization voltage terminal to receive the second initialization voltage, the second pole of the fourth transistor is connected to the drive The second end of the circuit is connected.
  • the pixel circuit provided in some embodiments of the present disclosure further includes a first light emission control circuit, wherein the first light emission control circuit is configured to apply the first power supply voltage to The first end of the drive circuit.
  • the first light emission control circuit includes a fifth transistor, the fifth transistor is an N-type thin film transistor, the gate of the fifth transistor and the first light emission control circuit terminal to receive the first light-emitting control signal, the first pole of the fifth transistor is connected to the first power supply terminal to receive the first power supply voltage, the second pole of the fifth transistor is connected to the drive circuit The first end connection.
  • the pixel circuit provided in some embodiments of the present disclosure further includes a third reset circuit, wherein the third reset circuit is configured to apply a holding voltage to the first drive circuit under the control of a third reset control signal.
  • the third reset control signal and the first reset control signal are both ON signals for at least part of the time period.
  • the third reset circuit includes a sixth transistor, the sixth transistor is an N-type thin film transistor, and the gate of the sixth transistor and the third reset control signal The terminal is connected to receive the third reset control signal, the first pole of the sixth transistor is connected to the holding voltage terminal to receive the holding voltage, the second pole of the sixth transistor is connected to the first pole of the driving circuit end connection.
  • the third reset control signal and the first reset control signal are the same control signal.
  • the pixel circuit provided in some embodiments of the present disclosure further includes a second light emission control circuit, wherein the second light emission control circuit is configured to apply the driving current to the first pole of the light emitting element.
  • the second light emission control circuit includes a seventh transistor, the seventh transistor is an N-type thin film transistor, the gate of the seventh transistor and the second light emission control circuit terminal to receive the second light-emitting control signal, the first pole of the seventh transistor is connected to the second terminal of the driving circuit, the second pole of the seventh transistor is connected to the first pole of the light-emitting element connect.
  • the pixel circuit provided in some embodiments of the present disclosure further includes a voltage transmission circuit, wherein the voltage transmission circuit is configured to transfer the second power supply voltage to transmitting to the first terminal of the driving circuit, and transmitting a first power supply voltage different from the second power supply voltage to the first terminal of the driving circuit within a second time period.
  • the voltage transmission circuit includes an eighth transistor, the eighth transistor is an N-type thin film transistor, and the gate of the eighth transistor is connected to the voltage transmission control signal terminal
  • the first pole of the eighth transistor is connected to the first power supply terminal
  • the second pole of the eighth transistor is connected to the first terminal of the driving circuit
  • the first power supply The terminal is configured to provide the second power supply voltage during the first time period, and provide the first power supply voltage during the second time period.
  • At least some embodiments of the present disclosure provide a display panel, including a plurality of pixel units arranged in an array; wherein each of the pixel units includes the pixel circuit according to any one of the above.
  • At least some embodiments of the present disclosure provide a driving method for a pixel circuit, including an initialization phase, a threshold voltage compensation phase, a data writing and mobility compensation phase, and a light emitting phase, wherein, in the initialization phase, the first reset is input control signal and the second reset control signal, turn on the first reset circuit and the second reset circuit, and apply the first initialization voltage to the control terminal of the driving circuit through the first reset circuit to reset the control terminal of the driving circuit, apply the second initialization voltage to the second terminal of the driving circuit through the second reset circuit to reset the second terminal of the driving circuit;
  • the first reset control signal is input, the first reset circuit is turned on, and the first initialization voltage is applied to the control terminal of the drive circuit through the first reset circuit to turn on
  • the driving circuit stops inputting the second reset control signal, turns off the second reset circuit, and performs threshold compensation through the turned-on driving circuit and the storage circuit; the gate scan signal, turn on the data writing circuit, write the data signal into the control terminal of the driving circuit through the data
  • FIG. 1A is a schematic diagram of a 2T1C pixel circuit
  • FIG. 1B is a schematic diagram of another 2T1C pixel circuit
  • Fig. 2A is a schematic block diagram of a pixel circuit provided by at least some embodiments of the present disclosure
  • FIG. 2B is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 2A;
  • FIG. 2C is a signal timing diagram of the driving method of the pixel circuit shown in FIG. 2B;
  • Fig. 3A is a schematic block diagram of a pixel circuit provided by at least some embodiments of the present disclosure.
  • FIG. 3B is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 3A;
  • FIG. 3C is a signal timing diagram of the driving method of the pixel circuit shown in FIG. 3B;
  • Fig. 4A is a schematic block diagram of a pixel circuit provided by at least some embodiments of the present disclosure.
  • FIG. 4B is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 4A;
  • FIG. 4C is a signal timing diagram of the driving method of the pixel circuit shown in FIG. 4B;
  • Fig. 5A is a schematic block diagram of a pixel circuit provided by at least some embodiments of the present disclosure.
  • FIG. 5B is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 5A;
  • FIG. 5C is a signal timing diagram of the driving method of the pixel circuit shown in FIG. 5B;
  • FIG. 5D is a signal timing diagram of a pixel circuit driving method provided by at least some embodiments of the present disclosure.
  • Fig. 6A is a schematic block diagram of a pixel circuit provided by at least some embodiments of the present disclosure.
  • FIG. 6B is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 6A;
  • FIG. 6C is a signal timing diagram of the driving method of the pixel circuit shown in FIG. 6B;
  • Fig. 7A is a schematic block diagram of a pixel circuit provided by at least some embodiments of the present disclosure.
  • FIG. 7B is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 7A;
  • FIG. 7C is a signal timing diagram of the driving method of the pixel circuit shown in FIG. 7B;
  • Fig. 8A is a schematic block diagram of a pixel circuit provided by at least some embodiments of the present disclosure.
  • FIG. 8B is a schematic circuit structure diagram of a specific implementation example of the pixel circuit shown in FIG. 8A;
  • FIG. 8C is a signal timing diagram of the driving method of the pixel circuit shown in FIG. 8B.
  • FIGS. 9A to 9F are schematic diagrams of a display panel provided by an embodiment of the present disclosure.
  • the pixel circuit in the OLED display panel generally adopts a matrix driving method, which is divided into active matrix (Active Matrix, AM) driving and passive matrix (Passive Matrix, PM) driving according to whether switching components are introduced into each pixel unit.
  • the AMOLED display panel integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. Through the driving control of the thin film transistors and storage capacitors, the control of the driving current flowing through the OLED is realized, so that the OLED can be controlled according to the needs. glow. Therefore, the AMOLED display panel requires a small driving current, low power consumption, and a longer lifespan, which can meet the large-size display requirements of high resolution and multiple gray scales.
  • the AMOLED display panel has obvious advantages in terms of viewing angle, color reproduction, power consumption, and response time, and is suitable for display devices with high information content and high resolution.
  • the basic pixel circuit used in the AMOLED display panel can be a 2T1C pixel circuit, which uses two TFTs (Thin-film transistor, thin film transistor) and a storage capacitor Cs to realize the basic function of driving OLED to emit light.
  • FIG. 1A and FIG. 1B respectively show schematic diagrams of two kinds of 2T1C pixel circuits.
  • a 2T1C pixel circuit includes a switching transistor T0 , a driving transistor N0 and a storage capacitor Cs.
  • the gate of the switching transistor T0 is connected to the scan line to receive the scan signal Scan1, for example, the source is connected to the data signal line to receive the data signal Vdata, and the drain is connected to the gate of the driving transistor N0;
  • the source of the driving transistor N0 is connected to To the first voltage terminal to receive the first voltage VDD (high voltage), the drain is connected to the positive terminal of the OLED; one end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to The source of the driving transistor N0 and the first voltage terminal;
  • the negative terminal of the OLED is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the driving method of the 2T1C pixel circuit is to control the brightness (gray scale) of the pixel through two TFTs and the storage capacitor Cs.
  • the scan signal Scan1 is applied through the scan line to turn on the switch transistor T0
  • the data signal Vdata sent by the data drive circuit through the data signal line will charge the storage capacitor Cs through the switch transistor T0, thereby storing the data signal Vdata in the storage capacitor Cs
  • the stored data signal Vdata controls the conduction degree of the driving transistor N0, thereby controlling the magnitude of the current flowing through the driving transistor to drive the OLED to emit light, that is, the current determines the gray scale of the pixel emitting light.
  • the switching transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.
  • another 2T1C pixel circuit also includes a switching transistor T0 , a driving transistor N0 and a storage capacitor Cs, but the connection method is slightly changed, and the driving transistor N0 is an N-type transistor.
  • the changes of the pixel circuit in FIG. 1B relative to FIG. 1A include: the positive terminal of the OLED is connected to the first voltage terminal to receive the first voltage VDD (high voltage), and the negative terminal is connected to the drain of the driving transistor N0, and the driving transistor The source of N0 is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • One end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0 , and the other end is connected to the source of the driving transistor N0 and the second voltage terminal.
  • the working mode of the 2T1C pixel circuit is basically the same as that of the pixel circuit shown in FIG. 1A , and will not be repeated here.
  • the switch transistor T0 is not limited to an N-type transistor, and can also be a P-type transistor, so that the polarity of the scanning signal Scan1 that controls its turn-on or cut-off is changed accordingly, that is, Can.
  • the OLED display panel often flickers when switching between high and low frequencies. This kind of flicker affects high-quality picture quality, so it needs to be improved.
  • the driving transistor (DTFT) in the pixel circuit is made of low-temperature polysilicon semiconductor as the active layer, and the channel itself shows obvious hysteresis effect due to many defect states.
  • the hysteresis effect of a TFT device refers to an uncertainty in the electrical characteristics of a TFT device under a certain bias voltage, that is, the magnitude of the TFT device current is not only related to the current bias voltage, but also depends on the previous bias voltage. The state of the TFT device at the moment.
  • the hysteresis effect of TFT has already caused harm to the current flat panel display technology. For example, the image at the last moment is often retained in the image display at the next moment, resulting in display errors.
  • the hysteresis effect of TFT devices is related to gate dielectrics, semiconductor materials and interface state traps between them. These traps will trap and release charges, which will cause changes in the threshold voltage of TFT devices, and then under the same bias voltage, cause channel Changes in the carrier concentration, thereby changing the electrical characteristics of the TFT.
  • the active layer with weak hysteresis effect is used to prepare DTFT, and the DTFT is further reset in the reset or programming stage, so that the DTFT characteristics can be restored to the initial state as soon as possible, thereby reducing Afterimages and flickering at low frequencies are eliminated to improve image quality.
  • the pixel circuit includes a driving circuit, a data writing circuit, a storage circuit, and a first reset circuit; wherein, the driving circuit includes a control terminal, a first terminal, and a second terminal, and is configured to control the current flowing through the first terminal and the second terminal.
  • the driving current used to drive the light-emitting element to emit light is configured to write the data signal into the control terminal of the driving circuit under the control of the gate scanning signal; the storage circuit is configured to store the data signal; the first reset circuit is configured to It is configured to apply the first initialization voltage to the control terminal of the driving circuit under the control of the first reset control signal; wherein, the driving circuit and the data writing circuit include N-type thin film transistors.
  • the first reset circuit includes an N-type oxide thin film transistor.
  • Some embodiments of the present disclosure also provide a driving method and a display panel corresponding to the above-mentioned pixel circuit.
  • the driving circuit and the data writing circuit include N-type thin film transistors.
  • the first reset circuit includes an N-type oxide thin film transistor, which can reduce low-frequency leakage, maintain the voltage of the control terminal of the drive circuit so that the light does not flicker, improve the hysteresis of the TFT device, and reduce low-frequency afterimages.
  • FIG. 2A is a schematic block diagram of a pixel circuit provided by at least some embodiments of the present disclosure.
  • the pixel circuit 10 includes a driving circuit 100 , a data writing circuit 200 , a storage circuit 300 , a first reset circuit 410 and a light emitting element 700 .
  • the driving circuit 100 includes a first terminal 110 , a second terminal 120 and a control terminal 130 , and is configured to control a driving current flowing through the first terminal 110 and the second terminal 120 for driving the light emitting element 700 to emit light.
  • the driving circuit 100 includes an N-type thin film transistor, such as an N-type oxide thin film transistor.
  • the driving circuit 100 in the light-emitting phase, can provide a driving current to the light-emitting element 700 to drive the light-emitting element 700 to emit light, and can display gray scales according to needs (different gray scales correspond to different data signals) Provide corresponding driving current to emit light.
  • the light-emitting element 700 can use organic light-emitting diodes (OLEDs), mini light-emitting diodes (Mini LEDs), micro-light-emitting diodes (Micro LEDs), quantum dot light-emitting diodes (QLEDs), inorganic light-emitting diodes, etc.
  • OLEDs organic light-emitting diodes
  • Mini LEDs mini light-emitting diodes
  • Micro LEDs micro-light-emitting diodes
  • QLEDs quantum dot light-emitting diodes
  • inorganic light-emitting diodes etc.
  • the first reset circuit 410 is configured to apply the first initialization voltage Vinit1 to the control terminal 130 of the driving circuit 100 in response to the first reset control signal RST1.
  • the first reset circuit 410 may be an N-type oxide thin film transistor.
  • the first reset circuit 410 in the initialization phase, is turned on in response to the first reset control signal RST1, so that the first initialization voltage Vinit1 can be applied to the control terminal 130 of the driving circuit 100 to drive The circuit 100 performs an initialization operation.
  • N-type oxide thin film transistors can use IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide) as the active layer of thin film transistors, compared to the use of LTPS (Low Temperature Poly Silicon, low temperature polysilicon) or amorphous silicon (such as Crystalline silicon) as the active layer of the thin film transistor can effectively reduce the size of the transistor and reduce the leakage current, thereby making the pixel circuit suitable for low-frequency driving and increasing the resolution of the display panel.
  • IGZO Indium Gallium Zinc Oxide, indium gallium zinc oxide
  • LTPS Low Temperature Poly Silicon, low temperature polysilicon
  • amorphous silicon such as Crystalline silicon
  • the data writing circuit 200 is configured to write the data signal Vdata transmitted by the data line into the control terminal 130 of the driving circuit 100 in response to the gate scanning signal GN.
  • the data writing circuit 200 includes N-type thin film transistors, such as N-type oxide thin film transistors.
  • the data writing circuit 200 in the data writing phase, is turned on in response to the gate scanning signal GN, so that the data signal Vdata transmitted by the data line can be written into the control terminal 130 of the driving circuit 100 And stored in the storage circuit 300, so that the driving circuit 100 generates a driving current for driving the light emitting element 700 to emit light according to the data signal Vdata during the light emitting phase.
  • the storage circuit 300 is configured to store the written data signal Vdata, and electrically connects the control terminal 130 and the second terminal 120 of the driving circuit 100 .
  • the storage circuit 300 includes a storage capacitor. During the data writing and storage phase, the storage capacitor can receive and store the data signal Vdata written by the data writing circuit 200 .
  • the storage circuit 300 electrically connects the control terminal 130 of the driving circuit 100 to the second terminal 120 , so that the relevant information of the threshold voltage Vth of the driving circuit is correspondingly stored in the storage capacitor.
  • the pixel circuit 10 may further include a second reset circuit 420 configured as The second initialization voltage Vinit2 is applied to the second terminal 120 of the driving circuit 100 under the control of the second reset control signal RST2 .
  • the second reset circuit 420 may include an N-type thin film transistor, such as an N-type oxide thin film transistor.
  • the second reset circuit 420 in the initialization phase, is turned on in response to the second reset control signal RST2, so that the second initialization voltage Vinit2 can be applied to the second terminal 120 of the driving circuit 100, so that The potential of the second terminal 120 of the driving circuit 100 is initialized to the second initialization voltage Vinit2 according to the second initialization voltage Vinit2, so as to initialize the second terminal of the driving circuit 100 and eliminate the influence of the previous light-emitting phase.
  • the pixel circuit 10 may further include a first light emission control circuit 500 .
  • the first light emission control circuit 500 may be an N-type thin film transistor, such as an N-type oxide thin film transistor.
  • the first light emission control circuit 500 is configured to apply the first power supply voltage VDD to the first terminal 110 of the driving circuit 100 in response to the first light emission control signal EM1, so that the driving circuit 100 generates a driving current. .
  • the first light-emitting control circuit 500 is turned on in response to the first light-emitting control signal EM1, and applies the first power supply voltage VDD to the first terminal 110 of the driving circuit 100, so that the driving circuit 100 can and the voltage at the first terminal to generate a driving current; and in the non-light-emitting phase, the first light-emitting control circuit 500 is turned off in response to the first light-emitting control signal EM1, so that the driving circuit 100 does not generate a driving current, and the light-emitting element can be avoided. 700 emits light, so that the contrast of the corresponding display device can be improved.
  • the pixel circuit 10 may further include a third reset circuit 430 .
  • the third reset circuit 430 may be an N-type thin film transistor, such as an N-type oxide thin film transistor, which is configured to apply the holding voltage Vhold to the driving circuit under the control of the third reset control signal RST3
  • the first end 110 of the drive circuit 100 is used to weaken the characteristic drift of the drive circuit 100 .
  • the third reset control signal RST3 and the first reset control signal RST1 are both on signals for at least part of the time period.
  • the third reset control signal RST3 and the first reset control signal RST1 can be the same control signal, that is, the same timing can be used, so as to realize the weakened driving circuit 100 The effect of hysteresis.
  • the first reset control signal RST1, the second reset control signal RST2 and the third reset control signal RST3 are used to distinguish three control signals with different timings (for example, reset control signals) .
  • the second reset control signal RST2 and the third reset control signal RST3 may be in a subordinate relationship with each other.
  • the second reset control signal RST2 used to control the second reset circuit 420 in the pixel circuit 10 of the current row of pixel units can also be used to control the second reset circuit 420 in the pixel circuit 10 of the previous row of pixel units.
  • Three reset circuits 430 that is, as the third reset control signal RST3 in the pixel circuit 10 of the pixel unit in the previous row; similarly, it is used to control the third reset control signal RST3 of the third reset circuit 430 in the pixel circuit 10 of the pixel unit in the current row
  • the signal RST3 can also be used to control the second reset circuit 420 in the pixel circuit 10 of the next row of pixel units, that is, the second reset control signal RST2 in the pixel circuit 10 of the next row of pixel units.
  • the second reset control signal RST2 and the third reset control signal RST3 can be provided by the same GOA (Gate driver On Array), which is beneficial to simplify the wiring of the display screen, improve the resolution, and realize narrow borders.
  • GOA Gate driver On Array
  • the pixel circuit 10 may further include a second light emission control circuit 600 .
  • the second light emission control circuit 600 may be an N-type thin film transistor, such as an N-type oxide thin film transistor.
  • the second light emission control circuit 600 is configured to apply a driving current to the first pole of the light emitting element 700 under the control of the second light emission control signal EM2 to make the light element 700 emit light.
  • the second light-emitting control circuit 600 is turned on in response to the second light-emitting control signal EM2, so that the driving circuit 100 can apply a driving current to the light-emitting element 700 through the second light-emitting control circuit 600 to make it emit light; and
  • the second light-emitting control circuit 600 is turned off in response to the second light-emitting control signal EM2 to prevent the light-emitting element 700 from emitting light, thereby improving the contrast of the corresponding display device.
  • the pixel circuit 10 may further include a voltage transmission circuit 800 .
  • the voltage transmission circuit 800 may be an N-type thin film transistor, such as an N-type oxide thin film transistor, which is configured to, under the control of the voltage transmission control signal Vtc, transfer the second
  • the second power supply voltage can be, for example, VSS transmitted to the first terminal 110 of the driving circuit 100, and within a second period of time, such as after t2, a first power supply voltage different from the second power supply voltage, such as VDD, is transmitted to the driving circuit 100.
  • first end 110 a first power supply voltage different from the second power supply voltage, such as VDD
  • the pixel circuit 10 may also include a second reset circuit 420.
  • the data signal terminal transmits the reference voltage Vref, such as the first initialization voltage Vinit1, to the first terminal of the data writing circuit 200 within the first time period, such as t1, t2 and t3.
  • the data signal terminal transmits the data signal Vdata to the first terminal of the data writing circuit 200 within the second time period, such as t3, t4 and t5, to write
  • the data signal Vdata is written and stored in the storage circuit 300 , so that the driving circuit 100 can generate a driving current for driving the light emitting element 700 to emit light according to the data signal Vdata during the light emitting stage.
  • FIG. 2B is a schematic circuit structure diagram of a specific example of the pixel circuit shown in FIG. 2A .
  • the pixel circuit 10 includes: first to third transistors T1 , T2 , T3 , a storage capacitor C1 and a light emitting element LE.
  • the first transistor T1 is used as a driving transistor
  • the other second transistor T2 and third transistor T3 are used as switching transistors.
  • the light-emitting element LE may be an OLED, and the embodiments of the present disclosure include but are not limited thereto. The following embodiments are all described using OLED as an example, and details are not repeated here.
  • the OLED can be of various types, such as top emission, bottom emission, etc., and can emit red light, green light, blue light, or white light, etc., which are not limited by embodiments of the present disclosure.
  • each transistor is an N-type transistor as an example for description, but this does not constitute a limitation to the embodiments of the present disclosure.
  • the above-mentioned first to third transistors T1 , T2 , T3 may all be N-type thin film transistors, wherein the first to third transistors T1 , T2 , T3 may all be N-type oxide thin film transistors.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly Silicon
  • amorphous silicon For example, hydrogenated amorphous silicon is used as the active layer of the thin film transistor, which can effectively reduce the size of the transistor and prevent leakage current.
  • the driving circuit 100 can be implemented as a first transistor T1 , where the first transistor T1 can be an N-type thin film transistor, such as an N-type oxide thin film transistor.
  • the gate of the first transistor T1 is connected to the first node N1 as the control terminal 130 of the driving circuit 100, and the first pole of the first transistor T1 is used as the first terminal 110 of the driving circuit 100 through the third node N3 and the first power supply terminal VDD Connected to receive the first power supply voltage VDD, the second pole of the first transistor T1 is connected to the second node N2 as the second terminal 120 of the driving circuit 100 .
  • the first power supply voltage VDD may be a driving voltage, such as a high voltage (relative to the second power supply voltage VSS connected to the light emitting element, which will be described in detail below).
  • the data writing circuit 200 may be realized as a second transistor T2, wherein the second transistor T2 may be an N-type thin film transistor, such as an N-type oxide thin film transistor.
  • the gate of the second transistor T2 is connected to the gate scan signal terminal to receive the gate scan signal GN.
  • the first pole of the second transistor T2 is connected to the data signal terminal to receive the data signal Vdata, and the second pole of the second transistor T2 is connected to the first node N1 (the control terminal 130 of the driving circuit 100 ).
  • the storage circuit 300 can be implemented as a storage capacitor C1, the first end of the storage capacitor C1 is connected to the first node N1 (the control end 130 of the drive circuit 100), and the second end of the storage capacitor C1 is connected to the first node N1.
  • the two nodes N2 (the second terminal 120 of the driving circuit 100 ) are connected.
  • the first reset circuit 410 may be implemented as a third transistor T3, wherein the third transistor T3 is an N-type oxide thin film transistor.
  • the gate of the third transistor T3 is connected to the first reset control signal terminal to receive the first reset control signal RST1
  • the first electrode of the third transistor T3 is connected to the first initialization voltage terminal to receive the first initialization voltage Vinit1
  • the third transistor T3 The second pole of T3 is connected to the first node N1 (the control terminal 130 of the driving circuit 100 ).
  • FIG. 3B is a schematic circuit structure diagram of a specific example of the pixel circuit shown in FIG. 3A .
  • the pixel circuit 10 includes: first to fourth transistors T1 , T2 , T3 , T4 , a storage capacitor C1 and a light emitting element LE.
  • the difference between the pixel circuit 10 shown in FIG. 3B and the pixel circuit 10 shown in FIG. 2B is that the pixel circuit 10 shown in FIG. 3B further includes a fourth transistor T4 for realizing the second reset circuit 420 .
  • the rest of the pixel circuit 10 shown in FIG. 3B is the same as the pixel circuit 10 shown in FIG. 2B , and will not be repeated here.
  • the above-mentioned first to fourth transistors T1 , T2 , T3 , T4 may all be N-type thin film transistors, wherein the first to fourth transistors T1 , T2 , T3 , T4 may all be N-type oxide thin film transistors.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly Silicon
  • amorphous silicon For example, hydrogenated amorphous silicon is used as the active layer of the thin film transistor, which can effectively reduce the size of the transistor and prevent leakage current.
  • the second reset circuit 420 may be realized as a fourth transistor T4, wherein the fourth transistor T4 may be an N-type thin film transistor, such as an N-type oxide thin film transistor.
  • the gate of the fourth transistor T4 is connected to the second reset control signal terminal to receive the second reset control signal RST2, the first electrode of the fourth transistor T4 is connected to the second initialization voltage terminal to receive the second initialization voltage Vinit2, and the fourth transistor T4
  • the second pole of T4 is connected to the second node N2 (the second terminal 120 of the driving circuit 100 ).
  • FIG. 4B is a schematic circuit structure diagram of a specific example of the pixel circuit shown in FIG. 4A .
  • the pixel circuit 10 includes: first to fifth transistors T1 , T2 , T3 , T4 , T5 , a storage capacitor C1 and a light emitting element LE.
  • the difference between the pixel circuit 10 shown in FIG. 4B and the pixel circuit 10 shown in FIG. 3B is that the pixel circuit 10 shown in FIG. 4B further includes a fifth transistor T5 for implementing the first light emission control circuit 500 .
  • the rest of the pixel circuit 10 shown in FIG. 4B is the same as the pixel circuit 10 shown in FIG. 3B , and will not be repeated here.
  • the above-mentioned first to fifth transistors T1, T2, T3, T4, and T5 may all use N-type thin film transistors, wherein the first to fifth transistors T1, T2, T3, T4, and T5 may all be N-type oxide thin films transistor.
  • N-type oxide thin film transistor Indium Gallium Zinc Oxide (IGZO) can be used as the active layer of the thin film transistor, compared to the use of low temperature polysilicon (Low Temperature Poly Silicon, LTPS) or amorphous silicon ( For example, hydrogenated amorphous silicon) is used as the active layer of the thin film transistor, which can effectively reduce the size of the transistor and prevent leakage current.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly Silicon
  • amorphous silicon for example, hydrogenated amorphous silicon
  • the first light emission control circuit 500 can be implemented as a fifth transistor T5, wherein the fifth transistor T5 can be an N-type thin film transistor, such as an N-type oxide thin film transistor, and the gate of the fifth transistor T5 It is connected to the first light emission control terminal to receive the first light emission control signal EM1, the first pole of the fifth transistor T5 is connected to the first power supply terminal to receive the first power supply voltage VDD, the second pole of the fifth transistor is connected to the third node N3 (the first terminal 110 of the drive circuit 100) is connected.
  • the fifth transistor T5 can be an N-type thin film transistor, such as an N-type oxide thin film transistor, and the gate of the fifth transistor T5 It is connected to the first light emission control terminal to receive the first light emission control signal EM1, the first pole of the fifth transistor T5 is connected to the first power supply terminal to receive the first power supply voltage VDD, the second pole of the fifth transistor is connected to the third node N3 (the first terminal 110 of the drive circuit 100) is connected.
  • FIG. 5B is a schematic circuit structure diagram of a specific example of the pixel circuit shown in FIG. 5A .
  • the pixel circuit 10 includes: first to sixth transistors T1 , T2 , T3 , T4 , T5 , T6 , a storage capacitor C1 and a light emitting element LE.
  • the difference between the pixel circuit 10 shown in FIG. 5B and the pixel circuit 10 shown in FIG. 4B is that the pixel circuit 10 shown in FIG. 5B further includes a sixth transistor T6 for realizing the third reset circuit 430 .
  • the rest of the pixel circuit 10 shown in FIG. 5B is the same as the pixel circuit 10 shown in FIG. 4B , and will not be repeated here.
  • the above-mentioned first to sixth transistors T1, T2, T3, T4, T5, and T6 can all be N-type thin film transistors, and the first to sixth transistors T1, T2, T3, T4, T5, and T6 can all be N-type oxide thin film transistor.
  • Indium Gallium Zinc Oxide (IGZO) can be used as the active layer of the thin film transistor, compared to the use of low temperature polysilicon (Low Temperature Poly Silicon, LTPS) or amorphous silicon ( For example, hydrogenated amorphous silicon) is used as the active layer of the thin film transistor, which can effectively reduce the size of the transistor and prevent leakage current.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly Silicon
  • amorphous silicon for example, hydrogenated amorphous silicon
  • the third reset circuit 430 may be implemented as a sixth transistor T6, wherein the sixth transistor T6 may be an N-type thin film transistor, such as an N-type oxide thin film transistor.
  • the gate of the sixth transistor T6 is connected to the third reset control signal end to receive the third reset control signal RST3, the first pole of the sixth transistor T6 is connected to the hold voltage end to receive the hold voltage Vhold, and the second electrode of the sixth transistor T6 The pole is connected to the third node N3 (the first terminal 110 of the driving circuit 100).
  • FIG. 6B is a schematic circuit structure diagram of a specific example of the pixel circuit shown in FIG. 6A .
  • the pixel circuit 10 includes: transistors T1 , T2 , T3 , T4 , T7 , a storage capacitor C1 and a light emitting element LE.
  • the difference between the pixel circuit 10 shown in FIG. 6B and the pixel circuit 10 shown in FIG. 3B is that the pixel circuit 10 shown in FIG. 6B further includes a seventh transistor T7 for realizing the second light emission control circuit 600 .
  • the rest of the pixel circuit 10 shown in FIG. 6B is the same as the pixel circuit 10 shown in FIG. 3B , and will not be repeated here.
  • the aforementioned transistors T1 , T2 , T3 , T4 , and T7 may all be N-type thin film transistors, and the transistors T1 , T2 , T3 , T4 , and T7 may all be N-type oxide thin film transistors.
  • Indium Gallium Zinc Oxide (IGZO) can be used as the active layer of the thin film transistor, compared to the use of low temperature polysilicon (Low Temperature Poly Silicon, LTPS) or amorphous silicon ( For example, hydrogenated amorphous silicon) is used as the active layer of the thin film transistor, which can effectively reduce the size of the transistor and prevent leakage current.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly Silicon
  • amorphous silicon for example, hydrogenated amorphous silicon
  • the second light emission control circuit 600 can be realized as a seventh transistor T7, wherein the seventh transistor T7 is an N-type thin film transistor, such as an N-type oxide thin film transistor.
  • the gate of the seventh transistor T7 is connected to the second light emission control terminal to receive the second light emission control signal EM2, the first pole of the seventh transistor T7 is connected to the second node N2 (the second end 120 of the driving circuit 100), and the seventh transistor T7
  • the second electrode of the transistor T7 is connected to the first electrode of the light emitting element EL.
  • FIG. 7B is a schematic circuit structure diagram of a specific example of the pixel circuit shown in FIG. 7A .
  • the pixel circuit 10 includes: transistors T1 , T2 , T3 , T8 , a storage capacitor C1 and a light emitting element LE.
  • the difference between the pixel circuit 10 shown in FIG. 7B and the pixel circuit 10 shown in FIG. 2B is that the pixel circuit 10 shown in FIG. 7B further includes an eighth transistor T8 for implementing the voltage transmission circuit 800 .
  • the rest of the pixel circuit 10 shown in FIG. 7B is the same as the pixel circuit 10 shown in FIG. 2B , and will not be repeated here.
  • the aforementioned transistors T1 , T2 , T3 , T4 , and T7 may all be N-type thin film transistors, and the transistors T1 , T2 , T3 , T4 , and T7 may all be N-type oxide thin film transistors.
  • Indium Gallium Zinc Oxide (IGZO) can be used as the active layer of the thin film transistor, compared to the use of low temperature polysilicon (Low Temperature Poly Silicon, LTPS) or amorphous silicon ( For example, hydrogenated amorphous silicon) is used as the active layer of the thin film transistor, which can effectively reduce the size of the transistor and prevent leakage current.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly Silicon
  • amorphous silicon for example, hydrogenated amorphous silicon
  • the second light emission control circuit 600 can be implemented as an eighth transistor T8, wherein the eighth transistor T8 is an N-type thin film transistor, such as an N-type oxide thin film transistor.
  • the gate of the eighth transistor T8 is connected to the voltage transmission control signal terminal to receive the voltage transmission control signal Vtc, the first pole of the eighth transistor T8 is connected to the first power supply terminal, and the second pole of the eighth transistor T8 is connected to the third node N3 (the first terminal 110 of the drive circuit 100) is connected.
  • the first power supply terminal is configured to transmit the second power supply voltage, for example, VSS, to the first terminal 110 of the drive circuit 100 during the first time period, and to transmit a voltage different from the second power supply voltage during the second time period.
  • the first power supply voltage such as VDD is transmitted to the first terminal 110 of the driving circuit 100 .
  • FIG. 8B is a schematic circuit structure diagram of a specific example of the pixel circuit shown in FIG. 8A .
  • the pixel circuit 10 includes: transistors T1 , T2 , T4 , T5 , a storage capacitor C1 and a light emitting element LE.
  • the difference between the pixel circuit 10 shown in FIG. 8B and the pixel circuit 10 shown in FIG. 3B is that the pixel circuit 10 shown in FIG. 8B does not include the third transistor T3 for implementing the first reset circuit 410 .
  • the rest of the pixel circuit 10 shown in FIG. 8B is the same as the pixel circuit 10 shown in FIG. 3B , and will not be repeated here.
  • the above-mentioned transistors T1, T2, T4, and T5 may all be N-type thin film transistors, such as N-type oxide thin film transistors.
  • the data signal terminal transmits the reference voltage Vref, for example, the first initialization voltage Vinit1, to the first terminal of the second transistor T2 within the first period of time. And after the second transistor T2 is turned on in response to the gate scanning signal GN, the first initialization voltage Vinit1 is transmitted to the control terminal 130 of the driving circuit 100 to complete the initialization operation of the control terminal 130 of the driving circuit 100, and the data signal During the second time period, the data signal Vdata is transmitted to the first terminal of the data writing circuit 200, and the data signal Vdata is written into the first terminal of the driving circuit 100 after the second transistor T2 is turned on in response to the gate scanning signal GN.
  • the control terminal 130 is also stored in the storage circuit 300 , so that the driving circuit 100 generates a corresponding driving current according to the intensity of the data signal Vdata during the light-emitting stage, so as to drive the light-emitting element 700 to emit light.
  • the storage capacitor C1 may at least partially be a capacitive device manufactured through a process, for example, by making a special capacitive electrode to realize the capacitive device, and each electrode of the capacitor may be made through a metal layer, a semiconductor layer (such as doped polysilicon), etc., and the capacitance can also be at least partially the parasitic capacitance between various devices, which can be realized by the transistor itself and other devices and lines.
  • the connection method of the capacitor is not limited to the method described above, and other suitable connection methods can also be used, as long as the voltage of the corresponding node can be stored.
  • the first node N1 , the second node N2 and the third node N3 do not represent components that must actually exist, but instead represent converging points of related electrical connections in the circuit diagram.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as examples.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • the embodiments of the present disclosure in order to distinguish the two poles of the transistor except the gate, it is directly described that one pole is the first pole and the other pole is the second pole.
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first pole of the transistor is a drain, and the second pole is a source.
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly Silicon
  • amorphous silicon For example, hydrogenated amorphous silicon is used as the active layer of the thin film transistor, which can effectively reduce the size of the transistor and prevent leakage current.
  • the cathode of the light-emitting element LE (for example, the common cathode of multiple light-emitting elements) is connected to the second power supply voltage VSS (low voltage) as an example for illustration.
  • VSS low voltage
  • examples include but are not limited to.
  • the anode of the light emitting element LE can also be connected to the first power supply voltage VDD (high voltage), and the cathode thereof can be directly or indirectly connected to the driving circuit, for example, refer to the 2T1C pixel circuit shown in FIG. 1B .
  • the effective voltage refers to the voltage that can make the operated transistor included in it be turned on
  • invalid voltage refers to the voltage that cannot make it Included is the voltage at which the operated transistor is turned on (ie, the transistor is turned off).
  • the effective voltage can be higher or lower than the inactive voltage.
  • the effective voltage when each transistor is an N-type transistor, the effective voltage is a high voltage, and the invalid voltage is a low voltage.
  • FIG. 2C is a signal timing diagram of a pixel circuit driving method provided by at least some embodiments of the present disclosure.
  • the working principle of the pixel circuit shown in FIG. 2A will be described by taking the pixel circuit shown in FIG. 2A as an example in which the pixel circuit structure shown in FIG. 2B is implemented in conjunction with the signal timing diagram shown in FIG. 2C .
  • the voltage level of the signal timing diagram shown in FIG. 2C is only schematic, and does not represent the real voltage value or relative ratio.
  • the high voltage signal corresponds to the voltage of the N-type transistor.
  • the on signal, and the low voltage signal corresponds to the off signal of the N-type transistor.
  • the driving method provided by this embodiment may include three phases, which are initialization phase p1, data writing phase p2, and light emitting phase p3, and FIG. 2C shows each signal in each phase. timing waveform.
  • the first reset control signal RST1 is input, the first reset circuit 410 is turned on (ie, turned on), and the control terminal 130 of the driving circuit 100 is reset through the first reset circuit 410 .
  • the third transistor T3 is turned on by the high voltage of the first reset control signal RST1, so that the first node N1 is initialized, and the initialization voltage is Vinit1.
  • Vinit1 is a low voltage (for example, it can be grounded or other low voltages)
  • the voltage of the gate of the first transistor T1 (that is, the first node N1) becomes Vinit1
  • the first transistor T1 is in a cut-off state, so that the light is emitted
  • the device EL is in a non-luminous state.
  • the third transistor T3 can use an oxide thin film transistor to reduce low-frequency leakage, so that the first node N1 maintains a low voltage, so that the first transistor T1 is in an off state for a long time, and then the light-emitting device EL Staying in the non-luminous state for a long time eliminates flickering.
  • the second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data signal Vdata.
  • the gate scanning signal GN is input, the data writing circuit 200 is turned on, the data signal Vdata is written into the control terminal 130 of the driving circuit 100 through the data writing circuit 200, and the written data is stored in the storage circuit 300.
  • Data signal Vdata For example, in the data writing phase, the first reset control signal RST1 becomes a low voltage, so that the third transistor T3 is turned off, and the gate scanning signal GN becomes a high voltage to turn on the second transistor T2.
  • the first The voltage of the node N1 changes from the first initialization voltage Vinit1 to a higher voltage, namely the data voltage Vdata (the voltage of the data signal Vdata), so that the first transistor T1 is turned on.
  • the storage capacitor C1 can store the data voltage Vdata, thereby completing data writing.
  • the input of the gate scan signal GN is stopped, the data writing circuit 200 is turned off, and the driving circuit 100 generates a driving current under the control of the data signal Vdata stored in the storage circuit 300 to make the light-emitting element 700 emit light.
  • the first reset control signal RST1 becomes a low voltage, so that the third transistor T3 is turned off, and at the same time, the second transistor T2 is turned off by the low voltage of the gate scanning signal GN, preventing the input of the data voltage Vdata .
  • the first transistor T1 is kept in the conduction state under the control of the data signal Vdata stored in the storage capacitor C1
  • the voltage of the second node N2 rises beyond the turn-on voltage of the light emitting device EL, and the light emitting device EL starts to emit light, because it is constant Therefore, the voltage of the second node N2 will reach the turn-on voltage of the light-emitting device.
  • the voltage of the first node N1 also follows the second The voltage of the node N2 rises to a stable state, even if the voltages of the two nodes N1 and N2 change, the voltage difference between the two nodes N1 and N2, that is, the voltage difference Vgs between the gate of the first transistor T1 and its source, can remain unchanged, so the luminous current I is constant as described by the following formula:
  • I is the light emitting current
  • k is a constant coefficient
  • ⁇ is the mobility of the first transistor T1
  • Vdata is the data signal voltage
  • ⁇ V is the gradually increasing value of the voltage of the second node N2.
  • FIG. 3C is a signal timing diagram of a pixel circuit driving method provided by at least some embodiments of the present disclosure.
  • the working principle of the pixel circuit shown in FIG. 3A will be described by taking the pixel circuit shown in FIG. 3A as an example in which the pixel circuit structure shown in FIG. 3B is implemented in conjunction with the signal timing diagram shown in FIG. 3C .
  • the driving method provided by this embodiment may include four stages, which are initialization stage t11, threshold voltage compensation stage t22, data writing and mobility compensation stage t33, and light emission stage t44.
  • initialization stage t11 threshold voltage compensation stage t22
  • data writing and mobility compensation stage t33 data writing and mobility compensation stage t33
  • light emission stage t44 light emission stage t44.
  • FIG. 3C The timing waveforms of the individual signals in each stage are shown.
  • the first reset control signal RST1 and the second reset control signal RST2 are input, the first reset circuit 410 and the second reset circuit 420 are turned on (that is, turned on), and the drive circuit 100 is controlled by the first reset circuit 410
  • the terminal 130 is reset, and the second terminal 120 of the driving circuit 100 is reset through the second reset circuit 420 .
  • the third transistor T3 is turned on by the high voltage of the first reset control signal RST1, so that the first node N1 is initialized, and the initialization voltage is Vinit1.
  • Vinit1 is at a high voltage (for example, the first power supply voltage, such as VDD or other high voltage)
  • the voltage of the gate of the first transistor T1 (that is, the first node N1 ) becomes Vinit1.
  • the fourth transistor T4 is turned on by the high voltage of the second reset control signal RST2, so that the second node N2 is initialized, and the initialization voltage is Vinit2.
  • Vinit2 can be a low voltage (for example, it can be grounded or be other low voltage), for example, the voltage of Vinit2 can be less than the second power supply voltage (for example VSS), so that the voltage difference Vgs between the gate of the first transistor T1 and its source Large enough (for example, greater than 7V), so that the hysteresis state can be quickly eliminated.
  • VSS the second power supply voltage
  • Vinit2 may be at a low voltage
  • the second node N2 connected to the second pole of the fourth transistor T4 is also at a low voltage after the fourth transistor T4 is turned on, so that the light emitting device EL is in a non-luminous state.
  • the third transistor T3 can use an oxide thin film transistor to reduce low-frequency leakage, so that the first node N1 maintains a low voltage, so that the first transistor T1 is in an off state for a long time, and the light-emitting device EL is in a non-light-emitting state for a long time. Eliminated flickering.
  • the second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data signal Vdata.
  • the first reset control signal RST1 is input, the first reset circuit 410 is turned on, and the first initialization voltage Vinit1 is applied to the control terminal 130 of the driving circuit 100 through the first reset circuit 410 to turn on the driving circuit 100 ;
  • stop inputting the second reset control signal, and turn off the second reset circuit 420 thus, threshold compensation can be performed through the turned-on drive circuit 100 and storage circuit 300 .
  • the first reset control signal RST1 can maintain a high voltage, so that the third transistor T3 remains turned on; the second reset control signal RST2 can be a low voltage, so that the fourth transistor T4 is turned off.
  • the second transistor T2 is continuously turned off by the low voltage of the gate scan signal GN, thereby continuously preventing the input of the data signal Vdata.
  • the voltage of the first node N1 ie, the first initialization voltage Vinit1
  • the first transistor T1 is turned on.
  • the voltage VDD of the third node N3 is a high voltage
  • the voltage of the second node N2 gradually rises from the initial VSS until the voltage difference Vgs between the gate of the first transistor T1 and its source (for example, the second pole) equal to its own threshold voltage Vth
  • the voltage V N2 of the second node N2 is the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1
  • the threshold voltage Vth of the first transistor T1 is written into across the storage capacitor C1, thus completing the threshold voltage compensation, as described by the following formula:
  • V N2 Vinit1-Vth
  • V N2 is the voltage of the second node N2
  • Vinit1 is the voltage of the second node N2
  • V N2 is the first initialization voltage
  • Vth is the threshold voltage of the first transistor T1 .
  • the gate scanning signal GN is input, the data writing circuit 200 is turned on, and the data signal Vdata is written into the control terminal 130 of the driving circuit 100 through the data writing circuit 200, and passed through the storage circuit 300
  • the written data signal Vdata is stored.
  • the first reset control signal RST1 becomes a low voltage, thereby turning off the third transistor T3;
  • the second reset control signal RST2 may be a low voltage, thereby causing the fourth transistor T4 to be turned off, and the gate scan signal GN becomes a high voltage
  • the second transistor T2 is turned on.
  • the voltage of the first node N1 changes from the first initialization voltage Vinit1 to the data voltage Vdata (the voltage of the data signal Vdata), so that the first transistor T1 is turned on.
  • the storage capacitor C1 can store the data voltage Vdata, thereby completing data writing. Since the light-emitting device EL connected to the second node N2 can be regarded as a capacitor, and its capacitance value is much larger than that of the first capacitor C1, the voltage at the second node N2 is almost unchanged, and remains the first capacitor in the previous stage t22. The difference between the initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1.
  • V N2 Vinit1-Vth+ ⁇ V
  • V N2 is the voltage of the second node N2
  • Vinit1 is the voltage of the second node N2
  • V N2 is the first initialization voltage
  • Vth is the threshold voltage of the first transistor T1
  • ⁇ V is the gradual increase of the voltage of the second node N2 value.
  • the voltage of the first node N1 is still the data voltage Vdata due to the conduction of the second transistor T2. Because the driving current of the first transistor T1 is described by the following formula:
  • Ids is the driving current of the first transistor T1
  • k is a constant coefficient
  • ⁇ is the mobility of the first transistor T1
  • Vgs is the voltage difference between the gate of the first transistor T1 and its source
  • Vth is the voltage difference of the first transistor T1 threshold voltage.
  • the first transistor T1 The voltage difference Vgs between the gate of a transistor T1 and its source is smaller, so (Vgs-Vth) 2 is smaller, and because the mobility ⁇ of the first transistor T1 is larger, the drive current Ids of the first transistor T1 is corrected .
  • the driving currents of driving transistors with different mobilities have little difference under the same data voltage Vdata.
  • the input of the gate scanning signal GN is stopped, the data writing circuit 200 is turned off, and the driving circuit 100 generates a driving current under the control of the data signal Vdata stored in the storage circuit 300 to make the light emitting element 700 emit light.
  • the first reset control signal RST1 becomes low voltage, thereby turning off the third transistor T3; the second reset control signal RST2 may be low voltage, thereby turning off the fourth transistor T4.
  • the second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data voltage Vdata.
  • the voltage of the second node N2 rises beyond the turn-on voltage of the light emitting device EL, and the light emitting device EL starts to emit light. Because it is driven by a constant current, the voltage of the second node N2 will finally reach the turn-on voltage of the light emitting device, and at the same time Since the first node N1 and the second node N2 are connected through the first capacitor C1, the voltage of the first node N1 also follows the voltage of the second node N2 to rise to a stable state, even if the voltages of the two nodes N1 and N2 change, N1 The voltage difference between the two nodes of 1 and N2, that is, the voltage difference Vgs between the gate of the first transistor T1 and its source can remain unchanged, so the luminous current I is constant, as described in the following formula:
  • the pixel circuit has the technical effects of threshold voltage compensation, mobility ⁇ compensation and voltage drop (IR Drop) compensation.
  • the second reset control signal RST2 and the gate scan signal GN may share a set of GOA circuits, so as to simplify the wiring of the display screen, improve the resolution, and realize narrow borders.
  • FIG. 6C is a signal timing diagram of a pixel circuit driving method provided by at least some embodiments of the present disclosure.
  • the driving method of the pixel circuit disclosed in FIG. 6C is almost the same as the driving method of the pixel circuit disclosed in FIG. 3C described above.
  • the working principle of the pixel circuit shown in FIG. 6A will be described by taking the pixel circuit shown in FIG. 6A as an example in which the pixel circuit structure shown in FIG. 6B is implemented in conjunction with the signal timing diagram shown in FIG. 6C .
  • the driving method provided by this embodiment may include four stages, which are initialization stage t11, threshold voltage compensation stage t22, data writing and mobility compensation stage t33, and light emission stage t44.
  • initialization stage t11 threshold voltage compensation stage t22
  • data writing and mobility compensation stage t33 data writing and mobility compensation stage t33
  • light emission stage t44 light emission stage t44.
  • FIG. 6C The timing waveforms of the individual signals in each stage are shown.
  • the pixel circuit 10 shown in FIG. 6B corresponding to the signal timing diagram of the pixel circuit driving method shown in FIG. 6C is compared to the signal timing diagram corresponding to the pixel circuit driving method shown in FIG. 3C shown in FIG. 3B.
  • the pixel circuit 10 shown in FIG. 6B differs in that the pixel circuit 10 shown in FIG. 6B adds a seventh transistor T7 for implementing the second light emission control circuit 600 .
  • the light emitting device EL is connected to the second node N2 through the seventh transistor T7, so that the drain (for example, the first electrode) of the first transistor T1 is always at the first power supply voltage, for example, VDD.
  • the first transistor T1 is only in two states, the off state and the saturation state, which is conducive to stabilizing the first transistor T1. A characteristic of transistor T1.
  • the voltage of the second initialization voltage Vinit2 can be lower than the second power supply voltage (such as VSS), so that the voltage difference Vgs between the gate and the source of the first transistor T1 is sufficiently large (such as greater than 7V), so that the hysteresis can be quickly eliminated. state, but the light emitting device EL is in an inverted state because the voltage of the second node N2 is the second initialization voltage Vinit2.
  • the reverse voltage is large enough, the light-emitting device EL has a reverse drive current, which is unfavorable to the light-emitting device EL for a long time. Therefore, the existence of the seventh transistor T7 avoids the generation of reverse drive current, and can also make the second initialization voltage Vinit2 Low enough (for example, lower than the second supply voltage) so that the hysteresis is eliminated as soon as possible.
  • the difference between the driving method provided by this embodiment and the driving method shown in FIG. 3C is that the second light emission control signal EM2 is at a low voltage, and the seventh transistor T7 is turned off.
  • the difference between the driving method provided by this embodiment and the driving method shown in FIG. 3C is that the second light emission control signal EM2 is low voltage, and the seventh transistor T7 is turned off.
  • the difference between the driving method provided by this embodiment and the driving method shown in FIG. 3C is that the second light emission control signal EM2 is a high voltage, and the seventh Transistor T7 is turned on.
  • the difference between the driving method provided by this embodiment and the driving method shown in FIG. 3C is that the second light-emitting control signal EM2 is at a high voltage, and the seventh transistor T7 is turned on.
  • the second reset control signal RST2 and the gate scanning signal GN can share a set of GOA circuits
  • the second reset control signal RST2 and the second light emission control signal EM2 can also share a set of GOA circuits, for example , an inverter can be added for generating a pair of the second reset control signal RST2 and the second light emission control signal EM2 . Therefore, the pixel circuit shown in FIG. 6B corresponding to the timing diagram shown in FIG. 6C only needs two sets of GOA circuits to work, so as to simplify wiring of the display screen, improve resolution, and realize narrow borders.
  • FIG. 4C is a signal timing diagram of a pixel circuit driving method provided by at least some embodiments of the present disclosure.
  • the working principle of the pixel circuit shown in FIG. 4A will be described by taking the pixel circuit shown in FIG. 4A as an example in which the pixel circuit structure shown in FIG. 4B is implemented in conjunction with the signal timing diagram shown in FIG. 4C .
  • the driving method provided by this embodiment may include five stages, which are initialization stage t1, threshold voltage compensation stage t2, data writing stage t3, mobility compensation stage t4, and light emitting stage t5.
  • the timing waveforms of the individual signals in each phase are shown in 4C.
  • the first reset control signal RST1 and the second reset control signal RST2 are input, the first reset circuit 410 and the second reset circuit 420 are turned on (that is, turned on), and the first reset circuit 420 of the driving circuit 100 is controlled by the second reset circuit 420.
  • the two terminals 120 are reset.
  • the third transistor T3 is turned on by the high voltage of the first reset control signal RST1 , so that the first node N1 (the control terminal 130 of the driving circuit 100 ) is initialized, and the initialization voltage is Vinit1 .
  • Vinit1 is at a high voltage (for example, the first power supply voltage, such as VDD or other high voltage)
  • the voltage of the gate of the first transistor T1 (that is, the first node N1 ) becomes Vinit1.
  • the fourth transistor T4 is turned on by the high voltage of the second reset control signal RST2 , so that the second node N2 (the second terminal 120 of the driving circuit 100 ) is initialized, and the initialization voltage is Vinit2 .
  • Vinit2 can be a low voltage (for example, it can be grounded or be other low voltage), for example, the voltage of Vinit2 can be less than the second power supply voltage (for example VSS), so that the voltage difference Vgs between the gate of the first transistor T1 and its source Large enough (for example, greater than 7V), so that the hysteresis state can be quickly eliminated, and the voltage difference Vgd between the gate of the first transistor T1 and its drain is equal to the difference between Vinit1 and VDD and smaller than Vth, so the first transistor T1 is only in There are two states, the off state and the saturation state, which are conducive to stabilizing the characteristics of the first transistor T1.
  • VSS the second power supply voltage
  • the fifth transistor T5 is cut off by the low voltage of the first light-emitting control signal EM1, which prevents the input of the first power supply voltage.
  • the second node N2 connected with two poles is also at a low voltage, so that the light emitting device EL is in a non-luminous state.
  • the third transistor T3 can use an oxide thin film transistor to reduce low-frequency leakage, so that the first node N1 maintains a low voltage, so that the first transistor T1 is in an off state for a long time, and the light-emitting device EL is in a non-light-emitting state for a long time. Eliminated flickering.
  • the second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data signal Vdata.
  • the first reset control signal RST1 is input, the first reset circuit 410 is turned on, and the first initialization voltage Vinit1 is applied to the control terminal 130 of the driving circuit 100 through the first reset circuit 410 to turn on the driving circuit 100 , input the first light-emitting control signal, turn on the first light-emitting control circuit 500, and at the same time, stop inputting the second reset control signal, and turn off the second reset circuit 420, so that the drive circuit 100 and the storage circuit 300 can be turned on. 100 for threshold compensation.
  • the first reset control signal RST1 is kept at a high voltage, so that the third transistor T3 is kept turned on, so that the voltage of the first node N1 is kept at the first initialization voltage Vinit1 , for example, may be a high voltage.
  • the second reset control signal RST2 is at a low voltage, so that the fourth transistor T4 is turned off.
  • the first initialization voltage Vinit1 of the first node N1 is a high voltage, for example, higher than VDD
  • the voltage of the third node N3 is a high voltage, for example, VDD.
  • the first light emission control signal EM1 can be a high voltage, so that the fifth transistor T5 is turned on, and the voltage of the second node N2 gradually increases from the initial second initialization voltage Vinit2 until the gate of the first transistor T1 and its source
  • the voltage difference Vgs of the first transistor T1 is equal to the threshold voltage Vth of the first transistor T1.
  • the voltage of the second node N2 is the difference between the first initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1. Therefore, the threshold voltage Vth of the first transistor T1 written to both ends of the first capacitor C1.
  • the light-emitting device EL connected to the second node N2 can be regarded as a capacitor, and its capacitance value is much larger than that of the first capacitor C1, the voltage at the second node N2 is almost unchanged, and remains the first capacitor in the previous stage t2.
  • the difference between the initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1 compensates the threshold voltage Vth of the first transistor T1 to complete threshold voltage compensation.
  • the second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data signal Vdata.
  • the gate scanning signal GN is input, the data writing circuit 200 is turned on, the data signal Vdata is written into the control terminal 130 of the drive circuit 100 through the data writing circuit 200, and the written data is stored in the storage circuit 300.
  • Data signal Vdata For example, in the data writing phase t3, the first light emission control signal EM1 may be at a low voltage, so that the fifth transistor T5 is turned off.
  • the first reset control signal RST1 is at a low voltage, so that the third transistor T3 is turned off.
  • the second reset control signal RST2 is at a low voltage, so that the fourth transistor T4 is turned off. Meanwhile, the second transistor T2 is turned on by the high voltage of the gate scan signal GN.
  • the voltage of the first node N1 changes from the first initialization voltage Vinit1 to a higher voltage, such as Vdata, that is, the data voltage Vdata (the voltage of the data signal Vdata), so that the first transistor T1 is turned on.
  • Vdata the voltage of the data signal Vdata
  • the storage capacitor C1 can store the data voltage Vdata, thereby completing data writing.
  • the mobility compensation stage t4 stop inputting the first reset control signal RST1, close the first reset circuit 410, stop inputting the second reset control signal, close the second reset circuit 420, input the gate scanning signal GN, and open the data writing circuit 200. Input a first light emission control signal to turn on the first light emission control circuit 500, so that mobility compensation can be performed through the turned on first light emission control circuit 500 and the turned on data writing circuit 200.
  • the first light emission control signal EM1 may be at a high voltage, thereby turning on the fifth transistor T5.
  • the second reset control signal RST2 is at a low voltage, so that the fourth transistor T4 is turned off.
  • the first reset control signal RST1 is at a low voltage, so that the third transistor T3 is turned off.
  • the gate scan signal GN remains at a high voltage, so that the second transistor T2 remains turned on.
  • the first transistor T1 is turned on, and the leakage current Ids flows from the first power supply voltage terminal, such as the VDD terminal, to the second node N2, and the voltage of the second node N2 gradually increases by ⁇ V.
  • the N2 voltage V N2 is the first A sum of the difference between the initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1 and the gradually increasing voltage ⁇ V, as described in the following formula:
  • V N2 Vinit1-Vth+ ⁇ V
  • V N2 is the voltage of the second node N2
  • Vinit1 is the voltage of the second node N2
  • V N2 is the first initialization voltage
  • Vth is the threshold voltage of the first transistor T1
  • ⁇ V is the gradual increase of the voltage of the second node N2 value.
  • the voltage of the first node N1 is still the data voltage Vdata due to the conduction of the second transistor T2. Because the driving current of the first transistor T1 is described by the following formula:
  • Ids is the leakage current of the first transistor T1
  • k is a constant coefficient
  • ⁇ is the mobility of the first transistor T1
  • Vgs is the voltage difference between the gate of the first transistor T1 and its source
  • Vth is the voltage difference of the first transistor T1 threshold voltage.
  • the first transistor T1 The voltage difference Vgs between the gate of a transistor T1 and its source is smaller, so (Vgs-Vth) 2 is smaller, and because the mobility ⁇ of the first transistor T1 is larger, the leakage current Ids of the first transistor T1 is corrected .
  • the driving currents of driving transistors with different mobilities have little difference under the same data voltage Vdata.
  • the first light emission control signal is input, and the first light emission control circuit 500 is turned on, so that the first power supply voltage can drive the light emitting element to emit light through the first light emission control circuit 500 and the drive circuit 100 turned on.
  • the first light emitting control signal EM1 may be at a high voltage, so as to turn on the fifth transistor T5.
  • the first reset control signal RST1 is at a low voltage, so that the third transistor T3 is turned off.
  • the second reset control signal RST2 is at a low voltage, so that the fourth transistor T4 is turned off.
  • the gate scan signal GN is at a low voltage, so that the second transistor T2 is turned off. At this time, the voltage of the second node N2 rises beyond the turn-on voltage of the light emitting device EL, and the light emitting device EL starts to emit light.
  • the voltage of the second node N2 will finally reach the turn-on voltage of the light emitting device, and at the same time Since the first node N1 and the second node N2 are connected through the first capacitor C1, the voltage of the first node N1 also rises to a stable state following the voltage of the second node N2, even if the voltages of the two nodes N1 and N2 change, The voltage difference between the two nodes N1 and N2, that is, the voltage difference Vgs between the gate of the first transistor T1 and its source can remain unchanged, so the luminous current I is constant, as described in the following formula:
  • the pixel circuit has the technical effects of threshold voltage compensation, mobility ⁇ compensation and voltage drop (IR Drop) compensation.
  • the third transistor T3 connected to the first node N1 can be replaced by a thin film transistor with lower leakage such as an oxide thin film transistor, which can reduce low frequency leakage, so that the voltage of the first node N1 can be maintained and light can be emitted.
  • the device EL does not flicker when it emits light.
  • FIG. 5C is a signal timing diagram of a pixel circuit driving method provided by at least some embodiments of the present disclosure.
  • the driving method of the pixel circuit disclosed in FIG. 5C is almost the same as the driving method of the pixel circuit disclosed in FIG. 4C described above.
  • the working principle of the pixel circuit shown in FIG. 5A will be described by taking the pixel circuit shown in FIG. 5A as an example in which the pixel circuit structure shown in FIG. 5B is implemented in conjunction with the signal timing diagram shown in FIG. 5C .
  • the driving method provided by this embodiment may include five stages, which are initialization stage t1, threshold voltage compensation stage t2, data writing stage t3, mobility compensation stage t4, and light emitting stage t5.
  • the timing waveforms of the individual signals in each phase are shown in 5C.
  • the pixel circuit 10 shown in FIG. 5B corresponding to the signal timing diagram of the pixel circuit driving method shown in FIG. 5C is compared to the signal timing diagram corresponding to the pixel circuit driving method shown in FIG. 4C shown in FIG. 4B.
  • the pixel circuit 10 shown in FIG. 5B differs in that the pixel circuit 10 shown in FIG. 5B adds a sixth transistor T6 for implementing the third reset control circuit 430 .
  • the gate of the sixth transistor T6 is connected to the third reset control signal terminal to receive the third reset control signal RST3, the first electrode of the sixth transistor T6 is connected to the hold voltage terminal to receive the hold voltage Vhold, and the sixth transistor T6
  • the second pole is connected to the third node N3 (the first end 110 of the drive circuit 100 ).
  • the difference between the driving method provided by this embodiment and the driving method shown in FIG. 4C is that the third reset control signal RST3 can be a high voltage, so that the sixth transistor T6 transistor is turned on, the first light-emitting control signal EM1 can be at a low voltage, so that the fifth transistor T5 is turned off, so that in the Vth compensation phase, the second node N2 can be charged by holding the voltage, such as Vhold, until the second node The voltage of N2 rises to the difference between the first initialization voltage Vinit2 and the threshold voltage Vth of the first transistor T1.
  • the holding voltage of the third node N3 may be, for example, Vhold, for example, may be higher than VDD.
  • Vhold for example, may be higher than VDD.
  • the voltage difference Vgd between the gate of the first transistor T1 and its drain is equal to the difference between Vinit1 and Vhold and less than Vth (for example, less than 0V), so the first transistor T1 is only in two states: off state and saturation state , so that it is beneficial to stabilize the characteristics of the first transistor T1.
  • the third reset control signal RST3 may share the same timing with the first reset control signal RST1 , so as to avoid the voltage drift of the third node N3 during the initialization phase.
  • the driving method shown in FIG. 5D is completely the same as the driving method shown in FIG. 5C , and will not be repeated here.
  • the second reset control signal RST2 and the third reset control signal RST3 can be in a subordinate relationship with each other, that is, the second reset control signal RST2 and the third reset control signal RST3 are sent by the same signal source , the second reset control signal RST2 and the third reset control signal RST3 belong to the signals corresponding to the upper and lower moments, so that the second reset control signal RST2 and the third reset control signal RST3 share the same GOA, which is beneficial to the display screen Simplify routing, increase resolution, achieve narrow bezels, and more.
  • FIG. 7C is a signal timing diagram of a pixel circuit driving method provided by at least some embodiments of the present disclosure.
  • the working principle of the pixel circuit shown in FIG. 7A will be described by taking the pixel circuit shown in FIG. 7A as an example in which the pixel circuit structure shown in FIG. 7B is implemented in conjunction with the signal timing diagram shown in FIG. 7C .
  • the driving method provided by this embodiment may include five stages, which are initialization stage t1, threshold voltage compensation stage t2, data writing stage t3, mobility compensation stage t4, and light emitting stage t5.
  • the timing waveforms of the individual signals in each phase are shown in 7C.
  • the first reset control signal RST1 is input, the first reset circuit 410 is turned on (that is, turned on), the voltage transmission control signal is input, the voltage transmission control circuit 800 is turned on, and the second power supply voltage is input through the first power supply voltage terminal, Thus, the second terminal 120 of the driving circuit 100 is reset.
  • the voltage transmission control signal Vtc is a high voltage, so that the eighth transistor T8 is turned on, and at the same time, the second power supply voltage can be, for example, VSS, transmitted to the third node N3 (the first pole of the first transistor T1) .
  • the first reset control signal RST1 is a high voltage, so that the third transistor T3 is turned on, and the voltage of the first node N1 is initialized to the first initialization voltage Vinit1 , for example, may be a high voltage, for example higher than VDD.
  • the second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data signal Vdata.
  • the voltage of the first node N1 is the first initialization voltage Vinit1 , for example, it may be a high voltage, for example higher than VDD.
  • the voltage of the third node N3 is a low voltage, such as the second power supply voltage VSS.
  • the voltage difference Vgs between the gate of the first transistor T1 and its source is equal to the difference between the first initialization voltage Vinit1 and the second power supply voltage VSS and is greater than the threshold voltage Vth of the first transistor T1, so that the first transistor T1 is in the conduction state.
  • the voltage of the second node N2 drops to a low voltage such as the second power supply voltage VSS, thereby resetting the voltage of the second node N2 (the second terminal 120 of the driving circuit 100 ).
  • the first reset control signal RST1 is input, the first reset circuit 410 is turned on (that is, turned on), the voltage transmission control signal is input, the voltage transmission control circuit 800 is turned on, and the first power supply is input through the first power supply voltage terminal voltage, thereby performing threshold compensation on the driving circuit 100 .
  • the voltage transmission control signal Vtc is a high voltage, so that the eighth transistor T8 is turned on, and at the same time, the first power supply voltage may be, for example, VDD, transmitted to the third node N3 (the first node of the first transistor T1 pole).
  • the first reset control signal RST1 is a high voltage, so that the third transistor T3 is turned on, and the voltage of the first node N1 is initialized to the first initialization voltage Vinit1 , for example, may be a high voltage, for example higher than VDD.
  • the second transistor T2 is turned off by the low voltage of the gate scan signal GN, preventing the input of the data signal Vdata.
  • the voltage of the first node N1 is the first initialization voltage Vinit1 , for example, it may be a high voltage, for example higher than VDD.
  • the voltage of the third node N3 is a high voltage, such as the first power supply voltage VDD.
  • the voltage of the second node N2 gradually rises from the initial VSS until the voltage difference Vgs between the gate and the source of the first transistor T1 is equal to the threshold voltage Vth of the first transistor T1, and at this time the voltage of the second node N2 is the first transistor T1.
  • the gate scanning signal GN is input, the data writing circuit 200 is turned on, the data signal Vdata is written into the control terminal 130 of the drive circuit 100 through the data writing circuit 200, and the written data is stored in the storage circuit 300.
  • Data signal Vdata For example, in the data writing phase t3, the voltage transmission control signal Vtc is at a low voltage, so that the eighth transistor T8 is turned off.
  • the first reset control signal RST1 is at a low voltage, so that the third transistor T3 is turned off.
  • the gate scan signal GN is at a high voltage, so that the second transistor T2 is turned on.
  • the voltage of the first node N1 changes from the first initialization voltage Vinit1 to a higher voltage, such as Vdata, that is, the data voltage Vdata (the voltage of the data signal Vdata), so that the first transistor T1 is turned on.
  • Vdata the voltage of the data signal Vdata
  • the storage capacitor C1 can store the data voltage Vdata, thereby completing data writing.
  • the input of the first reset control signal RST1 is stopped, the first reset circuit 410 is turned off, the gate scan signal GN is input, the data writing circuit 200 is turned on, the voltage transmission control signal is input, the voltage transmission control circuit 800 is turned on,
  • the first power supply voltage is input through the first power supply voltage terminal, so that the mobility compensation can be performed through the turned-on voltage transmission control circuit 800 and the data writing circuit 200 .
  • the voltage transmission control signal Vtc is a high voltage, so that the eighth transistor T8 is turned on, and at the same time, the first power supply voltage may be, for example, VDD, transmitted to the third node N3 (the first node of the first transistor T1 pole).
  • the first reset control signal RST1 is at a low voltage, so that the third transistor T3 is turned off.
  • the gate scan signal GN remains at a high voltage, so that the second transistor T2 remains turned on.
  • the first transistor T1 is turned on, and the driving current Ids flows from the first power supply voltage terminal, such as the VDD terminal, to the second node N2, and the voltage of the second node N2 gradually increases by ⁇ V.
  • the N2 voltage V N2 is the first A sum of the difference between the initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1 and the gradually increasing voltage ⁇ V, as described in the following formula:
  • V N2 Vinit1-Vth+ ⁇ V
  • V N2 is the voltage of the second node N2
  • Vinit1 is the voltage of the second node N2
  • V N2 is the first initialization voltage
  • Vth is the threshold voltage of the first transistor T1
  • ⁇ V is the gradual increase of the voltage of the second node N2 value.
  • the voltage of the first node N1 is still the data voltage Vdata due to the conduction of the second transistor T2. Because the driving current of the first transistor T1 is described by the following formula:
  • Ids is the driving current of the first transistor T1
  • k is a constant coefficient
  • ⁇ is the mobility of the first transistor T1
  • Vgs is the voltage difference between the gate of the first transistor T1 and its source
  • Vth is the voltage difference of the first transistor T1 threshold voltage.
  • the first transistor T1 The voltage difference Vgs between the gate of a transistor T1 and its source is smaller, so (Vgs-Vth) 2 is smaller, and because the mobility ⁇ of the first transistor T1 is larger, the drive current Ids of the first transistor T1 is corrected .
  • the driving currents of driving transistors with different mobilities have little difference under the same data voltage Vdata.
  • the first power supply voltage can drive the light-emitting element to emit light through the turned-on voltage transmission control circuit 800 and the turned-on driving circuit 100 .
  • the voltage transmission control signal Vtc is a high voltage, so that the eighth transistor T8 is turned on, and at the same time, the first power supply voltage can be, for example, VDD, transmitted to the third node N3 (the first pole of the first transistor T1) .
  • the first reset control signal RST1 is at a low voltage, so that the third transistor T3 is turned off.
  • the gate scan signal GN is at a low voltage, so that the second transistor T2 is turned off. At this time, the voltage of the second node N2 rises beyond the turn-on voltage of the light emitting device EL, and the light emitting device EL starts to emit light.
  • the voltage of the second node N2 will finally reach the turn-on voltage of the light emitting device, and at the same time Since the first node N1 is connected to the second node N2 through the first capacitor C1, the voltage of the first node N1 also follows the voltage of the second node N2 to rise to a stable state, even if the voltages of the two nodes N1 and N2 change, N1
  • the voltage difference between the two nodes, N2, that is, the voltage difference Vgs between the gate of the first transistor T1 and its source can remain unchanged, so the luminous current I is constant, as described in the following formula:
  • I is the light emitting current
  • k is a constant coefficient
  • ⁇ is the mobility of the first transistor T1
  • Vdata is a data signal voltage
  • ⁇ V is a gradually increasing value of the voltage of the second node N2. Therefore, the pixel circuit has the technical effects of threshold voltage compensation, mobility ⁇ compensation and voltage drop (IR Drop) compensation.
  • FIG. 8C is a signal timing diagram of a pixel circuit driving method provided by at least some embodiments of the present disclosure.
  • the working principle of the pixel circuit shown in FIG. 8A will be described below in conjunction with the signal timing diagram shown in FIG. 8C , taking the pixel circuit shown in FIG. 8A as an example in which the pixel circuit structure shown in FIG. 8B is implemented.
  • the driving method provided by this embodiment may include five stages, which are initialization stage t1, threshold voltage compensation stage t2, data writing stage t3, mobility compensation stage t4, and light emitting stage t5.
  • the timing waveforms of the individual signals in each phase are shown in 8C.
  • the second reset control signal RST2 is input, the second reset circuit 420 is turned on (that is, turned on), the gate scanning signal GN is input, the data writing circuit 200 is turned on, and the reference voltage Vref is input through the data writing circuit 200
  • the control terminal 130 of the driving circuit 100 is thereby reset to the second terminal 120 of the driving circuit 100 .
  • the first light emission control signal EM1 may be at a low voltage, so that the fifth transistor T5 is turned off.
  • the second reset control signal RST2 is a high voltage, so that the fourth transistor T4 is turned on, so that the initialization of the second node N2 is completed and the voltage of the second node N2 is the second initialization voltage Vinit2, for example, a low voltage, so that the first transistor T4 T1 conducts.
  • the voltage of the first pole of the light-emitting device EL such as the anode point, is also the second initialization voltage Vinit2, so as to reset the light-emitting device EL and make it not emit light.
  • the gate scan signal GN may be a high voltage, thereby turning on the second transistor T2.
  • the data signal terminal transmits the reference voltage Vref, for example, the first initialization voltage Vinit1, to the first electrode of the transistor T2, because the second transistor T2 is in the conduction state, at this time, the voltage Vinit1 of the first node N1 is a high voltage , for example higher than VDD, the voltage Vinit2 of the second node N2 is a low voltage, for example lower than VSS, and the third node N3 remains at the first power supply voltage, for example VDD.
  • Vref for example, the first initialization voltage Vinit1
  • Vinit2 of the second node N2 is a low voltage, for example lower than VSS
  • the third node N3 remains at the first power supply voltage, for example VDD.
  • the voltage difference Vgs between the gate of the first transistor T1 and its source is equal to the difference between the voltage Vinit2 of the second node N2 and the voltage Vinit1 of the first node N1 and is higher than the threshold voltage Vth of the first transistor T1, so that the first transistor T1 is turned on, and the voltage difference Vgd between the gate of the first transistor T1 and its drain is equal to the difference between Vinit1 and VDD and smaller than Vth, so the first transistor T1 is only in two states of off state and saturation state, which is conducive to stability Characteristics of the first transistor T1.
  • the input of the second reset control signal is stopped, the second reset circuit 420 is turned off, the gate scan signal GN is input, the data writing circuit 200 is turned on, and the reference voltage Vref is input into the driving circuit 100 through the data writing circuit 200
  • the control terminal 130 of the control terminal 130 inputs the first light emission control signal to turn on the first light emission control circuit 500 , so that threshold compensation can be performed on the drive circuit 100 through the turned on drive circuit 100 and storage circuit 300 .
  • the first light emission control signal EM1 may be at a high voltage, thereby turning on the fifth transistor T5.
  • the second reset control signal RST2 is at a low voltage, so that the fourth transistor T4 is turned off.
  • the gate scan signal GN may be a high voltage, thereby turning on the second transistor T2.
  • the data signal end transmits the reference voltage Vref, for example, the first initialization voltage Vinit1, to the first pole of the transistor T2, and because the second transistor T2 is in the conduction state, it is connected to the second pole of the second transistor T2
  • the voltage of the first node N1 is also the first initialization voltage Vinit1, for example, it may be a high voltage.
  • the first initialization voltage Vinit1 of the first node N1 is a high voltage, for example higher than VDD
  • the third node N3 is a high voltage, for example VDD
  • the voltage of the second node N2 is changed from the initial second initialization voltage Vinit2 gradually rises until the voltage difference Vgs between the gate and source of the first transistor T1 is equal to the threshold voltage Vth of the first transistor T1, at this time the voltage of the second node N2 is equal to the first initialization voltage Vinit1 and the first transistor T1 Therefore, the threshold voltage Vth of the first transistor T1 is written to both ends of the first capacitor C1.
  • the light-emitting device EL connected to the second node N2 can be regarded as a capacitor, and its capacitance value is much larger than that of the first capacitor C1, the voltage at the second node N2 is almost unchanged, and remains the first capacitor in the previous stage t2.
  • the difference between the initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1 compensates the threshold voltage Vth of the first transistor T1 to complete threshold voltage compensation.
  • the gate scanning signal GN is input, the data writing circuit 200 is turned on, the data signal Vdata is written into the control terminal 130 of the drive circuit 100 through the data writing circuit 200, and the written data is stored in the storage circuit 300.
  • Data signal Vdata For example, in the data writing phase t3, the first light emission control signal EM1 may be at a low voltage, so that the fifth transistor T5 is turned off.
  • the second reset control signal RST2 is at a low voltage, so that the fourth transistor T4 is turned off.
  • the gate scan signal GN may be a high voltage, thereby turning on the second transistor T2.
  • the data signal terminal transmits the data voltage Vdata to the first electrode of the transistor T2, because the second transistor T2 is in the conduction state, at this time, the voltage of the first node N1 changes from the first initialization voltage Vinit1 to a higher voltage, For example, it may be Vdata, that is, the data voltage Vdata (the voltage of the data signal Vdata), so that the first transistor T1 is turned on.
  • Vdata the data voltage Vdata (the voltage of the data signal Vdata)
  • the storage capacitor C1 can store the data voltage Vdata, thereby completing data writing.
  • the input of the second reset control signal is stopped, the second reset circuit 420 is turned off, the gate scan signal GN is input, the data writing circuit 200 is turned on and the data voltage Vdata is input, the first light emission control signal is input, and the second light emission control signal is turned on.
  • a light emission control circuit 500 thus, mobility compensation can be performed by the first light emission control circuit 500 being turned on and the data writing circuit 200 being turned on.
  • the first light emission control signal EM1 may be at a high voltage, thereby turning on the fifth transistor T5.
  • the second reset control signal RST2 is at a low voltage, so that the fourth transistor T4 is turned off.
  • the gate scan signal GN may be a high voltage, thereby turning on the second transistor T2.
  • the data signal terminal transmits the data voltage Vdata to the first electrode of the transistor T2, because the second transistor T2 is in the conduction state, at this time, the voltage of the first node N1 remains at a higher voltage, such as Vdata.
  • the first transistor T1 is turned on, and the driving current Ids flows from the first power supply voltage terminal, such as the VDD terminal, to the second node N2, and the voltage of the second node N2 gradually increases by ⁇ V.
  • the N2 voltage V N2 is the first A sum of the difference between the initialization voltage Vinit1 and the threshold voltage Vth of the first transistor T1 and the gradually increasing voltage ⁇ V, as described in the following formula:
  • V N2 Vinit1-Vth+ ⁇ V
  • V N2 is the voltage of the second node N2
  • Vinit1 is the voltage of the second node N2
  • V N2 is the first initialization voltage
  • Vth is the threshold voltage of the first transistor T1
  • ⁇ V is the gradual increase of the voltage of the second node N2 value.
  • the voltage of the first node N1 is still the data voltage Vdata due to the conduction of the second transistor T2. Because the driving current of the first transistor T1 is described by the following formula:
  • Ids is the driving current of the first transistor T1
  • k is a constant coefficient
  • ⁇ is the mobility of the first transistor T1
  • Vgs is the voltage difference between the gate of the first transistor T1 and its source
  • Vth is the voltage difference of the first transistor T1 threshold voltage.
  • the first transistor T1 The voltage difference Vgs between the gate of a transistor T1 and its source is smaller, so (Vgs-Vth) 2 is smaller, and because the mobility ⁇ of the first transistor T1 is larger, the drive current Ids of the first transistor T1 is obtained Correction.
  • the driving currents of driving transistors with different mobilities have little difference under the same data voltage Vdata.
  • the first power supply voltage can drive the light emitting element to emit light through the first light emitting control circuit 500 and the driving circuit 100 being turned on.
  • the first light emitting control signal EM1 may be at a high voltage, so as to turn on the fifth transistor T5.
  • the second reset control signal RST2 is at a low voltage, so that the fourth transistor T4 is turned off.
  • the gate scan signal GN is at a low voltage, so that the second transistor T2 is turned off.
  • the voltage of the second node N2 rises beyond the turn-on voltage of the light emitting device EL, and the light emitting device EL starts to emit light. Because it is driven by a constant current, the voltage of the second node N2 will finally reach the turn-on voltage of the light emitting device, and at the same time Since the first node N1 and the second node N2 are connected through the first capacitor C1, the voltage of the first node N1 also follows the voltage of the second node N2 to rise to a stable state, even if the voltages of the two nodes N1 and N2 change, N1 The voltage difference between the two nodes, N2, that is, the voltage difference Vgs between the gate of the first transistor T1 and its source can remain unchanged, so the luminous current I is constant, as described in the following formula:
  • the pixel circuit has the technical effects of threshold voltage compensation, mobility ⁇ compensation and voltage drop (IR Drop) compensation.
  • At least some embodiments of the present disclosure further provide a display panel, including a plurality of pixel units arranged in an array, for example, each of the plurality of pixel units includes the pixel circuit provided by any embodiment of the present disclosure.
  • Fig. 9A is a schematic block diagram of a display panel provided by some embodiments of the present disclosure. As shown in FIG. 9A , the display panel 11 is disposed in the display device 1 and is electrically connected to the gate driver 12 , the timing controller 13 and the data driver 14 .
  • the display panel 11 includes a pixel unit P defined by intersections of multiple scan lines GL and multiple data lines DL; a gate driver 12 is used to drive multiple scan lines GL; a data driver 14 is used to drive multiple data lines DL; timing
  • the controller 13 is used for processing the image data RGB input from the outside of the display device 1, providing the processed image data RGB to the data driver 14, and outputting the scan control signal GCS and the data control signal DCS to the gate driver 12 and the data driver 14, so as to control
  • the gate driver 12 and the data driver 14 perform control.
  • the display panel 11 includes a plurality of pixel units P, and the pixel units P include any pixel circuit 10 provided in the above-mentioned embodiments.
  • the pixel circuit 10 shown in FIG. 2B is included.
  • the display panel 11 further includes a plurality of scan lines GL and a plurality of data lines DL.
  • the plurality of scanning lines are correspondingly connected to the data writing circuit 200 in the pixel circuit 10 of each row of pixel units to provide gate scanning signals, and the plurality of scanning lines are also correspondingly connected to the pixel circuits 10 of each row of pixel units
  • the first reset circuit 410 in the circuit 410 provides a first reset control signal.
  • the pixel unit P is disposed at the intersection area of the scan line GL and the data line DL.
  • each pixel unit P is connected to two scanning lines GL (supply gate scanning signal and first reset control signal respectively), one data line DL, a first power supply voltage for supplying A power supply voltage line, a second power supply voltage line for supplying the second power supply voltage, and a first initialization voltage line for supplying the first initialization voltage.
  • the first voltage line or the second voltage line may be replaced by a corresponding plate-shaped common electrode (eg, common anode or common cathode). It should be noted that only part of the pixel unit P, the scan line GL, and the data line DL are shown in FIG. 9A .
  • the plurality of pixel units P are arranged in multiple rows, the first reset circuit 410 of the pixel circuit of each row of pixel unit P is connected to a scanning line GL to receive the first reset control signal, and the pixel circuit of each row of pixel unit P
  • the data writing circuit 200 is connected to another scan line GL to receive a gate scan signal.
  • the data line DL of each column is connected to the data writing circuit 200 in the pixel circuit 10 of this column to provide a data signal.
  • FIG. 9B is a schematic block diagram of a display panel provided by some embodiments of the present disclosure.
  • the connection relationship between the display panel 11 and the display device shown in FIG. 9B is the same as that of the panel shown in FIG. 9A , and will not be repeated here.
  • the display panel 11 includes a plurality of pixel units P, and the pixel units P include any pixel circuit 10 provided in the above-mentioned embodiments.
  • the pixel circuit 10 shown in FIG. 7B is included.
  • the display panel 11 further includes a plurality of scan lines GL and a plurality of data lines DL.
  • the multiple scan lines are also correspondingly connected to the voltage transmission circuit 800 in the pixel circuit 10 of each row of pixel units to provide voltage transmission control signals.
  • the pixel unit P is disposed at the intersection area of the scan line GL and the data line DL.
  • each pixel unit P is further connected to one scanning line GL (providing a first light emission control signal) compared to each pixel unit shown in FIG. 9A . It should be noted that only part of the pixel unit P, the scan line GL, and the data line DL are shown in FIG. 9B .
  • the plurality of pixel units P are arranged in multiple rows, and the first light emission control circuit 500 of the pixel circuit of each row of pixel units P is connected to a scanning line GL to receive the first light emission control signal.
  • the display panel includes a first power supply voltage line that can provide a second power supply voltage.
  • the pixel circuit can be powered by the first power supply
  • the voltage terminal is connected to the first supply voltage line providing the second supply voltage, so that the second supply voltage can be received from the first supply voltage terminal.
  • the display panel 11 includes a plurality of pixel units P, and the pixel units P include any pixel circuit 10 provided in the above-mentioned embodiments.
  • the pixel circuit 10 shown in FIG. 8B is included.
  • the display panel includes a scan line GL that can provide a second reset control signal.
  • the pixel circuit can provide a second reset control signal through the first reset control signal terminal.
  • the scanning line GL of the signal is connected so that the second reset control signal can be received from the first reset control signal terminal.
  • the display panel includes a data line DL that can provide the first initialization voltage
  • the pixel circuit can be connected to the data line DL that provides the first initialization voltage through the data signal terminal, so that it can receive the first reset from the data signal terminal. control signal.
  • FIG. 9C is a schematic block diagram of a display panel provided by some embodiments of the present disclosure.
  • the connection relationship between the display panel 11 and the display device shown in FIG. 9C is the same as that of the panel shown in FIG. 9A , and will not be repeated here.
  • the display panel 11 shown in FIG. 9C includes a plurality of pixel units P including any of the pixel circuits 10 provided in the above-mentioned embodiments.
  • the pixel circuit 10 shown in FIG. 3B is included.
  • the display panel 11 further includes a plurality of scan lines GL and a plurality of data lines DL.
  • the multiple scan lines are also correspondingly connected to the second reset circuit 420 in the pixel circuit 10 of each row of pixel units to provide a second reset control signal.
  • the pixel unit P is disposed at the intersection area of the scan line GL and the data line DL.
  • each pixel unit P is further connected to a scanning line GL (providing a second reset control signal) and a first scanning line GL for providing a second initialization voltage compared to each pixel unit shown in FIG. 9A .
  • Two initialization voltage lines It should be noted that only part of the pixel unit P, the scan line GL, and the data line DL are shown in FIG. 9C .
  • the plurality of pixel units P are arranged in multiple rows, and the second reset circuit 420 of the pixel circuit of each row of pixel units P is connected to a scanning line GL to receive the second reset control signal, and the second reset circuit 420 of the pixel circuit of each row of pixel units P
  • the second initialization voltage terminal is connected to the second initialization voltage line to receive the second initialization voltage.
  • FIG. 9D is a schematic block diagram of a display panel provided by some embodiments of the present disclosure.
  • the connection relationship between the display panel 11 and the display device shown in FIG. 9D is the same as that of the panel shown in FIG. 9C , and will not be repeated here.
  • the display panel 11 shown in FIG. 9D includes a plurality of pixel units P, and the pixel units P include any of the pixel circuits 10 provided in the above-mentioned embodiments.
  • the pixel circuit 10 shown in FIG. 4B is included.
  • the display panel 11 further includes a plurality of scan lines GL and a plurality of data lines DL.
  • the multiple scan lines are also correspondingly connected to the first light emission control circuit 500 in the pixel circuit 10 of each row of pixel units to provide the first light emission control signal.
  • the pixel unit P is disposed at the intersection area of the scan line GL and the data line DL.
  • each pixel unit P is further connected to one scanning line GL (providing a first light emission control signal) compared to each pixel unit shown in FIG. 9C . It should be noted that only part of the pixel unit P, the scan line GL, and the data line DL are shown in FIG. 9D .
  • the plurality of pixel units P are arranged in multiple rows, and the first light emission control circuit 500 of the pixel circuit of each row of pixel units P is connected to a scanning line GL to receive the first light emission control signal.
  • the display panel 11 includes a plurality of pixel units P, and the pixel units P include any pixel circuit 10 provided in the above-mentioned embodiments.
  • the pixel circuit 10 shown in FIG. 6B is included.
  • the display panel includes a scan line GL that can provide a second light emission control signal.
  • the pixel circuit 10 can be connected to the scan line GL that provides a second light emission control signal through the first light emission control signal terminal, so that it can emit light from the first light emission control signal.
  • the control signal end receives the second lighting control signal.
  • the second reset control signal and the gate scanning signal can share one scanning line GL, which can simplify the layout space around the display panel, thereby realizing the development of a high-resolution display panel.
  • FIG. 9E is a schematic block diagram of a display panel provided by some embodiments of the present disclosure.
  • the connection relationship between the display panel 11 and the display device shown in FIG. 9E is the same as that of the panel shown in FIG. 9D , and will not be repeated here.
  • the display panel 11 shown in FIG. 9E includes a plurality of pixel units P, and the pixel units P include any of the pixel circuits 10 provided in the above-mentioned embodiments.
  • the pixel circuit 10 shown in FIG. 5B is included.
  • the display panel 11 further includes a plurality of scan lines GL and a plurality of data lines DL.
  • the multiple scan lines are also correspondingly connected to the third reset circuit 430 in the pixel circuit 10 of each row of pixel units to provide a third reset control signal.
  • the pixel unit P is disposed at the intersection area of the scan line GL and the data line DL.
  • each pixel unit P is also connected to a scanning line GL (providing a third reset control signal) and a holding voltage line for providing a holding voltage compared to each pixel unit shown in FIG. 9D . It should be noted that only part of the pixel unit P, the scan line GL, and the data line DL are shown in FIG. 9E .
  • the plurality of pixel units P are arranged in multiple rows, and the third reset circuit 430 of the pixel circuit of each row of pixel unit P is connected to a scanning line GL to receive the third reset control signal, and the pixel circuit of each row of pixel unit P
  • the holding voltage terminal is connected to the holding voltage line to receive the holding voltage.
  • the third reset circuit 430 of the pixel circuit of the pixel unit P can also realize the communication with the third reset circuit 430 by receiving the second reset control signal.
  • the technical effect of receiving the third reset control signal is the same, that is, the third reset control signal received by the third reset circuit 430 can be replaced by the second reset control signal.
  • the second reset control signal and the third reset control signal belong to the signals corresponding to the upper and lower moments, so that the second reset control signal and the third reset control signal can share one scanning line GL, which can simplify the layout around the display panel. layout space so that the development of high-resolution display panels can be realized.
  • the gate driver 12 supplies a plurality of gate signals to a plurality of scan lines GL according to a plurality of scan control signals GCS from the timing controller 13 .
  • the plurality of gate signals include a gate scan signal, a first reset control signal, a second reset control signal, a third reset control signal, a first light emission control signal, and a second light emission control signal. These signals are supplied to each pixel unit P through a plurality of scan lines GL.
  • the data driver 14 converts digital image data RGB input from the timing controller 13 into data signals according to a plurality of data control signals DCS from the timing controller 13 using a reference gamma voltage.
  • the data driver 14 supplies converted data signals to a plurality of data lines DL.
  • the timing controller 13 processes externally input image data RGB to match the size and resolution of the display panel 11 , and then supplies the processed image data to the data driver 14 .
  • the timing controller 13 generates a plurality of scanning control signals GCS and a plurality of data control signals DCS using synchronous signals (such as dot clock DCLK, data enable signal DE, horizontal synchronous signal Hsync, and vertical synchronous signal Vsync) input from the display device.
  • the timing controller 13 provides the generated scan control signal GCS and data control signal DCS to the gate driver 12 and the data driver 14 respectively for controlling the gate driver 12 and the data driver 14 .
  • the data driver 14 can be connected to a plurality of data lines DL to provide a data signal Vdata; meanwhile, it can also be connected to a plurality of first voltage lines, a plurality of second voltage lines and a plurality of initialization voltage lines to provide a first voltage, a second voltage, and an initialization voltage.
  • the gate driver 12 and the data driver 14 may be implemented as semiconductor chips.
  • the display device 1 may also include other components, such as a signal decoding circuit, a voltage conversion circuit, etc. These components may be existing conventional components, and will not be described in detail here.
  • the display device in this embodiment may be any product or component with a display function such as a monitor, a TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, and a navigator.
  • the display device may also include other conventional components or structures.
  • those skilled in the art may configure other conventional components or structures according to specific application scenarios. This is not limited.

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Abstract

一种像素电路及其驱动方法及显示面板。该像素电路包括驱动电路、数据写入电路、存储电路和第一复位电路；其中，驱动电路包括控制端、第一端和第二端，且被配置为控制流经第一端和第二端的用于驱动发光元件发光的驱动电流；数据写入电路被配置为在第一扫描信号的控制下将数据信号写入驱动电路的控制端；存储电路被配置为存储数据信号；第一复位电路被配置为在第一复位控制信号的控制下将第一初始化电压施加至驱动电路的控制端；其中，驱动电路和数据写入电路各自均包括N型薄膜晶体管，第一复位电路包括N型氧化物薄膜晶体管。

Description

像素电路及其驱动方法、显示面板
本申请要求于2021年7月30日递交的PCT专利申请PCT/CN2021/109900及2021年8月5日递交的中国专利申请第202110898671.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路及其驱动方法、显示面板。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板具有薄、轻、宽视角、主动发光、发光颜色连续可调、成本低、响应速度快、能耗小、驱动电压低、工作温度范围宽、生产工艺简单、发光效率高及可柔性显示等优点，在手机、平板电脑、数码相机等显示领域的应用越来越广泛。
发明内容
本公开至少一些实施例提供一种像素电路，包括驱动电路、数据写入电路、存储电路和第一复位电路；其中，所述驱动电路包括控制端、第一端和第二端，且被配置为控制流经所述第一端和所述第二端的用于驱动发光元件发光的驱动电流；所述数据写入电路被配置为在第一扫描信号的控制下将数据信号写入所述驱动电路的控制端；所述存储电路被配置为存储所述数据信号；所述第一复位电路被配置为在第一复位控制信号的控制下将第一初始化电压施加至所述驱动电路的控制端；其中，所述驱动电路和所述数据写入电路各自均包括N型薄膜晶体管，所述第一复位电路包括N型氧化物薄膜晶体管。
例如，在本公开一些实施例提供的像素电路中，所述驱动电路包括的所述N型薄膜晶体管为第一晶体管；所述第一晶体管的栅极作为所述驱动电路的控制端，所述第一晶体管的第一极作为所述驱动电路的第一端，所述第一晶体管的第二极作为所述驱动电路的第二端。
例如，在本公开一些实施例提供的像素电路中，所述数据写入电路包括的所述N型薄膜晶体管为第二晶体管；所述第二晶体管的栅极和第一扫描信号端连接以接收所述第一扫描信号，所述第二晶体管的第一极和数据信号端连接以接收所述数据信号，所述第二晶体管的第二极和所述驱动电路的控制端连接。
例如，在本公开一些实施例提供的像素电路中，所述存储电路包括存储电容，所述存储电容的第一极与所述驱动电路的控制端连接，所述存储电容的第二极与所述驱动电路的第二端连接。
例如，在本公开一些实施例提供的像素电路中，所述第一复位电路包括的所述N型氧 化物薄膜晶体管为第三晶体管；所述第三晶体管的栅极和第一复位控制信号端连接以接收所述第一复位控制信号，所述第三晶体管的第一极和第一初始化电压端连接以接收所述第一初始化电压，所述第七晶体管的第二极和所述驱动电路的控制端连接。
例如，在本公开一些实施例提供的像素电路中，还包括第二复位电路，其中，所述第二复位电路被配置为在第二复位控制信号的控制下将第二初始化电压施加至所述驱动电路的第二端。
例如，在本公开一些实施例提供的像素电路中，所述第二复位电路包括第四晶体管，所述第四晶体管为N型薄膜晶体管，所述第四晶体管的栅极和第二复位控制信号端连接以接收所述第二复位控制信号，所述第四晶体管的第一极和第二初始化电压端连接以接收所述第二初始化电压，所述第四晶体管的第二极和所述驱动电路的第二端连接。
例如，在本公开一些实施例提供的像素电路中，还包括第一发光控制电路，其中，所述第一发光控制电路被配置为在第一发光控制信号的控制下将第一电源电压施加至所述驱动电路的第一端。
例如，在本公开一些实施例提供的像素电路中，所述第一发光控制电路包括第五晶体管，所述第五晶体管为N型薄膜晶体管，所述第五晶体管的栅极和第一发光控制端连接以接收所述第一发光控制信号，所述第五晶体管的第一极和第一电源端连接以接收所述第一电源电压，所述第五晶体管的第二极和所述驱动电路的第一端连接。
例如，在本公开一些实施例提供的像素电路中，还包括第三复位电路，其中，第三复位电路被配置为在第三复位控制信号的控制下将保持电压施加至所述驱动电路的第一端，所述第三复位控制信号和所述第一复位控制信号至少部分时间段内同时为开启信号。
例如，在本公开一些实施例提供的像素电路中，所述第三复位电路包括第六晶体管，所述第六晶体管为N型薄膜晶体管，所述第六晶体管的栅极和第三复位控制信号端连接以接收所述第三复位控制信号，所述第六晶体管的第一极和保持电压端连接以接收所述保持电压，所述第六晶体管的第二极和所述驱动电路的第一端连接。
例如，在本公开一些实施例提供的像素电路中，所述第三复位控制信号与所述第一复位控制信号为同一控制信号。
例如，在本公开一些实施例提供的像素电路中，还包括第二发光控制电路，其中，所述第二发光控制电路被配置为在第二发光控制信号的控制下将所述驱动电流施加至所述发光元件的第一极。
例如，在本公开一些实施例提供的像素电路中，所述第二发光控制电路包括第七晶体管，所述第七晶体管为N型薄膜晶体管，所述第七晶体管的栅极和第二发光控制端连接以接收所述第二发光控制信号，所述第七晶体管的第一极和所述驱动电路的第二端连接，所述第七晶体管的第二极和所述发光元件的第一极连接。
例如，在本公开一些实施例提供的像素电路中，还包括电压传输电路，其中，所述电压传输电路被配置为在电压传输控制信号的控制下，在第一时间段内将第二电源电压传输 至所述驱动电路的第一端，以及在第二时间段内将不同于所述第二电源电压的第一电源电压传输至所述驱动电路的第一端。
例如，在本公开一些实施例提供的像素电路中，所述电压传输电路包括第八晶体管，所述第八晶体管为N型薄膜晶体管，所述第八晶体管的栅极和电压传输控制信号端连接以接收所述电压传输控制信号，所述第八晶体管的第一极和第一电源端连接，所述第八晶体管的第二极和所述驱动电路的第一端连接，所述第一电源端被配置为在所述第一时间段内提供所述第二电源电压，以及在所述第二时间段内提供所述第一电源电压。
本公开至少一些实施例提供一种显示面板，包括阵列排布的多个像素单元；其中，每个所述像素单元包括根据上述任一所述的像素电路。
本公开至少一些实施例提供一种像素电路的驱动方法，包括初始化阶段、阈值电压补偿阶段、数据写入与迁移率补偿阶段、发光阶段，其中，在所述初始化阶段，输入所述第一复位控制信号和所述第二复位控制信号，开启所述第一复位电路和所述第二复位电路，通过所述第一复位电路将所述第一初始化电压施加至所述驱动电路的控制端以对所述驱动电路的控制端进行复位，通过所述第二复位电路将所述第二初始化电压施加至所述驱动电路的第二端以对所述驱动电路的第二端进行复位；在所述阈值电压补偿阶段，输入所述第一复位控制信号，开启所述第一复位电路，通过所述第一复位电路将所述第一初始化电压施加至所述驱动电路的控制端，以导通所述驱动电路，停止输入所述第二复位控制信号，关闭所述第二复位电路，通过导通的所述驱动电路和所述存储电路进行阈值补偿；在所述数据写入阶段，输入所述栅极扫描信号，开启所述数据写入电路，通过所述数据写入电路将所述数据信号写入所述驱动电路的控制端，并通过所述存储电路存储写入的所述数据信号；在所述发光阶段，停止输入所述栅极扫描信号，关闭所述数据写入电路，使所述驱动电路将在所述存储电路存储的所述数据信号的控制下产生驱动电流，以驱动所述发光元件发光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种2T1C像素电路的示意图；
图1B为另一种2T1C像素电路的示意图；
图2A为本公开至少一些实施例提供的一种像素电路的示意框图；
图2B为图2A中所示的像素电路的一种具体实现示例的电路结构示意图；
图2C为图2B中所示的像素电路的驱动方法的信号时序图；
图3A为本公开至少一些实施例提供的一种像素电路的示意框图；
图3B为图3A中所示的像素电路的一种具体实现示例的电路结构示意图；
图3C为图3B中所示的像素电路的驱动方法的信号时序图；
图4A为本公开至少一些实施例提供的一种像素电路的示意框图；
图4B为图4A中所示的像素电路的一种具体实现示例的电路结构示意图；
图4C为图4B中所示的像素电路的驱动方法的信号时序图；
图5A为本公开至少一些实施例提供的一种像素电路的示意框图；
图5B为图5A中所示的像素电路的一种具体实现示例的电路结构示意图；
图5C为图5B中所示的像素电路的驱动方法的信号时序图；
图5D为本公开至少一些实施例提供的一种像素电路的驱动方法的信号时序图；
图6A为本公开至少一些实施例提供的一种像素电路的示意框图；
图6B为图6A中所示的像素电路的一种具体实现示例的电路结构示意图；
图6C为图6B中所示的像素电路的驱动方法的信号时序图；
图7A为本公开至少一些实施例提供的一种像素电路的示意框图；
图7B为图7A中所示的像素电路的一种具体实现示例的电路结构示意图；
图7C为图7B中所示的像素电路的驱动方法的信号时序图；
图8A为本公开至少一些实施例提供的一种像素电路的示意框图；
图8B为图8A中所示的像素电路的一种具体实现示例的电路结构示意图；
图8C为图8B中所示的像素电路的驱动方法的信号时序图；以及
图9A至图9F分别为本公开一实施例提供的一种显示面板的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本公开实施例的以下说明清楚且简明，可省略已知功能和已知部(元)件的详细说明。当本公开实施例的任一部(元)件在一个以上的附图中出现时，该部(元)件在每个附图中由相同或类似的参考标号表示。
OLED显示面板中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix，AM)驱动和无源矩阵(Passive Matrix，PM)驱动。其中，AMOLED显示面板在每一个像素的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的驱动电流的控制，从而使OLED根据需要发光。因此，AMOLED显示面板所需驱动电流小、功耗低、寿命更长，可以满足高分辨率多灰度的大尺寸显示需求。同时，AMOLED显示面板在可视角度、色彩的还原、功耗以及响应时间等方面具有明显的优势，适用于高信息含量、高分辨率的显示装置。
AMOLED显示面板中使用的基础像素电路可以为2T1C像素电路，即利用两个TFT(Thin-film transistor，薄膜晶体管)和一个存储电容Cs来实现驱动OLED发光的基本功能。
图1A和图1B分别示出了两种2T1C像素电路的示意图。
如图1A所示，一种2T1C像素电路包括开关晶体管T0、驱动晶体管N0以及存储电容Cs。例如，该开关晶体管T0的栅极连接扫描线以接收扫描信号Scan1，例如源极连接到数据信号线以接收数据信号Vdata，漏极连接到驱动晶体管N0的栅极；驱动晶体管N0的源极连接到第一电压端以接收第一电压VDD(高电压)，漏极连接到OLED的正极端；存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第一电压端；OLED的负极端连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。该2T1C像素电路的驱动方式是将像素的明暗(灰阶)经由两个TFT和存储电容Cs来控制。当通过扫描线施加扫描信号Scan1以开启开关晶体管T0时，数据驱动电路通过数据信号线送入的数据信号Vdata将经由开关晶体管T0对存储电容Cs充电，由此将数据信号Vdata存储在存储电容Cs中，且此存储的数据信号Vdata控制驱动晶体管N0的导通程度，由此控制流过驱动晶体管以驱动OLED发光的电流大小，即此电流决定该像素发光的灰阶。在图1A所示的2T1C像素电路中，开关晶体管T0为N型晶体管而驱动晶体管N0为P型晶体管。
如图1B所示，另一种2T1C像素电路也包括开关晶体管T0、驱动晶体管N0以及存储电容Cs，但是其连接方式略有改变，且驱动晶体管N0为N型晶体管。图1B的像素电路相对于图1A的变化之处包括：OLED的正极端连接到第一电压端以接收第一电压VDD(高电压)，而负极端连接到驱动晶体管N0的漏极，驱动晶体管N0的源极连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第二电压端。该2T1C像素电路的工作方式基本上与图1A所示的像素电路基本相同，这里不再赘述。
此外，对于图1A和图1B所示的像素电路，开关晶体管T0不限于N型晶体管，也可以为P型晶体管，由此控制其导通或截止的扫描信号Scan1的极性进行相应地改变即可。
OLED显示面板高低频切换时常画面闪烁，这种闪烁影响高品质画质，因此需要改进。究其原因是，在该OLED显示面板中，像素电路中的驱动晶体管(DTFT)是由低温多晶硅半 导体作为有源层制作的，其沟道本身因为缺陷态多而显现出明显的磁滞效应。TFT器件的磁滞效应指的是在一定的偏压下，TFT器件的电特性所表现出来的一种不确定性，即TFT器件电流的大小不仅与当前的偏压有关，还依赖于上一时刻TFT器件所处的状态。TFT的磁滞效应对于当前的平板显示技术已经造成了危害，比如上一时刻的图像往往会保留在下一时刻的图像显示中，导致显示错误。TFT器件的磁滞效应与栅介质、半导体材料和它们之间的界面态陷阱有关，这些陷阱会俘获和释放电荷，从而引起TFT器件阈值电压的改变，进而在相同的偏压下，引起沟道载流子浓度的变化，从而改变TFT的电特性。
因此，在上述2T1C的基本像素电路的基础上，使用磁滞效应较弱的有源层来制备DTFT，并且在重置或编程阶段进一步重置DTFT，使DTFT特性尽快回复到初始状态，从而减少低频下的残像、闪烁等现象，以获得画质的提升。
本公开至少一些实施例提供一种像素电路。该像素电路包括驱动电路、数据写入电路、存储电路和第一复位电路；其中，驱动电路包括控制端、第一端和第二端，且被配置为控制流经第一端和第二端的用于驱动发光元件发光的驱动电流；数据写入电路被配置为在栅极扫描信号的控制下将数据信号写入驱动电路的控制端；存储电路被配置为存储数据信号；第一复位电路被配置为在第一复位控制信号的控制下将第一初始化电压施加至驱动电路的控制端；其中，驱动电路和数据写入电路包括N型薄膜晶体管。第一复位电路包括N型氧化物薄膜晶体管。
本公开的一些实施例还提供对应于上述像素电路的驱动方法、显示面板。
在本公开的实施例提供的像素电路中，驱动电路和数据写入电路包括N型薄膜晶体管。第一复位电路包括N型氧化物薄膜晶体管，可以降低低频漏电，保持驱动电路控制端的电压使得发光不闪烁，并改善TFT器件磁滞，减少低频残像。
下面结合附图对本公开的一些实施例及其示例进行详细说明。
图2A为本公开至少一些实施例提供的一种像素电路的示意框图。如图2A所示，像素电路10包括驱动电路100、数据写入电路200、存储电路300、第一复位电路410和发光元件700。
例如，驱动电路100包括第一端110、第二端120和控制端130，且被配置为控制流经第一端110和第二端120的用于驱动发光元件700发光的驱动电流。例如，驱动电路100包括N型薄膜晶体管，例如N型氧化物薄膜晶体管。例如在一些实施例中，在发光阶段，驱动电路100可以向发光元件700提供驱动电流以驱动发光元件700进行发光，且可以根据需要显示的灰阶(不同的灰阶对应于不同的数据信号)提供相应的驱动电流发光。例如，发光元件700可以采用有机发光二极管(OLED)、迷你发光二极管(Mini LED)、微发光二极管(Micro LED)、量子点发光二极管(QLED)、无机发光二极管等，本公开的实施例包括但不限于此。
例如，第一复位电路410被配置为响应于第一复位控制信号RST1将第一初始化电压Vinitl施加至驱动电路100的控制端130。例如，第一复位电路410可以是N型氧化物薄膜 晶体管。例如，在一些实施例中，在初始化阶段，第一复位电路410响应于第一复位控制信号RST1而导通，从而可以将第一初始化电压Vinitl施加至驱动电路100的控制端130，以对驱动电路100进行初始化操作。N型氧化物薄膜晶体管可以采用IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)等作为薄膜晶体管的有源层，相对于采用LTPS(Low Temperature Poly Silicon，低温多晶硅)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及减小漏电流，从而在使得该像素电路可以适用于低频驱动的同时，还可以增加显示面板的分辨率。
例如，数据写入电路200被配置为响应于栅极扫描信号GN，将数据线传输的数据信号Vdata写入驱动电路100的控制端130。例如，数据写入电路200包括N型薄膜晶体管，例如N型氧化物薄膜晶体管。例如，在一些实施例中，在数据写入阶段，数据写入电路200响应于栅极扫描信号GN而导通，从而可以将数据线传输过来的数据信号Vdata写入驱动电路100的控制端130并存储于存储电路300中，以在发光阶段时使驱动电路100根据该数据信号Vdata产生驱动发光元件700发光的驱动电流。
例如，存储电路300被配置为存储写入的数据信号Vdata，且将驱动电路100的控制端130和第二端120电连接。例如，在一些实施例中，存储电路300包括存储电容，在数据写入和存储阶段，存储电容可以接收并存储数据写入电路200写入的数据信号Vdata。存储电路300将驱动电路100的控制端130和第二端120电连接，从而使驱动电路的阈值电压Vth的相关信息也相应地存储在存储电容中。
例如，在本公开的至少一些实施例中，在图2A所示的电路结构的基础上，如图3A所示，像素电路10还可以包括第二复位电路420，第二复位电路420被配置为在第二复位控制信号RST2的控制下将第二初始化电压Vinit2施加至驱动电路100的第二端120。例如，第二复位电路420可以包括N型薄膜晶体管，例如N型氧化物薄膜晶体管。例如，在一些实施例中，在初始化阶段，第二复位电路420响应于第二复位控制信号RST2而导通，从而可以将第二初始化电压Vinit2施加至驱动电路100的第二端120，以使驱动电路100的第二端120的电位根据第二初始化电压Vinit2初始化为第二初始化电压Vinit2，从而对驱动电路100的第二端进行初始化操作，消除之前的发光阶段的影响。
例如，在本公开的至少一些实施例中，在图3A所示的电路结构的基础上，如图4A所示，像素电路10还可以包括第一发光控制电路500。例如，在一些实施例中，第一发光控制电路500可以是N型薄膜晶体管，例如N型氧化物薄膜晶体管。例如，在一些实施例中，第一发光控制电路500被配置为响应于第一发光控制信号EM1将第一电源电压VDD施加至驱动电路100的第一端110，以使驱动电路100产生驱动电流。例如，在发光阶段，第一发光控制电路500响应于第一发光控制信号EM1而导通，将第一电源电压VDD施加至驱动电路100的第一端110，从而驱动电路100可以在其控制端和第一端的电压的共同作用下产生驱动电流；而在非发光阶段，第一发光控制电路500响应于第一发光控制信号EM1而截止，从而驱动电路100不产生驱动电流，可以避免发光元件700发光，从而可以提高相 应的显示装置的对比度。
例如，在本公开的至少一些实施例中，在图4A所示的电路结构的基础上，如图5A所示，像素电路10还可以包括第三复位电路430。例如，在一些实施例中，第三复位电路430可以是N型薄膜晶体管，例如N型氧化物薄膜晶体管，其被配置为在第三复位控制信号RST3的控制下将保持电压Vhold施加至驱动电路100的第一端110，以减弱驱动电路100的特性漂移。例如，在一些实施例中，第三复位控制信号RST3和第一复位控制信号RST1至少部分时间段内同时为开启信号。
例如，在本公开的至少一些实施例中，如图5D所示，第三复位控制信号RST3与第一复位控制信号RST1可以为同一控制信号，即可以使用相同的时序，以实现减弱驱动电路100磁滞的效果。
需要说明的是，在本公开的实施例中，第一复位控制信号RST1、第二复位控制信号RST2和第三复位控制信号RST3是为了区别三个时序不同的控制信号(例如，复位控制信号)。例如，在一些实施例中，当显示面板中的多个像素单元的像素电路10呈阵列排布时，第二复位控制信号RST2和第三复位控制信号RST3可以互为上下级关系。例如，对于一行像素单元而言，用于控制本行像素单元的像素电路10中的第二复位电路420的第二复位控制信号RST2还可以用于控制上一行像素单元的像素电路10中的第三复位电路430，即作为上一行像素单元的像素电路10中的第三复位控制信号RST3；同样地，用于控制本行像素单元的像素电路10中的第三复位电路430的第三复位控制信号RST3还可以用于控制下一行像素单元的像素电路10中的第二复位电路420，即作为下一行像素单元的像素电路10中的第二复位控制信号RST2。这样就能使得第二复位控制信号RST2和第三复位控制信号RST3可以由同一个GOA(Gate driver On Array)提供，以利于显示屏布线简化、提高分辨率、实现窄边框等。
例如，在本公开的至少一些实施例中，在图3A所示的电路结构的基础上，如图6A所示，像素电路10还可以包括第二发光控制电路600。例如，在一些实施例中，第二发光控制电路600可以是N型薄膜晶体管，例如N型氧化物薄膜晶体管。例如，在一些实施例中，第二发光控制电路600被配置为在第二发光控制信号EM2的控制下将驱动电流施加至发光元件700的第一极，以使光元件700发光。例如，在发光阶段，第二发光控制电路600响应于第二发光控制信号EM2而导通，从而驱动电路100可以通过第二发光控制电路600将驱动电流施加至发光元件700以使其发光；而在非发光阶段，第二发光控制电路600响应于第二发光控制信号EM2而截止，避免发光元件700发光，从而可以提高相应的显示装置的对比度。
例如，在本公开的至少一些实施例中，在图2A所示的电路结构的基础上，如图7A所示，像素电路10还可以包括电压传输电路800。例如，在一些实施例中，电压传输电路800可以是N型薄膜晶体管，例如N型氧化物薄膜晶体管，其被配置为在电压传输控制信号Vtc的控制下，在第一时间段内，将第二电源电压例如可以为VSS传输至驱动电路100的第一 端110，以及在第二时间段内，例如t2以后，将不同于第二电源电压的第一电源电压例如VDD传输至驱动电路100的第一端110。
例如，在本公开的至少一些实施例中，在图3A所示的电路结构的基础上，如图8A所示，像素电路10还可以在不包括第一复位电路410的同时，包括第二复位电路420。例如，在一些实施例中，数据信号端在第一时间段内，例如t1、t2和t3，将参考电压Vref，例如可以为第一初始化电压Vinit1，传输至数据写入电路200的第一端以完成对驱动电路100的控制端130的初始化操作，以及数据信号端在第二时间段内，例如t3、t4和t5，将数据信号Vdata传输至数据写入电路200的第一端，以将数据信号Vdata写入并存储于存储电路300中，以在发光阶段时使驱动电路100根据该数据信号Vdata产生驱动发光元件700发光的驱动电流。
图2B为图2A中所示的像素电路的一种具体示例的电路结构示意图。如图2B所示，该像素电路10包括：第一至第三晶体管T1、T2、T3以及存储电容C1和发光元件LE。例如，第一晶体管T1被用作驱动晶体管，其他的第二晶体管T2、第三晶体管T3被用作开关晶体管。例如，发光元件LE可以采用OLED，本公开的实施例包括但不限于此，以下实施例均以OLED为例进行说明，不再赘述。
该OLED可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。另外，还需要说明的是，以下实施例还以各晶体管为N型晶体管为例进行说明，但这并不构成对本公开的实施例的限制。
例如，上述第一至第三晶体管T1、T2、T3可以均采用N型薄膜晶体管，其中第一至第三晶体管T1、T2、T3均可以是N型氧化物薄膜晶体管。当采用N型氧化物薄膜晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
例如，如图2B所示，驱动电路100可以实现为第一晶体管T1，其中第一晶体管T1可以是N型薄膜晶体管，例如N型氧化物薄膜晶体管。第一晶体管T1的栅极作为驱动电路100的控制端130与第一节点N1连接，第一晶体管T1的第一极作为驱动电路100的第一端110通过第三节点N3和第一电源端VDD连接以接收第一电源电压VDD，第一晶体管T1的第二极作为驱动电路100的第二端120与第二节点N2连接。例如，第一电源电压VDD可以是驱动电压，例如高电压(相对与发光元件相连的第二电源电压VSS而言，下面将详细说明)。
例如，如图2B所示，数据写入电路200可以实现为第二晶体管T2，其中，第二晶体管T2可以是N型薄膜晶体管，例如N型氧化物薄膜晶体管。第二晶体管T2的栅极和栅极扫描信号端连接以接收栅极扫描信号GN。第二晶体管T2的第一极和数据信号端连接以接收数据信号Vdata，第二晶体管T2的第二极与第一节点N1(驱动电路100的控制端130)连接。
例如，如图2B所示，存储电路300可以实现为存储电容C1，存储电容C1的第一端与第一节点N1(驱动电路100的控制端130)连接，存储电容C1的第二端与第二节点N2(驱动电路100的第二端120)连接。
例如，如图2B所示，第一复位电路410可以实现为第三晶体管T3，其中，第三晶体管T3为N型氧化物薄膜晶体管。第三晶体管T3的栅极和第一复位控制信号端连接以接收第一复位控制信号RST1，第三晶体管T3的第一极和第一初始化电压端连接以接收第一初始化电压Vinit1，第三晶体管T3的第二极和第一节点N1(驱动电路100的控制端130)连接。
图3B为图3A中所示的像素电路的一种具体示例的电路结构示意图。如图3B所示，该像素电路10包括：第一至第四晶体管T1、T2、T3、T4以及存储电容C1和发光元件LE。图3B所示的像素电路10相比图2B所示的像素电路10的区别在于：图3B所示的像素电路10还包括用于实现第二复位电路420的第四晶体管T4。图3B所示的像素电路10的其余部分与图2B所示的像素电路10相同，此处不再赘述。
例如，上述第一至第四晶体管T1、T2、T3、T4可以均采用N型薄膜晶体管，其中第一至第四晶体管T1、T2、T3、T4均可以是N型氧化物薄膜晶体管。当采用N型氧化物薄膜晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
例如，如图3B所示，第二复位电路420可以实现为第四晶体管T4，其中，第四晶体管T4可以为N型薄膜晶体管，例如N型氧化物薄膜晶体管。第四晶体管T4的栅极和第二复位控制信号端连接以接收第二复位控制信号RST2，第四晶体管T4的第一极和第二初始化电压端连接以接收第二初始化电压Vinit2，第四晶体管T4的第二极和第二节点N2(驱动电路100的第二端120)连接。
图4B为图4A中所示的像素电路的一种具体示例的电路结构示意图。如图4B所示，该像素电路10包括：第一至第五晶体管T1、T2、T3、T4、T5以及存储电容C1和发光元件LE。图4B所示的像素电路10相比图3B所示的像素电路10的区别在于：图4B所示的像素电路10还包括用于实现第一发光控制电路500的第五晶体管T5。图4B所示的像素电路10的其余部分与图3B所示的像素电路10相同，此处不再赘述。
例如，上述第一至第五晶体管T1、T2、T3、T4、T5可以均采用N型薄膜晶体管，其中第一至第五晶体管T1、T2、T3、T4、T5均可以是N型氧化物薄膜晶体管。当采用N型氧化物薄膜晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
例如，如图4B所示，第一发光控制电路500可以实现为第五晶体管T5，其中，第五 晶体管T5可以是N型薄膜晶体管，例如N型氧化物薄膜晶体管，第五晶体管T5的栅极和第一发光控制端连接以接收第一发光控制信号EM1，第五晶体管T5的第一极和第一电源端连接以接收第一电源电压VDD，第五晶体管的第二极和第三节点N3(驱动电路100的第一端110)连接。
图5B为图5A中所示的像素电路的一种具体示例的电路结构示意图。如图5B所示，该像素电路10包括：第一至第六晶体管T1、T2、T3、T4、T5、T6以及存储电容C1和发光元件LE。图5B所示的像素电路10相比图4B所示的像素电路10的区别在于：图5B所示的像素电路10还包括用于实现第三复位电路430的第六晶体管T6。图5B所示的像素电路10的其余部分与图4B所示的像素电路10相同，此处不再赘述。
例如，上述第一至第六晶体管T1、T2、T3、T4、T5、T6可以均采用N型薄膜晶体管，其中述第一至第六晶体管T1、T2、T3、T4、T5、T6均可以是N型氧化物薄膜晶体管。当采用N型氧化物薄膜晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
例如，如图5B所示，第三复位电路430可以实现为第六晶体管T6，其中，第六晶体管T6可以是N型薄膜晶体管，例如N型氧化物薄膜晶体管。第六晶体管T6的栅极和第三复位控制信号端连接以接收第三复位控制信号RST3，第六晶体管T6的第一极和保持电压端连接以接收保持电压Vhold，第六晶体管T6的第二极和第三节点N3(驱动电路100的第一端110)连接。
图6B为图6A中所示的像素电路的一种具体示例的电路结构示意图。如图6B所示，该像素电路10包括：晶体管T1、T2、T3、T4、T7以及存储电容C1和发光元件LE。图6B所示的像素电路10相比图3B所示的像素电路10的区别在于：图6B所示的像素电路10还包括用于实现第二发光控制电路600的第七晶体管T7。图6B所示的像素电路10的其余部分与图3B所示的像素电路10相同，此处不再赘述。
例如，上述晶体管T1、T2、T3、T4、T7可以均采用N型薄膜晶体管，其中晶体管T1、T2、T3、T4、T7均可以是N型氧化物薄膜晶体管。当采用N型氧化物薄膜晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
例如，如图6B所示，第二发光控制电路600可以实现为第七晶体管T7，其中，第七晶体管T7为N型薄膜晶体管，例如N型氧化物薄膜晶体管。第七晶体管T7的栅极与第二发光控制端连接以接收第二发光控制信号EM2，第七晶体管T7的第一极与第二节点N2(驱动电路100的第二端120)连接，第七晶体管T7的第二极与发光元件EL的第一极连接。
图7B为图7A中所示的像素电路的一种具体示例的电路结构示意图。如图7B所示， 该像素电路10包括：晶体管T1、T2、T3、T8以及存储电容C1和发光元件LE。图7B所示的像素电路10相比图2B所示的像素电路10的区别在于：图7B所示的像素电路10还包括用于实现电压传输电路800的第八晶体管T8。图7B所示的像素电路10的其余部分与图2B所示的像素电路10相同，此处不再赘述。
例如，上述晶体管T1、T2、T3、T4、T7可以均采用N型薄膜晶体管，其中晶体管T1、T2、T3、T4、T7均可以是N型氧化物薄膜晶体管。当采用N型氧化物薄膜晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
例如，如图7B所示，第二发光控制电路600可以实现为第八晶体管T8其中，第八晶体管T8为N型薄膜晶体管，例如N型氧化物薄膜晶体管。第八晶体管T8的栅极和电压传输控制信号端连接以接收电压传输控制信号Vtc，第八晶体管T8的第一极与第一电源端连接，第八晶体管T8的第二极和第三节点N3(驱动电路100的第一端110)连接。第一电源端被配置为在第一时间段内，将第二电源电压例如可以为VSS传输至驱动电路100的第一端110，以及在第二时间段内，将不同于第二电源电压的第一电源电压例如VDD传输至驱动电路100的第一端110。
图8B为图8A中所示的像素电路的一种具体示例的电路结构示意图。如图8B所示，该像素电路10包括：晶体管T1、T2、T4、T5以及存储电容C1和发光元件LE。图8B所示的像素电路10相比图3B所示的像素电路10的区别在于：图8B所示的像素电路10不包括用于实现第一复位电路410的第三晶体管T3。图8B所示的像素电路10的其余部分与图3B所示的像素电路10相同，此处不再赘述。
例如，上述晶体管T1、T2、T4、T5可以均采用N型薄膜晶体管，例如N型氧化物薄膜晶体管。
例如，如图8A和8B所示，在一些实施例中，数据信号端在第一时间段内，将参考电压Vref，例如可以是第一初始化电压Vinit1，传输至第二晶体管T2的第一端并在第二晶体管T2响应于栅极扫描信号GN而导通后将第一初始化电压Vinit1传输至驱动电路100的控制端130以完成对驱动电路100的控制端130的初始化操作，以及，数据信号端在第二时间段内，将数据信号Vdata传输至数据写入电路200的第一端，在第二晶体管T2响应于栅极扫描信号GN而导通后将数据信号Vdata写入驱动电路100的控制端130并存储于存储电路300中，以在发光阶段时使驱动电路100根据该数据信号Vdata的强度产生相应的驱动电流，以驱动发光元件700发光。
需要说明的是，在本公开的实施例中，存储电容C1可以至少部分是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，并且，电容也可以至少部分是各个器件之间 的寄生电容，可以通过晶体管本身与其他器件、线路来实现。电容的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式，只要能存储相应节点的电压即可。
需要说明的是，在本公开的实施例的说明中，第一节点N1、第二节点N2和第三节点N3并非表示必须实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。当采用N型氧化物薄膜晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
需要说明的是，在本公开的实施例中，均是以发光元件LE的阴极(例如多个发光元件的公共阴极)接入第二电源电压VSS(低电压)为例进行说明的，本公开的实施例包括但不限于此。例如，还可以使发光元件LE的阳极接入第一电源电压VDD(高电压)，而其阴极则直接或间接地连接到驱动电路，例如可以参考图1B所示的2T1C像素电路。
需要说明的是，在本公开的实施例提供的像素电路中，“有效电压”指的是能够使得其包括的被操作晶体管被导通的电压，相应地“无效电压”指的是不能使得其包括的被操作晶体管被导通(即，该晶体管被截止)的电压。根据移位寄存器单元的电路结构中的晶体管的类型(例如N型)等因素，有效电压可以比无效电压高或者低。例如，在本公开实施例中，当各个晶体管均为N型晶体管时，有效电压为高电压，无效电压为低电压。
本公开至少一些实施例还提供一种像素电路的驱动方法。图2C为本公开至少一些实施例提供的一种像素电路的驱动方法的信号时序图。下面结合图2C所示的信号时序图，以图2A所示的像素电路具体实现为图2B所示的像素电路结构为例，对图2A所示的像素电路的工作原理进行说明。需要说明的是，图2C中所示的信号时序图的电压的高低仅是示意性的，不代表真实电压值或相对比例，对应于本公开的实施例，高电压信号对应于N型晶体管的导通信号，而低电压信号对应于N型晶体管的截止信号。
例如，如图2C所示，本实施例提供的驱动方法可以包括三个阶段，分别为初始化阶段p1、数据写入阶段p2以及发光阶段p3，图2C中示出了每个阶段中各个信号的时序波形。
在初始化阶段p1，输入第一复位控制信号RST1，开启(即导通)第一复位电路410，通过第一复位电路410对驱动电路100的控制端130进行复位。例如，在初始化阶段p1初始化阶段，第三晶体管T3被第一复位控制信号RST1的高电压导通，使得第一节点N1初始化，且初始化电压为Vinit1。例如，Vinit1为低电压(例如可以接地或为其他低电压)， 第一晶体管T1的栅极(也即第一节点N1)的电压变为Vinit1，因而第一晶体管T1处于截止状态，从而使发光器件EL处于不发光状态，例如，第三晶体管T3可以使用氧化物薄膜晶体管，降低低频漏电，使得第一节点N1保持低电压，从而使得第一晶体管T1长时间处于截止状态，进而使得发光器件EL长时间处于不发光状态，消除了闪烁。同时，第二晶体管T2被栅极扫描信号GN的低电压截止，阻止了数据信号Vdata的输入。
在数据写入阶段p2，输入栅极扫描信号GN，开启数据写入电路200，通过数据写入电路200将数据信号Vdata写入驱动电路100的控制端130，并通过存储电路300存储写入的数据信号Vdata。例如，在数据写入阶段，第一复位控制信号RST1变为低电压，从而使得第三晶体管T3截止，而栅极扫描信号GN变为高电压使得第二晶体管T2导通，此时，第一节点N1的电压由第一初始化电压Vinit1变为更高的电压，即数据电压Vdata(数据信号Vdata的电压)，从而使得第一晶体管T1导通。同时，由于第一节点N1的电压变为数据电压Vdata，存储电容C1可以存储该数据电压Vdata，从而完成了数据写入。
需要说明的是，在数据写入阶段p2，由于第一晶体管T1导通，漏电流Ids从第三节点N3流向第二节点N2，第二节点N2的电压逐渐升高。
在发光阶段p3，停止输入栅极扫描信号GN，关闭数据写入电路200，驱动电路100在存储电路300存储的数据信号Vdata的控制下产生驱动电流，使发光元件700发光。例如，在发光阶段p3，第一复位控制信号RST1变为低电压，从而使得第三晶体管T3截止，同时，第二晶体管T2被栅极扫描信号GN的低电压截止，阻止了数据电压Vdata的输入。此时，第一晶体管T1在存储电容C1存储的数据信号Vdata的控制下保持导通状态，第二节点N2的电压升高超过发光器件EL的启亮电压，发光器件EL开始发光，因为是恒流驱动，因此最后第二节点N2的电压会到达发光器件的启亮电压，同时由于第一节点N1与第二节点N2通过第一电容C1相连，因此第一节点N1的电压也同样跟随第二节点N2的电压升高到稳定状态，即使N1、N2两节点电压发生变化，N1、N2两节点电压压差即第一晶体管T1栅极和其源极电压差Vgs可以保持不变，因此发光电流I恒定，如下面的公式所述：
I＝kμ(Vdata-ΔV) 2
其中，I是发光电流，k是常数系数，μ是第一晶体管T1的迁移率，Vdata是数据信号电压，ΔV是第二节点N2的电压的逐渐升高值。
本公开至少一些实施例还提供一种像素电路的驱动方法。图3C为本公开至少一些实施例提供的一种像素电路的驱动方法的信号时序图。下面结合图3C所示的信号时序图，以图3A所示的像素电路具体实现为图3B所示的像素电路结构为例，对图3A所示的像素电路的工作原理进行说明。
例如，如图3C所示，本实施例提供的驱动方法可以包括四个阶段，分别为初始化阶段t11、阈值电压补偿阶段t22、数据写入与迁移率补偿阶段t33以及发光阶段t44，图3C中示出了每个阶段中各个信号的时序波形。
在初始化阶段t11，输入第一复位控制信号RST1和第二复位控制信号RST2，开启(即 导通)第一复位电路410和第二复位电路420，通过第一复位电路410对驱动电路100的控制端130进行复位，通过第二复位电路420对驱动电路100的第二端120进行复位。例如，在初始化阶段t11，第三晶体管T3被第一复位控制信号RST1的高电压导通，使得第一节点N1初始化，且初始化电压为Vinit1。由于Vinit1为高电压(例如可以是第一电源电压，例如VDD或其他高电压)，第一晶体管T1的栅极(也即第一节点N1)的电压变为Vinit1。例如，在初始化阶段t11，第四晶体管T4被第二复位控制信号RST2的高电压导通，使得第二节点N2初始化，且初始化电压为Vinit2。例如，Vinit2可以是低电压(例如可以接地或为其他低电压)，例如，Vinit2的电压可以小于第二电源电压(例如VSS)，使第一晶体管T1的栅极和其源极的电压差Vgs足够大(例如大于7V)，从而可以快速消除磁滞状态。同时，因为Vinit2可以是低电压，所以在第四晶体管T4导通后与第四晶体管T4的第二极相连的第二节点N2也为低电压，从而使发光器件EL处于不发光状态。例如，第三晶体管T3可以使用氧化物薄膜晶体管，降低低频漏电，使得第一节点N1保持低电压，从而使得第一晶体管T1长时间处于截止状态，进而使得发光器件EL长时间处于不发光状态，消除了闪烁。同时，第二晶体管T2被栅极扫描信号GN的低电压截止，阻止了数据信号Vdata的输入。
在阈值电压补偿阶段t22，输入第一复位控制信号RST1，开启第一复位电路410，通过第一复位电路410将第一初始化电压Vinit1施加至驱动电路100的控制端130，以导通驱动电路100；同时，停止输入第二复位控制信号，关闭第二复位电路420；从而，可以通过导通的驱动电路100和存储电路300进行阈值补偿。例如，第一复位控制信号RST1可以保持高电压，从而使得第三晶体管T3保持导通状态；第二复位控制信号RST2可以是低电压，从而使得第四晶体管T4截止。第二晶体管T2持续被栅极扫描信号GN的低电压截止，从而持续阻止了数据信号Vdata的输入。同时，第一节点N1的电压(即第一初始化电压Vinit1)为高电压，第一晶体管T1导通。由于第三节点N3的电压VDD为高电压，从而使第二节点N2的电压由初始的VSS逐渐升高，直至第一晶体管T1的栅极和其源极(例如第二极)的电压差Vgs等于其自身的阈值电压Vth，此时第二节点N2的电压V N2为第一初始化电压Vinit1与第一晶体管T1的阈值电压Vth的差值，同时，第一晶体管T1的阈值电压Vth写入了存储电容C1的两端，从而完成了阈值电压补偿，如下面的公式所述：
V N2＝Vinit1-Vth
其中，V N2是第二节点N2的电压，Vinit1是第二节点N2的电压V N2为第一初始化电压，Vth是第一晶体管T1的阈值电压。
在数据写入与迁移率补偿阶段t33，输入栅极扫描信号GN，开启数据写入电路200，通过数据写入电路200将数据信号Vdata写入驱动电路100的控制端130，并通过存储电路300存储写入的数据信号Vdata。例如，第一复位控制信号RST1变为低电压，从而使得第三晶体管T3截止；第二复位控制信号RST2可以是低电压，从而使得第四晶体管T4截止，而栅极扫描信号GN变为高电压使得第二晶体管T2导通，此时，第一节点N1的电压由第 一初始化电压Vinit1变为数据电压Vdata(数据信号Vdata的电压)，从而使得第一晶体管T1导通。同时，由于第一节点N1的电压变为数据电压Vdata，存储电容C1可以存储该数据电压Vdata，从而完成了数据写入。由于第二节点N2连接的发光器件EL可以看做是一个电容，且其电容值远大于第一电容器C1，因此第二节点N2点的电压几乎不变，且保持为上一阶段t22的第一初始化电压Vinit1与第一晶体管T1的阈值电压Vth的差值。由于第一晶体管T1导通，其驱动电流Ids从第三节点N3流向第二节点N2，第二节点N2的电压逐渐升高了ΔV，此时N2电压V N2为第一初始化电压Vinit1与第一晶体管T1的阈值电压Vth的差值与逐渐升高的电压ΔV的和，如下面的公式所述：
V N2＝Vinit1-Vth+ΔV
其中，V N2是第二节点N2的电压，Vinit1是第二节点N2的电压V N2为第一初始化电压，Vth是第一晶体管T1的阈值电压，ΔV是第二节点N2的电压的逐渐升高值。
第一节点N1的电压由于第二晶体管T2的导通仍然为数据电压Vdata。因为第一晶体管T1的驱动电流如下面的公式所述：
Ids＝kμ(Vgs-Vth) 2
其中，Ids是第一晶体管T1的驱动电流，k是常数系数，μ是第一晶体管T1的迁移率，Vgs是第一晶体管T1的栅极和其源极的电压差，Vth是第一晶体管T1的阈值电压。由上述公式可以看出，第一晶体管T1的驱动电流第一晶体管T1的迁移率μ越大，其驱动电流越大，第二节点N2的电压逐渐升高的电压ΔV也就越大，因此第一晶体管T1栅极和其源极电压差Vgs就越小，所以(Vgs-Vth) 2越小，又因为第一晶体管T1的迁移率μ越大，所以第一晶体管T1的驱动电流Ids得到校正。例如，不同迁移率的驱动晶体管在相同数据电压Vdata下的驱动电流差异不大。
在发光阶段t44，停止输入栅极扫描信号GN，关闭数据写入电路200，驱动电路100在存储电路300存储的数据信号Vdata的控制下产生驱动电流，使发光元件700发光。例如，第一复位控制信号RST1变为低电压，从而使得第三晶体管T3截止；第二复位控制信号RST2可以是低电压，从而使得第四晶体管T4截止。同时，第二晶体管T2被栅极扫描信号GN的低电压截止，阻止了数据电压Vdata的输入。此时，第二节点N2的电压升高超过发光器件EL的启亮电压，发光器件EL开始发光，因为是恒流驱动，因此最后第二节点N2的电压会到达发光器件的启亮电压，同时由于第一节点N1与第二节点N2通过第一电容C1相连，因此第一节点N1的电压也同样跟随第二节点N2的电压升高到稳定状态，即使N1、N2两节点电压发生变化，N1、N2两节点的电压差即第一晶体管T1栅极和其源极电压差Vgs可以保持不变，因此发光电流I恒定，如下面的公式所述：
I＝kμ(Vdata-ΔV) 2
其中，I是发光电流，k是常数系数，μ是第一晶体管T1的迁移率，Vdata是数据信号电压，ΔV是第二节点N2的电压的逐渐升高值。因而，该像素电路兼具阈值电压补偿、迁移率μ补偿和电压降(IR Drop)补偿的技术效果。
例如，为了简化电路，上述第二复位控制信号RST2与栅极扫描信号GN可以共用一组GOA电路，以利于显示屏布线简化、提高分辨率、实现窄边框等。
本公开至少一些实施例还提供一种像素电路的驱动方法。图6C为本公开至少一些实施例提供的一种像素电路的驱动方法的信号时序图。图6C公开的像素电路的驱动方法几乎与上述图3C公开的像素电路驱动方法相同。下面结合图6C所示的信号时序图，以图6A所示的像素电路具体实现为图6B所示的像素电路结构为例，对图6A所示的像素电路的工作原理进行说明。
例如，如图6C所示，本实施例提供的驱动方法可以包括四个阶段，分别为初始化阶段t11、阈值电压补偿阶段t22、数据写入与迁移率补偿阶段t33以及发光阶段t44，图6C中示出了每个阶段中各个信号的时序波形。
例如，与图6C所示的像素电路驱动方法的信号时序图相对应的图6B所示的像素电路10相比于与图3C所示的像素电路驱动方法的信号时序图相对应的图3B所示的像素电路10，区别在于，图6B所示的像素电路10增加了用于实施第二发光控制电路600的第七晶体管T7。例如，发光器件EL通过第七晶体管T7连接到第二节点N2，这样可以使第一晶体管T1的漏极(例如第一极)始终处于第一电源电压，例如可以是VDD。又因为第一晶体管T1的栅极与其漏极之间的电压差Vgd始终小于第一晶体管T1的阈值电压Vth，所以第一晶体管T1仅处于关态和饱和态两种状态，从而有利于稳定第一晶体管T1的特性。
例如，第二初始化电压Vinit2的电压可以小于第二电源电压(例如VSS)，使第一晶体管T1的栅极和其源极的电压差Vgs足够大(例如大于7V)，从而可以快速消除磁滞状态，但是发光器件EL因第二节点N2的电压是第二初始化电压Vinit2，所以发光器件EL处于反置状态。当反置电压足够大时，发光器件EL存在反置驱动电流，长期对发光器件EL不利，因此，第七晶体管T7的存在避免了反置驱动电流的产生，同时还可以让第二初始化电压Vinit2足够低(例如低于第二电源电压)从而使磁滞尽快消除。
在初始化阶段t11，如图6C所示，本实施例提供的驱动方法相比图3C所示的驱动方法的区别在于第二发光控制信号EM2为低电压，第七晶体管T7截止。
在阈值电压补偿阶段t22，如图6C所示，本实施例提供的驱动方法相比图3C所示的驱动方法的区别在于第二发光控制信号EM2为低电压，第七晶体管T7截止。
例如，在数据写入与迁移率补偿阶段t33，如图6C所示，本实施例提供的驱动方法相比图3C所示的驱动方法的区别在于第二发光控制信号EM2为高电压，第七晶体管T7导通。
例如，在发光阶段t44，如图6C所示，本实施例提供的驱动方法相比图3C所示的驱动方法的区别在于第二发光控制信号EM2为高电压，第七晶体管T7导通。
例如，根据图6C，为了简化电路，第二复位控制信号RST2与栅极扫描信号GN可以共用一组GOA电路，第二复位控制信号RST2与第二发光控制信号EM2也可以共用一组GOA，例如，可以增加一个反相器用于生成一对第二复位控制信号RST2与第二发光控制 信号EM2。因此，图6C所示的时序图对应的图6B所示的像素电路只需要两组GOA电路即可工作，以利于显示屏布线简化、提高分辨率、实现窄边框等。
本公开至少一些实施例还提供一种像素电路的驱动方法。图4C为本公开至少一些实施例提供的一种像素电路的驱动方法的信号时序图。下面结合图4C所示的信号时序图，以图4A所示的像素电路具体实现为图4B所示的像素电路结构为例，对图4A所示的像素电路的工作原理进行说明。
例如，如图4C所示，本实施例提供的驱动方法可以包括五个阶段，分别为初始化阶段t1、阈值电压补偿阶段t2、数据写入阶段t3、迁移率补偿阶段t4以及发光阶段t5，图4C中示出了每个阶段中各个信号的时序波形。
在初始化阶段t1，输入第一复位控制信号RST1和第二复位控制信号RST2，开启(即导通)第一复位电路410和第二复位电路420，通过第二复位电路420对驱动电路100的第二端120进行复位。例如，在初始化阶段t11，第三晶体管T3被第一复位控制信号RST1的高电压导通，使得第一节点N1(驱动电路100的控制端130)初始化，且初始化电压为Vinit1。由于Vinit1为高电压(例如可以是第一电源电压，例如VDD或其他高电压)，第一晶体管T1的栅极(也即第一节点N1)的电压变为Vinit1。例如，在初始化阶段t11，第四晶体管T4被第二复位控制信号RST2的高电压导通，使得第二节点N2(驱动电路100的第二端120)初始化，且初始化电压为Vinit2。例如，Vinit2可以是低电压(例如可以接地或为其他低电压)，例如，Vinit2的电压可以小于第二电源电压(例如VSS)，使第一晶体管T1的栅极和其源极的电压差Vgs足够大(例如大于7V)，从而可以快速消除磁滞状态，而第一晶体管T1的栅极与其漏极之间的电压差Vgd等于Vinit1与VDD的差且小于Vth，所以第一晶体管T1仅处于关态和饱和态两种状态，从而有利于稳定第一晶体管T1的特性。同时，第五晶体管T5被第一发光控制信号EM1的低电压截止，阻止了第一电源电压的输入，因为Vinit2可以是低电压，所以在第四晶体管T4导通后与第四晶体管T4的第二极相连的第二节点N2也为低电压，从而使发光器件EL处于不发光状态。例如，第三晶体管T3可以使用氧化物薄膜晶体管，降低低频漏电，使得第一节点N1保持低电压，从而使得第一晶体管T1长时间处于截止状态，进而使得发光器件EL长时间处于不发光状态，消除了闪烁。同时，第二晶体管T2被栅极扫描信号GN的低电压截止，阻止了数据信号Vdata的输入。
在阈值电压补偿阶段t2，输入第一复位控制信号RST1，开启第一复位电路410，通过第一复位电路410将第一初始化电压Vinit1施加至驱动电路100的控制端130，以导通驱动电路100，输入第一发光控制信号，开启第一发光控制电路500，同时，停止输入第二复位控制信号，关闭第二复位电路420，从而，可以通过导通的驱动电路100和存储电路300对驱动电路100进行阈值补偿。例如，第一复位控制信号RST1保持为高电压，从而使得第三晶体管T3保持导通，从而使得第一节点N1的电压保持为为第一初始化电压Vinit1，例如可以是高电压。第二复位控制信号RST2为低电压，使得第四晶体管T4截止。此时，第一 节点N1的电压第一初始化电压Vinit1为高电压，例如高于VDD，第三节点N3的电压为高电压，例如为VDD。第一发光控制信号EM1可以为高电压，从而使得第五晶体管T5导通，第二节点N2的电压由初始的第二初始化电压Vinit2逐渐升高，直至第一晶体管T1的栅极和其源极的电压差Vgs等于第一晶体管T1的阈值电压Vth，此时第二节点N2的电压为第一初始化电压Vinit1与第一晶体管T1的阈值电压Vth的差，从而，第一晶体管T1的阈值电压Vth写到了第一电容器C1的两端。由于第二节点N2连接的发光器件EL可以看做是一个电容，且其电容值远大于第一电容器C1，因此第二节点N2点的电压几乎不变，且保持为上一阶段t2的第一初始化电压Vinit1与第一晶体管T1的阈值电压Vth的差值，因而补偿了第一晶体管T1的阈值电压Vth，以完成阈值电压的补偿。同时，第二晶体管T2被栅极扫描信号GN的低电压截止，阻止了数据信号Vdata的输入。
在数据写入阶段t3，输入栅极扫描信号GN，开启数据写入电路200，通过数据写入电路200将数据信号Vdata写入驱动电路100的控制端130，并通过存储电路300存储写入的数据信号Vdata。例如，在数据写入阶段t3，第一发光控制信号EM1可以为低电压，从而使得第五晶体管T5截止。第一复位控制信号RST1为低电压，使得第三晶体管T3截止。第二复位控制信号RST2为低电压，使得第四晶体管T4截止。同时，第二晶体管T2被栅极扫描信号GN的高电压导通。此时，第一节点N1的电压由第一初始化电压Vinit1变为更高电压，例如可以是Vdata，即数据电压Vdata(数据信号Vdata的电压)，从而使得第一晶体管T1导通。同时，由于第一节点N1的电压变为数据电压Vdata，存储电容C1可以存储该数据电压Vdata，从而完成了数据写入。
在迁移率补偿阶段t4，停止输入第一复位控制信号RST1，关闭第一复位电路410，停止输入第二复位控制信号，关闭第二复位电路420，输入栅极扫描信号GN，开启数据写入电路200，输入第一发光控制信号，开启第一发光控制电路500，从而，可以通过导通的第一发光控制电路500和导通的数据写入电路200进行迁移率补偿。例如，在迁移率补偿阶段t4，第一发光控制信号EM1可以为高电压，从而使得第五晶体管T5导通。第二复位控制信号RST2为低电压，使得第四晶体管T4截止。第一复位控制信号RST1为低电压，使得第三晶体管T3截止。栅极扫描信号GN保持为高电压，从而使得第二晶体管T2保持导通。此时，第一晶体管T1导通，漏流Ids从第一电源电压端，例如可以是VDD端流向第二节点N2，第二节点N2的电压逐渐升高ΔV，此时N2电压V N2为第一初始化电压Vinit1与第一晶体管T1的阈值电压Vth的差值与逐渐升高的电压ΔV的和，如下面的公式所述：
V N2＝Vinit1-Vth+ΔV
其中，V N2是第二节点N2的电压，Vinit1是第二节点N2的电压V N2为第一初始化电压，Vth是第一晶体管T1的阈值电压，ΔV是第二节点N2的电压的逐渐升高值。第一节点N1的电压由于第二晶体管T2的导通仍然为数据电压Vdata。因为第一晶体管T1的驱动电流如下面的公式所述：
Ids＝kμ(Vgs-Vth) 2
其中，Ids是第一晶体管T1的漏电流，k是常数系数，μ是第一晶体管T1的迁移率，Vgs是第一晶体管T1的栅极和其源极的电压差，Vth是第一晶体管T1的阈值电压。由上述公式可以看出，第一晶体管T1的驱动电流第一晶体管T1的迁移率μ越大，其驱动电流越大，第二节点N2的电压逐渐升高的电压ΔV也就越大，因此第一晶体管T1栅极和其源极电压差Vgs就越小，所以(Vgs-Vth) 2越小，又因为第一晶体管T1的迁移率μ越大，所以第一晶体管T1的漏电流Ids得到校正。例如，不同迁移率的驱动晶体管在相同数据电压Vdata下的驱动电流差异不大。
在发光阶段t5，停止输入第一复位控制信号RST1，关闭第一复位电路410，停止输入第二复位控制信号，关闭第二复位电路420，停止输入栅极扫描信号GN，关闭数据写入电路200，输入第一发光控制信号，开启第一发光控制电路500，从而，第一电源电压可以通过导通的第一发光控制电路500和导通的驱动电路100驱动发光元件发光。例如，在发光阶段t5，第一发光控制信号EM1可以为高电压，从而使得第五晶体管T5导通。第一复位控制信号RST1为低电压，使得第三晶体管T3截止。第二复位控制信号RST2为低电压，使得第四晶体管T4截止。栅极扫描信号GN为低电压，从而使得第二晶体管T2截止。此时，第二节点N2的电压升高超过发光器件EL的启亮电压，发光器件EL开始发光，因为是恒流驱动，因此最后第二节点N2的电压会到达发光器件的启亮电压，同时由于第一节点N1与第二节点N2通过第一电容C1相连，因此第一节点N1的电压也同样跟随第二节点N2的电压升高到稳定状态，即使N1、N2两节点的电压发生变化，N1、N2两节点的电压压差即第一晶体管T1栅极和其源极电压差Vgs可以保持不变，因此发光电流I恒定，如下面的公式所述：
I＝kμ(Vdata-ΔV) 2
其中，I是发光电流，k是常数系数，μ是第一晶体管T1的迁移率，Vdata是数据信号电压，ΔV是第二节点N2的电压的逐渐升高值。因而，该像素电路兼具阈值电压补偿、迁移率μ补偿和电压降(IR Drop)补偿的技术效果。
例如，上述像素电路可以将与第一节点N1连接的第三晶体管T3换为漏电更低的薄膜晶体管例如氧化物薄膜晶体管，可以降低低频漏电，从而使得第一节点N1的电压得到保持，使得发光器件EL发光时不闪烁。
本公开至少一些实施例还提供一种像素电路的驱动方法。图5C为本公开至少一些实施例提供的一种像素电路的驱动方法的信号时序图。图5C公开的像素电路的驱动方法几乎与上述图4C公开的像素电路驱动方法相同。下面结合图5C所示的信号时序图，以图5A所示的像素电路具体实现为图5B所示的像素电路结构为例，对图5A所示的像素电路的工作原理进行说明。
例如，如图5C所示，本实施例提供的驱动方法可以包括五个阶段，分别为初始化阶段t1、阈值电压补偿阶段t2、数据写入阶段t3、迁移率补偿阶段t4以及发光阶段t5，图5C中示出了每个阶段中各个信号的时序波形。
例如，与图5C所示的像素电路驱动方法的信号时序图相对应的图5B所示的像素电路10相比于与图4C所示的像素电路驱动方法的信号时序图相对应的图4B所示的像素电路10，区别在于，图5B所示的像素电路10增加了用于实施第三复位控制电路430的第六晶体管T6。例如，第六晶体管T6的栅极和第三复位控制信号端连接以接收第三复位控制信号RST3，第六晶体管T6的第一极和保持电压端连接以接收保持电压Vhold，第六晶体管T6的第二极和第三节点N3(驱动电路100的第一端110)连接。
例如，阈值电压补偿阶段t2，如图5C所示，本实施例提供的驱动方法相比图4C所示的驱动方法的区别在于第三复位控制信号RST3可以为高电压，使得第六晶体管T6管导通，第一发光控制信号EM1可以为低电压，从而使得第五晶体管T5截止，这样，在Vth补偿阶段，可以通过保持电压，例如可以是Vhold，给第二节点N2充电，直到第二节点N2的电压升到第一初始化电压Vinit2与第一晶体管T1的阈值电压Vth的差。同时，第三节点N3为保持电压例如可以是Vhold，例如可以高于VDD。此时，第一晶体管T1的栅极与其漏极之间的电压差Vgd等于Vinit1与Vhold的差且小于Vth(例如可以小于0V)，所以第一晶体管T1仅处于关态和饱和态两种状态，从而有利于稳定第一晶体管T1的特性。
例如，如图5D所示，第三复位控制信号RST3可以与第一复位控制信号RST1共用同一时序，以避免第三节点N3的电压在初始化阶段出现漂移的问题。图5D所示驱动方法与图5C所示的驱动方法完全相同，此处不再赘述。
例如，根据图5C所示的驱动方法，第二复位控制信号RST2和第三复位控制信号RST3可以互为上下级关系，即第二复位控制信号RST2和第三复位控制信号RST3由同一信号源发出，第二复位控制信号RST2和第三复位控制信号RST3属于上下的两个时刻对应的信号，这样就能使得第二复位控制信号RST2和第三复位控制信号RST3共用同一个GOA，以利于显示屏布线简化、提高分辨率、实现窄边框等。
同时，由于图5D所示驱动方法与图5C所示的驱动方法的t1、t3、t4和t5阶段与上述图4C所示的驱动方法完全相同，此处不再赘述。
本公开至少一些实施例还提供一种像素电路的驱动方法。图7C为本公开至少一些实施例提供的一种像素电路的驱动方法的信号时序图。下面结合图7C所示的信号时序图，以图7A所示的像素电路具体实现为图7B所示的像素电路结构为例，对图7A所示的像素电路的工作原理进行说明。
例如，如图7C所示，本实施例提供的驱动方法可以包括五个阶段，分别为初始化阶段t1、阈值电压补偿阶段t2、数据写入阶段t3、迁移率补偿阶段t4以及发光阶段t5，图7C中示出了每个阶段中各个信号的时序波形。
在初始化阶段t1，输入第一复位控制信号RST1，开启(即导通)第一复位电路410，输入电压传输控制信号，开启电压传输控制电路800，通过第一电源电压端输入第二电源电压，从而，对驱动电路100的第二端120进行复位。例如，在初始化阶段t1，电压传输控制信号Vtc为高电压，使得第八晶体管T8导通，同时将第二电源电压例如可以为VSS传输 至第三节点N3(第一晶体管T1的第一极)。第一复位控制信号RST1为高电压，使得第三晶体管T3导通，将第一节点N1的电压初始化为第一初始化电压Vinit1例如可以高电压，例如高于VDD。第二晶体管T2被栅极扫描信号GN的低电压截止，阻止了数据信号Vdata的输入。此时，第一节点N1的电压为第一初始化电压Vinit1，例如可以是为高电压，例如高于VDD。第三节点N3的电压为低电压，例如可以是第二电源电压VSS。例如，第一晶体管T1的栅极和其源极的电压差Vgs等于第一初始化电压Vinit1与第二电源电压VSS的差而且大于第一晶体管T1的阈值电压Vth，从而使得第一晶体管T1处于导通状态，第二节点N2的电压降低到低电压例如第二电源电压VSS，从而对第二节点N2的电压(驱动电路100的第二端120)进行了复位。
在阈值电压补偿阶段t2，输入第一复位控制信号RST1，开启(即导通)第一复位电路410，输入电压传输控制信号，开启电压传输控制电路800，通过第一电源电压端输入第一电源电压，从而，对驱动电路100进行阈值补偿。例如，在阈值电压补偿阶段t2，电压传输控制信号Vtc为高电压，使得第八晶体管T8导通，同时将第一电源电压例如可以为VDD传输至第三节点N3(第一晶体管T1的第一极)。第一复位控制信号RST1为高电压，使得第三晶体管T3导通，将第一节点N1的电压初始化为第一初始化电压Vinit1例如可以高电压，例如高于VDD。第二晶体管T2被栅极扫描信号GN的低电压截止，阻止了数据信号Vdata的输入。此时，第一节点N1的电压为第一初始化电压Vinit1，例如可以是为高电压，例如高于VDD。第三节点N3的电压为高电压，例如可以是第一电源电压VDD。第二节点N2的电压由初始的VSS逐渐升高，直至第一晶体管T1的栅极和其源极的电压差Vgs等于第一晶体管T1的阈值电压Vth，此时第二节点N2的电压为第一初始化电压Vinit1与第一晶体管T1的阈值电压Vth的差，从而，第一晶体管T1的阈值电压Vth写到了第一电容器C1的两端。由于第二节点N2连接的发光器件EL可以看做是一个电容，且其电容值远大于第一电容器C1，因此第二节点N2点的电压几乎不变，且保持为上一阶段t2的第一初始化电压Vinit1与第一晶体管T1的阈值电压Vth的差值，因而补偿了第一晶体管T1的阈值电压Vth，以完成阈值电压的补偿。
在数据写入阶段t3，输入栅极扫描信号GN，开启数据写入电路200，通过数据写入电路200将数据信号Vdata写入驱动电路100的控制端130，并通过存储电路300存储写入的数据信号Vdata。例如，在数据写入阶段t3，电压传输控制信号Vtc为低电压，使得第八晶体管T8截止。第一复位控制信号RST1为低电压，使得第三晶体管T3截止。栅极扫描信号GN为高电压，从而使得第二晶体管T2导通。此时，第一节点N1的电压由第一初始化电压Vinit1变为更高电压，例如可以是Vdata，即数据电压Vdata(数据信号Vdata的电压)，从而使得第一晶体管T1导通。同时，由于第一节点N1的电压变为数据电压Vdata，存储电容C1可以存储该数据电压Vdata，从而完成了数据写入。
在迁移率补偿阶段t4，停止输入第一复位控制信号RST1，关闭第一复位电路410，输入栅极扫描信号GN，开启数据写入电路200，输入电压传输控制信号，开启电压传输控制 电路800，通过第一电源电压端输入第一电源电压，从而，可以通过导通的电压传输控制电路800和数据写入电路200进行迁移率补偿。例如，在迁移率补偿阶段t4，电压传输控制信号Vtc为高电压，使得第八晶体管T8导通，同时将第一电源电压例如可以为VDD传输至第三节点N3(第一晶体管T1的第一极)。第一复位控制信号RST1为低电压，使得第三晶体管T3截止。栅极扫描信号GN保持为高电压，从而使得第二晶体管T2保持导通。此时，第一晶体管T1导通，驱动电流Ids从第一电源电压端，例如可以是VDD端流向第二节点N2，第二节点N2的电压逐渐升高ΔV，此时N2电压V N2为第一初始化电压Vinit1与第一晶体管T1的阈值电压Vth的差值与逐渐升高的电压ΔV的和，如下面的公式所述：
V N2＝Vinit1-Vth+ΔV
其中，V N2是第二节点N2的电压，Vinit1是第二节点N2的电压V N2为第一初始化电压，Vth是第一晶体管T1的阈值电压，ΔV是第二节点N2的电压的逐渐升高值。第一节点N1的电压由于第二晶体管T2的导通仍然为数据电压Vdata。因为第一晶体管T1的驱动电流如下面的公式所述：
Ids＝kμ(Vgs-Vth) 2
其中，Ids是第一晶体管T1的驱动电流，k是常数系数，μ是第一晶体管T1的迁移率，Vgs是第一晶体管T1的栅极和其源极的电压差，Vth是第一晶体管T1的阈值电压。由上述公式可以看出，第一晶体管T1的驱动电流第一晶体管T1的迁移率μ越大，其驱动电流越大，第二节点N2的电压逐渐升高的电压ΔV也就越大，因此第一晶体管T1栅极和其源极电压差Vgs就越小，所以(Vgs-Vth) 2越小，又因为第一晶体管T1的迁移率μ越大，所以第一晶体管T1的驱动电流Ids得到校正。例如，不同迁移率的驱动晶体管在相同数据电压Vdata下的驱动电流差异不大。
在发光阶段t5，停止输入第一复位控制信号RST1，关闭第一复位电路410，停止输入栅极扫描信号GN，关闭数据写入电路200，输入电压传输控制信号，开启电压传输控制电路800，从而，第一电源电压可以通过导通的电压传输控制电路800和导通的驱动电路100驱动发光元件发光。例如，在发光阶段t5，电压传输控制信号Vtc为高电压，使得第八晶体管T8导通，同时将第一电源电压例如可以为VDD传输至第三节点N3(第一晶体管T1的第一极)。第一复位控制信号RST1为低电压，使得第三晶体管T3截止。栅极扫描信号GN为低电压，从而使得第二晶体管T2截止。此时，第二节点N2的电压升高超过发光器件EL的启亮电压，发光器件EL开始发光，因为是恒流驱动，因此最后第二节点N2的电压会到达发光器件的启亮电压，同时由于第一节点N1与第二节点N2通过第一电容C1相连，因此第一节点N1的电压也同样跟随第二节点N2的电压升高到稳定状态，即使N1、N2两节点电压发生变化，N1、N2两节点电压压差即第一晶体管T1栅极和其源极电压差Vgs可以保持不变，因此发光电流I恒定，如下面的公式所述：
I＝kμ(Vdata-ΔV) 2
其中，I是发光电流，k是常数系数，μ是第一晶体管T1的迁移率，Vdata是数据信号 电压，ΔV是第二节点N2的电压的逐渐升高值。因而，该像素电路兼具阈值电压补偿、迁移率μ补偿和电压降(IR Drop)补偿的技术效果。
本公开至少一些实施例还提供一种像素电路的驱动方法。图8C为本公开至少一些实施例提供的一种像素电路的驱动方法的信号时序图。下面结合图8C所示的信号时序图，以图8A所示的像素电路具体实现为图8B所示的像素电路结构为例，对图8A所示的像素电路的工作原理进行说明。
例如，如图8C所示，本实施例提供的驱动方法可以包括五个阶段，分别为初始化阶段t1、阈值电压补偿阶段t2、数据写入阶段t3、迁移率补偿阶段t4以及发光阶段t5，图8C中示出了每个阶段中各个信号的时序波形。
在初始化阶段t1，输入第二复位控制信号RST2，开启(即导通)第二复位电路420，输入栅极扫描信号GN，开启数据写入电路200，通过数据写入电路200将参考电压Vref输入驱动电路100的控制端130，从而，对驱动电路100的第二端120进行复位。例如，在初始化阶段t1，第一发光控制信号EM1可以为低电压，从而使得第五晶体管T5截止。第二复位控制信号RST2为高电压，使得第四晶体管T4导通，从而使得第二节点N2完成初始化且第二节点N2的电压为第二初始化电压Vinit2，例如为低电压，从而使得第一晶体管T1导通。同时，发光器件EL的第一极，例如阳极点的电压也为第二初始化电压Vinit2，从而复位发光器件EL且使其不发光。栅极扫描信号GN可以为高电压，从而使得第二晶体管T2导通。同时，数据信号端将参考电压Vref，例如可以为第一初始化电压Vinit1，传输至晶体管T2的第一极，因第二晶体管T2处于导通状态，此时，第一节点N1电压Vinit1为高电压，例如高于VDD，第二节点N2电压Vinit2为低电压，例如低于VSS，第三节点N3保持为第一电源电压，例如VDD。其中，第一晶体管T1的栅极和其源极的电压差Vgs等于第二节点N2电压Vinit2与第一节点N1电压Vinit1的差而高于第一晶体管T1的阈值电压Vth，从而第一晶体管T1导通，而第一晶体管T1的栅极与其漏极之间的电压差Vgd等于Vinit1与VDD的差且小于Vth，所以第一晶体管T1仅处于关态和饱和态两种状态，从而有利于稳定第一晶体管T1的特性。
在阈值电压补偿阶段t2，停止输入第二复位控制信号，关闭第二复位电路420，输入栅极扫描信号GN，开启数据写入电路200，通过数据写入电路200将参考电压Vref输入驱动电路100的控制端130，输入第一发光控制信号，开启第一发光控制电路500，从而，可以通过导通的驱动电路100和存储电路300对驱动电路100进行阈值补偿。例如，在阈值电压补偿阶段t2，第一发光控制信号EM1可以为高电压，从而使得第五晶体管T5导通。第二复位控制信号RST2为低电压，使得第四晶体管T4截止。栅极扫描信号GN可以为高电压，从而使得第二晶体管T2导通。同时，数据信号端将参考电压Vref，例如可以为第一初始化电压Vinit1，传输至晶体管T2的第一极，因第二晶体管T2处于导通状态，从而，与第二晶体管T2的第二极相连的第一节点N1的电压也是第一初始化电压Vinit1，例如可以是高电压。此时，第一节点N1的电压第一初始化电压Vinit1为高电压，例如高于VDD， 第三节点N3的电压为高电压，例如为VDD，第二节点N2的电压由初始的第二初始化电压Vinit2逐渐升高，直至第一晶体管T1的栅极和其源极的电压差Vgs等于第一晶体管T1的阈值电压Vth，此时第二节点N2的电压为第一初始化电压Vinit1与第一晶体管T1的阈值电压Vth的差，从而，第一晶体管T1的阈值电压Vth写到了第一电容器C1的两端。由于第二节点N2连接的发光器件EL可以看做是一个电容，且其电容值远大于第一电容器C1，因此第二节点N2点的电压几乎不变，且保持为上一阶段t2的第一初始化电压Vinit1与第一晶体管T1的阈值电压Vth的差值，因而补偿了第一晶体管T1的阈值电压Vth，以完成阈值电压的补偿。
在数据写入阶段t3，输入栅极扫描信号GN，开启数据写入电路200，通过数据写入电路200将数据信号Vdata写入驱动电路100的控制端130，并通过存储电路300存储写入的数据信号Vdata。例如，在数据写入阶段t3，第一发光控制信号EM1可以为低电压，从而使得第五晶体管T5截止。第二复位控制信号RST2为低电压，使得第四晶体管T4截止。栅极扫描信号GN可以为高电压，从而使得第二晶体管T2导通。同时，数据信号端将数据电压Vdata，传输至晶体管T2的第一极，因第二晶体管T2处于导通状态，此时，第一节点N1的电压由第一初始化电压Vinit1变为更高电压，例如可以是Vdata，即数据电压Vdata(数据信号Vdata的电压)，从而使得第一晶体管T1导通。同时，由于第一节点N1的电压变为数据电压Vdata，存储电容C1可以存储该数据电压Vdata，从而完成了数据写入。
在迁移率补偿阶段t4，停止输入第二复位控制信号，关闭第二复位电路420，输入栅极扫描信号GN，开启数据写入电路200并输入数据电压Vdata，输入第一发光控制信号，开启第一发光控制电路500，从而，可以通过导通的第一发光控制电路500和导通的数据写入电路200进行迁移率补偿。例如，在迁移率补偿阶段t4，第一发光控制信号EM1可以为高电压，从而使得第五晶体管T5导通。第二复位控制信号RST2为低电压，使得第四晶体管T4截止。栅极扫描信号GN可以为高电压，从而使得第二晶体管T2导通。同时，数据信号端将数据电压Vdata传输至晶体管T2的第一极，因第二晶体管T2处于导通状态，此时，第一节点N1的电压保持为更高电压，例如可以是Vdata。此时，第一晶体管T1导通，驱动电流Ids从第一电源电压端，例如可以是VDD端流向第二节点N2，第二节点N2的电压逐渐升高ΔV，此时N2电压V N2为第一初始化电压Vinit1与第一晶体管T1的阈值电压Vth的差值与逐渐升高的电压ΔV的和，如下面的公式所述：
V N2＝Vinit1-Vth+ΔV
其中，V N2是第二节点N2的电压，Vinit1是第二节点N2的电压V N2为第一初始化电压，Vth是第一晶体管T1的阈值电压，ΔV是第二节点N2的电压的逐渐升高值。第一节点N1的电压由于第二晶体管T2的导通仍然为数据电压Vdata。因为第一晶体管T1的驱动电流如下面的公式所述：
Ids＝kμ(Vgs-Vth) 2
其中，Ids是第一晶体管T1的驱动电流，k是常数系数，μ是第一晶体管T1的迁移率， Vgs是第一晶体管T1的栅极和其源极的电压差，Vth是第一晶体管T1的阈值电压。由上述公式可以看出，第一晶体管T1的驱动电流第一晶体管T1的迁移率μ越大，其驱动电流越大，第二节点N2的电压逐渐升高的电压ΔV也就越大，因此第一晶体管T1栅极和其源极压差电Vgs就越小，所以(Vgs-Vth) 2越小，又因为第一晶体管T1的迁移率μ越大，所以第一晶体管T1的驱动电流Ids得到校正。例如，不同迁移率的驱动晶体管在相同数据电压Vdata下的驱动电流差异不大。
在发光阶段t5，停止输入第二复位控制信号，关闭第二复位电路420，停止输入栅极扫描信号GN，关闭数据写入电路200，输入第一发光控制信号，开启第一发光控制电路500，从而，第一电源电压可以通过导通的第一发光控制电路500和导通的驱动电路100驱动发光元件发光。例如，在发光阶段t5，第一发光控制信号EM1可以为高电压，从而使得第五晶体管T5导通。第二复位控制信号RST2为低电压，使得第四晶体管T4截止。栅极扫描信号GN为低电压，从而使得第二晶体管T2截止。此时，第二节点N2的电压升高超过发光器件EL的启亮电压，发光器件EL开始发光，因为是恒流驱动，因此最后第二节点N2的电压会到达发光器件的启亮电压，同时由于第一节点N1与第二节点N2通过第一电容C1相连，因此第一节点N1的电压也同样跟随第二节点N2的电压升高到稳定状态，即使N1、N2两节点电压发生变化，N1、N2两节点电压压差即第一晶体管T1栅极和其源极电压差Vgs可以保持不变，因此发光电流I恒定，如下面的公式所述：
I＝kμ(Vdata-ΔV) 2
其中，I是发光电流，k是常数系数，μ是第一晶体管T1的迁移率，Vdata是数据信号电压，ΔV是第二节点N2的电压的逐渐升高值。因而，该像素电路兼具阈值电压补偿、迁移率μ补偿和电压降(IR Drop)补偿的技术效果。
本公开的实施例提供的像素电路的驱动方法的技术效果参考上述实施例中关于像素电路10的相应描述，在此不再赘述。
本公开至少一些实施例还提供一种显示面板，包括阵列布置的多个像素单元，例如，该多个像素单元每个包括本公开任一实施例提供的像素电路。
图9A为本公开一些实施例提供的一种显示面板的示意框图。如图9A所示显示面板11设置在显示装置1中，并与栅极驱动器12、定时控制器13和数据驱动器14电连接。该显示面板11包括根据多条扫描线GL和多条数据线DL交叉限定的像素单元P；栅极驱动器12用于驱动多条扫描线GL；数据驱动器14用于驱动多条数据线DL；定时控制器13用于处理从显示装置1外部输入的图像数据RGB、向数据驱动器14提供处理的图像数据RGB以及向栅极驱动器12和数据驱动器14输出扫描控制信号GCS和数据控制信号DCS，以对栅极驱动器12和数据驱动器14进行控制。
例如，该显示面板11包括多个像素单元P，该像素单元P包括上述实施例中提供的任一像素电路10。例如，包括图2B所示像素电路10。如图9A所示，显示面板11还包括多条扫描线GL和多条数据线DL。例如，该多条扫描线对应连接到每行像素单元的像素电路 10中的数据写入电路200以提供栅极扫描信号，并且该多条扫描线还对应连接到每行像素单元的像素电路10中的第一复位电路410以提供第一复位控制信号。
例如，像素单元P设置在扫描线GL和数据线DL的交叉区域。例如，如图9A所示，每个像素单元P连接到两条扫描线GL(分别提供栅极扫描信号和第一复位控制信号)、一条数据线DL、用于提供第一电源电压的第一电源电压线、用于提供第二电源电压的第二电源电压线以及用于提供第一初始化电压的第一初始化电压线。例如，第一电压线或第二电压线可以用相应的板状公共电极(例如公共阳极或公共阴极)替代。需要说明的是，在图9A中仅示出了部分的像素单元P、扫描线GL、数据线DL。
例如，该多个像素单元P排列为多行，每一行像素单元P的像素电路的第一复位电路410连接到一条扫描线GL以接收第一复位控制信号，每一行像素单元P的像素电路的数据写入电路200连接到另一条扫描线GL以接收栅极扫描信号。例如，每一列的数据线DL和本列像素电路10中的数据写入电路200连接以提供数据信号。
图9B为本公开一些实施例提供的一种显示面板的示意框图。如图9B所示显示面板11与显示装置的连接关系与图9A所示的面板相同，此处不再赘述。
例如，该显示面板11包括多个像素单元P，该像素单元P包括上述实施例中提供的任一像素电路10。例如，包括图7B所示像素电路10。如图9B所示，显示面板11还包括多条扫描线GL和多条数据线DL。例如，该多条扫描线还对应连接到每行像素单元的像素电路10中的电压传输电路800以提供电压传输控制信号。
例如，像素单元P设置在扫描线GL和数据线DL的交叉区域。例如，如图9B所示，每个像素单元P相比于图9A所示的每个像素单元还连接到一条扫描线GL(提供第一发光控制信号)。需要说明的是，在图9B中仅示出了部分的像素单元P、扫描线GL、数据线DL。
例如，该多个像素单元P排列为多行，每一行像素单元P的像素电路的第一发光控制电路500连接到一条扫描线GL以接收第一发光控制信号。
例如，如图9B所示，该显示面板上包括可以提供第二电源电压的第一电源电压线，同时，根据本公开一些实施例提供的另一像素电路10，该像素电路可以通过第一电源电压端与提供第二电源电压的第一电源电压线连接，从而可以从第一电源电压端接收第二电源电压。
例如，如图9B所示，该显示面板11包括多个像素单元P，该像素单元P包括上述实施例中提供的任一像素电路10。例如，包括图8B所示像素电路10。该显示面板上包括可以提供第二复位控制信号的扫描线GL，同时，根据本公开一些实施例提供的另一像素电路10，该像素电路可以通过第一复位控制信号端与提供第二复位控制信号的扫描线GL连接，从而可以从第一复位控制信号端接收第二复位控制信号。与此同时，该显示面板上包括可以提供第一初始化电压的数据线DL，该像素电路可以通过数据信号端与提供第一初始化电压的数据线DL连接，从而可以从数据信号端接收第一复位控制信号。
图9C为本公开一些实施例提供的一种显示面板的示意框图。如图9C所示显示面板11与显示装置的连接关系与图9A所示的面板相同，此处不再赘述。
例如，图9C所示的显示面板11包括多个像素单元P，该像素单元P包括上述实施例中提供的任一像素电路10。例如，包括图3B所示像素电路10。如图9C所示，显示面板11还包括多条扫描线GL和多条数据线DL。例如，该多条扫描线还对应连接到每行像素单元的像素电路10中的第二复位电路420以提供第二复位控制信号。
例如，像素单元P设置在扫描线GL和数据线DL的交叉区域。例如，如图9C所示，每个像素单元P相比于图9A所示的每个像素单元还连接到一条扫描线GL(提供第二复位控制信号)以及用于提供第二初始化电压的第二初始化电压线。需要说明的是，在图9C中仅示出了部分的像素单元P、扫描线GL、数据线DL。
例如，该多个像素单元P排列为多行，每一行像素单元P的像素电路的第二复位电路420连接到一条扫描线GL以接收第二复位控制信号，每一行像素单元P的像素电路的第二初始化电压端连接到第二初始化电压线以接收第二初始化电压。
图9D为本公开一些实施例提供的一种显示面板的示意框图。如图9D所示显示面板11与显示装置的连接关系与图9C所示的面板相同，此处不再赘述。
例如，图9D所示的显示面板11包括多个像素单元P，该像素单元P包括上述实施例中提供的任一像素电路10。例如，包括图4B所示像素电路10。如图9B所示，显示面板11还包括多条扫描线GL和多条数据线DL。例如，该多条扫描线还对应连接到每行像素单元的像素电路10中的第一发光控制电路500以提供第一发光控制信号。
例如，像素单元P设置在扫描线GL和数据线DL的交叉区域。例如，如图9D所示，每个像素单元P相比于图9C所示的每个像素单元还连接到一条扫描线GL(提供第一发光控制信号)。需要说明的是，在图9D中仅示出了部分的像素单元P、扫描线GL、数据线DL。
例如，该多个像素单元P排列为多行，每一行像素单元P的像素电路的第一发光控制电路500连接到一条扫描线GL以接收第一发光控制信号。
例如，如图9D所示，该显示面板11包括多个像素单元P，该像素单元P包括上述实施例中提供的任一像素电路10。例如，包括图6B所示像素电路10。该显示面板上包括可以提供第二发光控制信号的扫描线GL，同时，该像素电路10可以通过第一发光控制信号端与提供第二发光控制信号的扫描线GL连接，从而可以从第一发光控制信号端接收第二发光控制信号。同时，第二复位控制信号与栅极扫描信号可以共用一条扫描线GL，可以简化显示面板周围的布局空间，从而可以实现高分辨率显示面板的开发。
图9E为本公开一些实施例提供的一种显示面板的示意框图。如图9E所示显示面板11与显示装置的连接关系与图9D所示的面板相同，此处不再赘述。
例如，图9E所示的显示面板11包括多个像素单元P，该像素单元P包括上述实施例中提供的任一像素电路10。例如，包括图5B所示像素电路10。如图9E所示，显示面板 11还包括多条扫描线GL和多条数据线DL。例如，该多条扫描线还对应连接到每行像素单元的像素电路10中的第三复位电路430以提供第三复位控制信号。
例如，像素单元P设置在扫描线GL和数据线DL的交叉区域。例如，如图9E所示，每个像素单元P相比于图9D所示的每个像素单元还连接到一条扫描线GL(提供第三复位控制信号)以及用于提供保持电压的保持电压线。需要说明的是，在图9E中仅示出了部分的像素单元P、扫描线GL、数据线DL。
例如，该多个像素单元P排列为多行，每一行像素单元P的像素电路的第三复位电路430连接到一条扫描线GL以接收第三复位控制信号，每一行像素单元P的像素电路的保持电压端连接到保持电压线以接收保持电压。
需要注意的是，如图9F所示的一种显示面板的示意框图，该像素单元P的像素电路的第三复位电路430也可以通过接收第二复位控制信号来实现与第三复位电路430通过接收第三复位控制信号同样的技术效果，也即是，第三复位电路430接收的第三复位控制信号可以替换为第二复位控制信号。同时，第二复位控制信号和第三复位控制信号属于上下的两个时刻对应的信号，这样就能使得第二复位控制信号和第三复位控制信号共用一条扫描线GL，可以简化显示面板周围的布局空间，从而可以实现高分辨率显示面板的开发。
例如，栅极驱动器12根据源自定时控制器13的多个扫描控制信号GCS向多个扫描线GL提供多个选通信号。多个选通信号包括栅极扫描信号、第一复位控制信号、第二复位控制信号、第三复位控制信号、第一发光控制信号以及第二发光控制信号。这些信号通过多个扫描线GL提供给每个像素单元P。
例如，数据驱动器14使用参考伽玛电压根据源自定时控制器13的多个数据控制信号DCS将从定时控制器13输入的数字图像数据RGB转换成数据信号。数据驱动器14向多条数据线DL提供转换的数据信号。
例如，定时控制器13对外部输入的图像数据RGB进行处理以匹配显示面板11的大小和分辨率，然后向数据驱动器14提供处理的图像数据。定时控制器13使用从显示装置外部输入的同步信号(例如点时钟DCLK、数据使能信号DE、水平同步信号Hsync以及垂直同步信号Vsync)产生多条扫描控制信号GCS和多条数据控制信号DCS。定时控制器13分别向栅极驱动器12和数据驱动器14提供产生的扫描控制信号GCS和数据控制信号DCS，以用于栅极驱动器12和数据驱动器14的控制。
例如，数据驱动电器14可以与多条数据线DL连接，以提供数据信号Vdata；同时还可以与多条第一电压线、多条第二电压线和多条初始化电压线连接以分别提供第一电压、第二电压和初始化电压。
例如，栅极驱动器12和数据驱动器14可以实现为半导体芯片。该显示装置1还可以包括其他部件，例如信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，本实施例中的显示装置可以为：显示器、电视、电子纸显示装置、手机、平板 电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。需要说明的是，该显示装置还可以包括其他常规部件或结构，例如，为实现显示装置的必要功能，本领域技术人员可以根据具体应用场景设置其他的常规部件或结构，本公开的实施例对此不做限制。
本公开的至少一些实施例提供的显示装置的技术效果可以参考上述实施例中关于像素电路10的相应描述，在此不再赘述。
对于本公开，有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围由所附的权利要求确定。

Claims (18)

  1. 一种像素电路，包括：驱动电路、数据写入电路、存储电路和第一复位电路；其中，
    所述驱动电路包括控制端、第一端和第二端，且被配置为控制流经所述第一端和所述第二端的用于驱动发光元件发光的驱动电流；
    所述数据写入电路被配置为在第一扫描信号的控制下将数据信号写入所述驱动电路的控制端；
    所述存储电路被配置为存储所述数据信号；
    所述第一复位电路被配置为在第一复位控制信号的控制下将第一初始化电压施加至所述驱动电路的控制端；
    其中，所述驱动电路和所述数据写入电路各自均包括N型薄膜晶体管，所述第一复位电路包括N型氧化物薄膜晶体管。
  2. 根据权利要求1所述的像素电路，其中，所述驱动电路包括的所述N型薄膜晶体管为第一晶体管；
    所述第一晶体管的栅极作为所述驱动电路的控制端，所述第一晶体管的第一极作为所述驱动电路的第一端，所述第一晶体管的第二极作为所述驱动电路的第二端。
  3. 根据权利要求1或2所述的像素电路，其中，所述数据写入电路包括的所述N型薄膜晶体管为第二晶体管；
    所述第二晶体管的栅极和第一扫描信号端连接以接收所述第一扫描信号，所述第二晶体管的第一极和数据信号端连接以接收所述数据信号，所述第二晶体管的第二极和所述驱动电路的控制端连接。
  4. 根据权利要求1-3任一项所述的像素电路，其中，所述存储电路包括存储电容，
    所述存储电容的第一极与所述驱动电路的控制端连接，所述存储电容的第二极与所述驱动电路的第二端连接。
  5. 根据权利要求1-4任一项所述的像素电路，其中，所述第一复位电路包括的所述N型氧化物薄膜晶体管为第三晶体管；
    所述第三晶体管的栅极和第一复位控制信号端连接以接收所述第一复位控制信号，所述第三晶体管的第一极和第一初始化电压端连接以接收所述第一初始化电压，所述第七晶体管的第二极和所述驱动电路的控制端连接。
  6. 根据权利要求1-5任一项所述的像素电路，还包括：第二复位电路，其中，
    所述第二复位电路被配置为在第二复位控制信号的控制下将第二初始化电压施加至所述驱动电路的第二端。
  7. 根据权利要求6所述的像素电路，其中，所述第二复位电路包括第四晶体管，所述第四晶体管为N型薄膜晶体管，
    所述第四晶体管的栅极和第二复位控制信号端连接以接收所述第二复位控制信号，所 述第四晶体管的第一极和第二初始化电压端连接以接收所述第二初始化电压，所述第四晶体管的第二极和所述驱动电路的第二端连接。
  8. 根据权利要求6或7所述的像素电路，还包括：第一发光控制电路，其中，
    所述第一发光控制电路被配置为在第一发光控制信号的控制下将第一电源电压施加至所述驱动电路的第一端。
  9. 根据权利要求8所述的像素电路，其中，所述第一发光控制电路包括第五晶体管，所述第五晶体管为N型薄膜晶体管，
    所述第五晶体管的栅极和第一发光控制端连接以接收所述第一发光控制信号，所述第五晶体管的第一极和第一电源端连接以接收所述第一电源电压，所述第五晶体管的第二极和所述驱动电路的第一端连接。
  10. 根据权利要求8或9所述的像素电路，还包括：第三复位电路，其中，
    第三复位电路被配置为在第三复位控制信号的控制下将保持电压施加至所述驱动电路的第一端，
    所述第三复位控制信号和所述第一复位控制信号至少部分时间段内同时为开启信号。
  11. 根据权利要求10所述的像素电路，其中，所述第三复位电路包括第六晶体管，所述第六晶体管为N型薄膜晶体管，
    所述第六晶体管的栅极和第三复位控制信号端连接以接收所述第三复位控制信号，所述第六晶体管的第一极和保持电压端连接以接收所述保持电压，所述第六晶体管的第二极和所述驱动电路的第一端连接。
  12. 根据权利要求10或11所述的像素电路，其中，所述第三复位控制信号与所述第一复位控制信号为同一控制信号。
  13. 根据权利要求6或7所述的像素电路，还包括：第二发光控制电路，其中，
    所述第二发光控制电路被配置为在第二发光控制信号的控制下将所述驱动电流施加至所述发光元件的第一极。
  14. 根据权利要求13所述的像素电路，其中，所述第二发光控制电路包括第七晶体管，所述第七晶体管为N型薄膜晶体管，
    所述第七晶体管的栅极和第二发光控制端连接以接收所述第二发光控制信号，所述第七晶体管的第一极和所述驱动电路的第二端连接，所述第七晶体管的第二极和所述发光元件的第一极连接。
  15. 根据权利要求1-5任一项所述的像素电路，还包括：电压传输电路，其中，
    所述电压传输电路被配置为在电压传输控制信号的控制下，在第一时间段内将第二电源电压传输至所述驱动电路的第一端，以及在第二时间段内将不同于所述第二电源电压的第一电源电压传输至所述驱动电路的第一端。
  16. 根据权利要求15所述的像素电路，其中，所述电压传输电路包括第八晶体管，所述第八晶体管为N型薄膜晶体管，
    所述第八晶体管的栅极和电压传输控制信号端连接以接收所述电压传输控制信号，所述第八晶体管的第一极和第一电源端连接，所述第八晶体管的第二极和所述驱动电路的第一端连接，
    所述第一电源端被配置为在所述第一时间段内提供所述第二电源电压，以及在所述第二时间段内提供所述第一电源电压。
  17. 一种显示面板，包括：阵列排布的多个像素单元；其中，
    每个所述像素单元包括根据权利要求1-16任一项所述的像素电路。
  18. 一种根据权利要求1-16任一项所述的像素电路的驱动方法，包括：初始化阶段、阈值电压补偿阶段、数据写入与迁移率补偿阶段、发光阶段，其中，
    在所述初始化阶段，输入所述第一复位控制信号和所述第二复位控制信号，开启所述第一复位电路和所述第二复位电路，通过所述第一复位电路将所述第一初始化电压施加至所述驱动电路的控制端以对所述驱动电路的控制端进行复位，通过所述第二复位电路将所述第二初始化电压施加至所述驱动电路的第二端以对所述驱动电路的第二端进行复位；
    在所述阈值电压补偿阶段，输入所述第一复位控制信号，开启所述第一复位电路，通过所述第一复位电路将所述第一初始化电压施加至所述驱动电路的控制端，以导通所述驱动电路，停止输入所述第二复位控制信号，关闭所述第二复位电路，通过导通的所述驱动电路和所述存储电路进行阈值补偿；
    在所述数据写入阶段，输入所述栅极扫描信号，开启所述数据写入电路，通过所述数据写入电路将所述数据信号写入所述驱动电路的控制端，并通过所述存储电路存储写入的所述数据信号；
    在所述发光阶段，停止输入所述栅极扫描信号，关闭所述数据写入电路，使所述驱动电路将在所述存储电路存储的所述数据信号的控制下产生驱动电流，以驱动所述发光元件发光。
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