[go: up one dir, main page]

WO2021175150A1 - 像素驱动电路及其控制方法、显示面板 - Google Patents

像素驱动电路及其控制方法、显示面板 Download PDF

Info

Publication number
WO2021175150A1
WO2021175150A1 PCT/CN2021/077905 CN2021077905W WO2021175150A1 WO 2021175150 A1 WO2021175150 A1 WO 2021175150A1 CN 2021077905 W CN2021077905 W CN 2021077905W WO 2021175150 A1 WO2021175150 A1 WO 2021175150A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
signal line
gate
electrically connected
level
Prior art date
Application number
PCT/CN2021/077905
Other languages
English (en)
French (fr)
Inventor
刘利宾
李梅
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/432,467 priority Critical patent/US20230360599A1/en
Publication of WO2021175150A1 publication Critical patent/WO2021175150A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a control method thereof, and a display panel.
  • OLED organic light-emitting diode
  • the embodiments of the present disclosure provide a pixel driving circuit and a control method thereof, and a display panel.
  • a pixel driving circuit for driving light emitting diodes to emit light including: a reset module; the reset module includes: a double-gate first transistor and a second transistor;
  • the first electrode of the double-gate first transistor is electrically connected to the initial signal line, the second electrode of the double-gate first transistor is electrically connected to the first node; the first electrode of the second transistor is electrically connected to the double An intermediate node of the gate-type first transistor, and the second electrode of the second transistor is electrically connected to the anode of the light emitting diode;
  • the two control electrodes of the double-gate first transistor and the control electrode of the second transistor are both electrically connected to a reset signal line; the reset module is used to use all the electrodes under the control of the reset signal of the reset signal line The initial signal of the initial signal line resets the first node and the anode of the light emitting diode;
  • the second transistor and a part of the first dual-gate transistor form a dual-gate transistor.
  • it also includes:
  • the driving module is electrically connected to the first node, the second node, and the third node, and is configured to guide the path between the second node and the third node under the control of the voltage of the first node And make the path generate current for making the light emitting diode emit light.
  • it further includes: a first lighting control module and a second lighting control module;
  • the first lighting control module is electrically connected to a lighting control signal line, the second node and the anode, and the second lighting control module is electrically connected to the lighting control signal line, a voltage signal line, and the third node;
  • the first light-emitting control module and the second light-emitting control module are respectively configured to transmit the current for making the light-emitting diode to emit light under the control of the light-emitting control signal of the light-emitting control signal line. ⁇ anodes.
  • it also includes:
  • the drive control module is electrically connected to the gate drive signal line, the data signal line and the third node, and is configured to transfer the data of the data signal line under the control of the gate drive signal of the gate drive signal line. The signal is written to the third node.
  • the driving module includes: a double-gate third transistor, a fourth transistor, and a storage capacitor;
  • the two control electrodes of the double-gate third transistor are electrically connected to the gate drive signal line
  • the first electrode of the double-gate third transistor is electrically connected to the first node
  • the double-gate third transistor is electrically connected to the first node.
  • the second electrode of the third transistor is electrically connected to the second node;
  • the control electrode of the fourth transistor is electrically connected to the first node, and the first electrode of the fourth transistor is electrically connected to the second node.
  • the second electrode of the fourth transistor is electrically connected to the third node;
  • the first end of the storage capacitor is electrically connected to the voltage signal line, and the second end of the storage capacitor is electrically connected to the first node.
  • the first light emission control module includes a fifth transistor
  • control electrode of the fifth transistor is electrically connected to the light emission control signal line
  • first electrode of the fifth transistor is electrically connected to the anode
  • second electrode of the fifth transistor is electrically connected to the second node
  • the second light emission control module includes a sixth transistor
  • the control electrode of the sixth transistor is electrically connected to the light emission control signal line, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the voltage signal line .
  • the drive control module includes a seventh transistor, a control electrode of the seventh transistor is electrically connected to the gate drive signal line, a first electrode of the seventh transistor is electrically connected to the third node, and The second electrode of the seventh transistor is electrically connected to the data signal line.
  • the double-gate first transistor, the second transistor, the double-gate third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type thin film transistors.
  • the double-gate first transistor, the second transistor, the double-gate third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type low temperature polysilicon thin film transistors.
  • the double-gate first transistor and the second transistor are N-type oxide thin film transistors
  • the double-gate third transistor, the fourth transistor, the fifth transistor, and the second transistor are N-type oxide thin film transistors.
  • the sixth transistor and the seventh transistor are both P-type low-temperature polysilicon thin film transistors.
  • the light emitting diode is an organic light emitting diode or a miniature light emitting diode.
  • a display panel including the above-mentioned pixel driving circuit.
  • the display panel is an organic light emitting diode display panel, a Micro LED display panel, or a Mini LED display panel.
  • a control method for controlling the above-mentioned pixel driving circuit.
  • the third, fourth, fifth, sixth, and seventh double-gate transistors are all P-type thin film transistors. , The method includes:
  • the light emission control signal having the first level is input to the light emission control signal line
  • the gate drive signal having the first level is input to the gate drive signal line
  • the first reset signal is input to the reset signal line
  • the data signal having the first level is input to the data signal line
  • the voltage signal having the first level is input to the voltage signal line
  • the initial signal line Inputting a voltage signal having the second level
  • the light emission control signal having the first level is input to the light emission control signal line
  • the gate drive signal having the second level is input to the gate drive signal line
  • the light emission control signal having the second level is input to the light emission control signal line
  • the gate drive signal having the first level is input to the gate drive signal line
  • the voltage value of the first level is greater than the voltage value of the second level.
  • the first reset signal is a reset signal having the second level
  • the second reset The signal is a reset signal having the first level
  • the reset signal having the first level is input to the reset signal line
  • the reset signal having the first level is input to the reset signal line.
  • the first reset signal is a reset signal having the first level
  • the second reset The signal is a reset signal having the second level
  • the method further includes:
  • the reset signal having the second level is input to the reset signal line
  • the reset signal having the second level is input to the reset signal line.
  • the present disclosure provides a computing processing device, including:
  • a memory in which computer readable codes are stored
  • One or more processors when the computer-readable code is executed by the one or more processors, the computing processing device executes the above-mentioned control method.
  • the present disclosure provides a computer program, including computer-readable code, which when the computer-readable code runs on a computing processing device, causes the computing processing device to execute the above-mentioned control method.
  • the present disclosure provides a computer-readable medium in which the above-mentioned computer program is stored.
  • FIG. 1 is a circuit diagram of a pixel driving circuit provided by an embodiment of the disclosure
  • FIG. 2 is a signal timing diagram of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 3 is a diagram of a pixel driving circuit in the related art
  • FIG. 4 is a diagram of a pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 5 schematically shows a block diagram of a computing processing device for executing the method according to the present disclosure.
  • Fig. 6 schematically shows a storage unit for holding or carrying program codes for implementing the method according to the present disclosure.
  • the gate of the transistor is referred to as a control electrode
  • one of the source and drain is referred to as a first electrode
  • the other is referred to as a second electrode.
  • the first electrode of all transistors is referred to as the drain and the second electrode is referred to as the source for illustration.
  • a pixel driving circuit for driving light-emitting diodes to emit light includes:
  • Double-gate first transistor and second transistor wherein the first electrode of the double-gate first transistor is electrically connected to the initial signal line, the second electrode is electrically connected to the first node, and the two gates are electrically connected to the reset signal line; second The first pole of the transistor is electrically connected to the initial signal line, the second pole is electrically connected to the anode of the light emitting diode, and the gate is electrically connected to the gate driving signal line.
  • the double-gate third transistor, the fourth transistor and the storage capacitor wherein the two control electrodes of the double-gate third transistor are electrically connected to the gate drive signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected To the second node; the control electrode of the fourth transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node; the first end of the storage capacitor is electrically connected to the voltage signal line and the second node The terminal is electrically connected to the first node.
  • the fifth transistor and the sixth transistor wherein the control electrode of the sixth transistor is electrically connected to the light-emitting control signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the voltage signal line; the control electrode of the fifth transistor is electrically connected to emit light The control signal line, the first pole is electrically connected to the anode, and the second pole is electrically connected to the second node.
  • a seventh transistor The control electrode of the seventh transistor is electrically connected to the gate drive signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the data signal line.
  • the above pixel driving circuit can be used to drive the light emitting diode to emit light.
  • the anode voltage of the light emitting diode is relatively high, and the anode, the second transistor and the initial signal line are likely to form a leakage path, that is, leakage phenomenon occurs, and the amount of leakage will increase with the low frequency time. Lengthen and increase, which seriously affects the display effect.
  • the present disclosure provides a pixel driving circuit for driving light-emitting diodes to emit light.
  • the pixel driving circuit includes: a reset module 5;
  • the reset module 5 includes: a double-gate first transistor T1 and a second transistor T2; the first electrode of the double-gate first transistor T1 is electrically connected to the initial signal line Vint, and the second electrode of the double-gate first transistor T1 is electrically connected to the A node n1; the first electrode of the second transistor T2 is electrically connected to the intermediate node n5 of the double-gate first transistor T1, and the second electrode of the second transistor T2 is electrically connected to the anode; the two control electrodes of the double-gate first transistor T1 , The control electrodes of the second transistor T2 are electrically connected to the reset signal line Reset; the reset module 5 is used for under the control of the reset signal of the reset signal line Reset, use the initial signal of the initial signal line Vint to contact the first node n1 and the light emitting diode 6 Reset the anode;
  • the second transistor T2 and a part of the double-gate first transistor T1 form a double-gate transistor.
  • a driving module 1 which is electrically connected to the first node n1, the second node n2, and the third node n3, and is configured to connect the second node n2 to the third node n1 under the control of the voltage of the first node n1.
  • the path between the three nodes n3 is turned on, and a current for causing the light emitting diode 6 to emit light is generated in the path.
  • first light emission control module 2 and a second light emission control module 3.
  • the first light emission control module 2 is electrically connected to the light emission control signal line EM, the second node n2 and the anode of the light emitting diode 6, and the second light emission control
  • the module 3 is electrically connected to the light emission control signal line EM, the voltage signal line VDD, and the third node n3.
  • the first light emission control module 2 and the second light emission control module 3 are respectively configured to be under the control of the light emission control signal of the light emission control signal line EM , The current used to make the light emitting diode 6 emit light is transmitted to the anode.
  • a drive control module 4 which is electrically connected to the gate drive signal line Gate, the data signal line Vdata, and the third node n3, and is configured to be controlled by the gate drive signal of the gate drive signal line Gate, The data signal of the data signal line Vdata is written into the third node n3.
  • the specific circuit structures included in the above-mentioned driving module, the first light-emitting control module, the second light-emitting control module, and the driving control module are not limited, as long as the corresponding functions are satisfied.
  • the above-mentioned double-gate first transistor T1 includes two single-gate transistors T1a and T1b connected in series.
  • the second transistor T2 is a single-gate transistor, and the single-gate transistor T1a can form a new double-gate transistor T; at this time, the single-gate transistor T1a and the single-gate transistor T1b can still form the double-gate first transistor T1 .
  • the types of the above-mentioned double-gate first transistor and the second transistor which may be thin film transistors, field effect transistors, or the like.
  • the former is mostly used.
  • the size of the above-mentioned double-gate first transistor and the second transistor is not limited here.
  • the double-gate first transistor can choose a tube with a width-to-length ratio of 3um/(3+3)um.
  • the second The double-gate transistor composed of the transistor and the single-gate transistor T1a can choose a tube with a width-to-length ratio of 3um/(3+3)um.
  • first node, second node, and third node are only defined for the convenience of describing the circuit structure, and the first node, second node, and third node are not an actual circuit unit.
  • the first electrode of the second transistor T2 is called the drain (D), the second electrode is called the source (S), and the control electrode is called the gate (G).
  • the cathode of the light emitting diode 6 may be electrically connected to the ground terminal VSS.
  • the first electrode of the second transistor in the reset module is electrically connected to the intermediate node of the double-gate first transistor, and the two control electrodes of the double-gate first transistor and the control electrode of the second transistor are both electrically connected to the reset signal line , So that the second transistor and a part of the double-gate first transistor form a double-gate transistor.
  • the double-gate transistor can greatly reduce the leakage of the anode, thereby reducing the influence of the anode leakage on the display effect, thereby improving the quality of the product.
  • the double-gate structure of the second transistor can also be realized by adding a transistor, but this will undoubtedly increase the layout space.
  • the present disclosure uses the idea of common gate to form a double-gate transistor with a part of the second transistor and the first double-gate transistor without increasing the number of tubes.
  • the second transistor T2 is connected between the transistor T1a and the transistor T1b, and the transistor T1a and the transistor T1b are arranged longitudinally; the initial signal line Vint is set on the lower side of the reset signal line Reset; the reset signal line Reset is set to two, one It is electrically connected to the transistor T1a, and the other is electrically connected to the transistor T1b and the second transistor T2.
  • the width-to-length ratio of the double-gate transistor composed of the transistor T1a and the transistor T1b is (2 ⁇ 4)um/[2+(2 ⁇ 4)]um, and the second transistor T2 is in the range of (2 ⁇ 4) um/(2 ⁇ 4)um;
  • the second transistor and the transistor T1a form a double-gate transistor. Compared with FIG.
  • the connection position and arrangement position of the transistor T1a, the transistor T1b, and the second transistor T2 in FIG. 4 change, and the relative positions of the initial signal line Vint and the reset signal line Reset change; the initial signal line Vint only needs to be
  • the transistor T1a needs to be electrically connected and does not need to be electrically connected to the second transistor T2, thereby saving some space; although the number of reset signal lines Reset increases, the space for the initial signal line Vint is reduced. After the two are offset, the overall There is no increase in layout space.
  • the above-mentioned pixel driving circuit does not add additional layout space and does not increase the size of existing products, so that it can be applied to high-resolution (HPPI) display panels.
  • the above-mentioned driving module 1 includes: a double-gate third transistor T3, a fourth transistor T4, and a storage capacitor Cst.
  • the two control electrodes of the double-gate third transistor T3 are electrically connected to the gate drive signal line Gate, the first electrode is electrically connected to the first node n1, and the second electrode is electrically connected to the second node n2;
  • the control electrode is electrically connected to the first node n1, the first electrode is electrically connected to the second node n2, and the second electrode is electrically connected to the third node n3;
  • the first end of the storage capacitor Cst is electrically connected to the voltage signal line VDD, and the second end is electrically connected to the second node.
  • the double-gate third transistor T3 in FIG. 1 does not show two single-gate transistors connected in series, but a double-gate transistor is used instead.
  • the first light emission control module 2 includes a fifth transistor T5
  • the second light emission control module 3 includes a sixth transistor T6.
  • the control electrode of the sixth transistor T6 is electrically connected to the light emission control signal line EM, the first electrode is electrically connected to the third node n3, and the second electrode is electrically connected to the voltage signal line VDD; the control electrode of the fifth transistor T5 is electrically connected to the light emission control signal line EM, the first electrode is electrically connected to the anode, and the second electrode is electrically connected to the second node n2.
  • the first electrode of the fifth transistor T5 and the second electrode of the second transistor T2 may be electrically connected to the fourth node n4, and the fourth node n4 is electrically connected to the anode of the light emitting diode.
  • the drive control module 4 includes a seventh transistor T7, the control electrode of the seventh transistor T7 is electrically connected to the gate drive signal line Gate, the first electrode is electrically connected to the third node n3, and the second electrode is electrically connected to the gate drive signal line Gate. Connect the data signal line Vdata.
  • the above-mentioned double-gate first transistor, second transistor, double-gate third transistor, fourth transistor, fifth transistor, sixth transistor, and seventh transistor are all P-type thin film transistors.
  • the double-gate first transistor, the second transistor, the double-gate third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type low temperature polysilicon thin film transistors.
  • -silicon-Thin Film Transistor, LTPS-TFT Low-temperature polysilicon thin-film transistors have higher electron mobility and shorter response time.
  • the above-mentioned double-gate first transistor and the second transistor are N-type oxide thin film transistors
  • the double-gate third transistor, fourth transistor, fifth transistor, sixth transistor, and seventh transistor are all P-type low temperature transistors.
  • the above-mentioned oxide thin film transistors may be indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) thin film transistors, indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), etc.; in practice, IGZO is mostly used Thin film transistors have better performance.
  • Indium Gallium Zinc Oxide, IGZO Indium Gallium Zinc Oxide
  • ITO Indium Tin Oxide
  • IZO indium zinc oxide
  • Thin film transistors have better performance.
  • the above-mentioned light-emitting diode is an organic light-emitting diode (OLED) or a miniature light-emitting diode.
  • the miniature light-emitting diodes here include Mini LED and Micro LED.
  • the pixel driving circuit is applied to an OLED display panel, the light-emitting diode is an organic light-emitting diode. If the aforementioned pixel driving circuit is applied to a Mini LED display panel or a Micro LED display panel, the aforementioned light emitting diode is a Mini LED or a Micro LED.
  • An embodiment of the present disclosure provides a display panel including the pixel driving circuit of the above embodiment.
  • the above-mentioned display panel may be a flexible display panel (also called a flexible screen), or a rigid display panel (that is, a display panel that cannot be bent), which is not limited here.
  • the above-mentioned display panel can be an Organic Light-Emitting Diode (OLED) display panel, a Micro LED display panel or a Mini LED display panel, and any TV, digital camera, mobile phone, tablet computer, etc. including these display panels. Products or parts with display function.
  • OLED Organic Light-Emitting Diode
  • the above-mentioned display panel has the characteristics of low anode leakage, good display effect and high product quality.
  • the embodiment of the present disclosure provides a control method for controlling the pixel driving circuit shown in FIG. 1. It should be noted that the control method can be applied to the double-gate first transistor and the second transistor are both P-type thin film transistors or both N-type thin film transistors, and the double-gate third transistor, fourth transistor, and fifth transistor The sixth transistor and the seventh transistor are both P-type thin film transistors, the first level is high level, and the second level is low level.
  • the control method includes:
  • a light-emission control signal having a first level is input to the light-emission control signal line EM, and a gate drive signal having the first level is input to the gate drive signal line Gate
  • a reset signal having a second level is input to the reset signal line Reset
  • a data signal having a first level is input to the data signal line Vdata
  • a voltage signal having a first level is input to the voltage signal line VDD
  • a voltage signal having the first level is input to the initial signal line Vint Input the voltage signal with the second level.
  • the double-gate first transistor and the second transistor are turned on, and the potential of the initial signal line Vint resets the gate of the fourth transistor T4 and the anode of the light-emitting diode;
  • the gate of the four transistor T4 is reset to a low level, and the P-type thin film transistor is turned on at a low level, so the fourth transistor T4 is turned on; the third transistor, the fifth transistor, the sixth transistor and the seventh transistor of the double-gate type are turned off .
  • This stage can be called the initialization stage.
  • a light-emission control signal having a first level is input to the light-emission control signal line EM, and a gate drive signal having a second level is input to the gate drive signal line Gate.
  • a reset signal having a first level is input to the reset signal line Reset, a data signal having a first level is input to the data signal line Vdata, a voltage signal having the first level is input to the voltage signal line VDD, and a voltage signal having the first level is input to the initial signal line Vint Input the voltage signal with the second level.
  • the third and seventh double-gate transistors are turned on, and the gate of the fourth transistor T4 is written with the voltage of Vdata+Vth and then turned off.
  • the voltage of the first node n1 is also Vdata+Vth, where, Vth is the threshold voltage of the fourth transistor; the double-gate first transistor, second transistor, fifth transistor, and sixth transistor are off.
  • This stage can be called the compensation stage.
  • the light emission control signal with the second level is input to the light emission control signal line EM
  • the gate drive signal with the first level is input to the gate drive signal line Gate
  • a reset signal having a first level is input to the reset signal line Reset
  • a data signal having a first level is input to the data signal line Vdata
  • a voltage signal having the first level is input to the voltage signal line VDD
  • a voltage signal having the first level is input to the initial signal line Vint.
  • the voltage value of the first level is greater than the voltage value of the second level.
  • the fourth transistor, the fifth transistor, and the sixth transistor are turned on, and the double-gate first transistor, the second transistor, the double-gate third transistor, and the seventh transistor are turned off.
  • the current input from the voltage signal line VDD flows into the anode of the light emitting diode, thereby driving the light emitting diode to emit light.
  • This stage can be called the light-emitting stage.
  • the above-mentioned data signal line only needs to ensure that it is high in the second period t2, and there is no requirement in the other two periods.
  • the above control method and FIG. 4 take the data signal line to be high in the three periods as an example. illustrate.
  • the conduction conditions of the N-type thin film transistor and the P-type thin film transistor are different, the former is turned on at a high level of the gate, and the latter is turned on at a low level of the gate. Therefore, the double-gate first transistor and the second transistor are N-type thin film transistors, and the double-gate third, fourth, fifth, sixth, and seventh transistors are pixel drivers of P-type thin film transistors.
  • the control method of the circuit only needs to adjust the level of the reset signal input from the gates of the first and second dual-gate transistors in different periods. Others are the same as the above control method, so I won't repeat them here.
  • the double-gate first transistor and the second transistor are N-type thin film transistors
  • the double-gate third, fourth, fifth, sixth, and seventh transistors are all pixels with P-type thin film transistors.
  • the control method adjusts the level of the reset signal as follows:
  • the reset signal having the second level is input to the reset signal line
  • the reset signal having the second level is input to the reset signal line.
  • the light-emitting diodes in the pixel driving circuit can also be controlled to emit light.
  • the embodiments of the present disclosure provide a control method by which the pixel driving circuit can drive the light-emitting diode to emit light; the control method is simple and easy to implement.
  • the various component embodiments of the present disclosure may be implemented by hardware, or by software modules running on one or more processors, or by a combination of them.
  • a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the computing processing device according to the embodiments of the present disclosure.
  • DSP digital signal processor
  • the present disclosure can also be implemented as a device or device program (for example, a computer program and a computer program product) for executing part or all of the methods described herein.
  • Such a program for realizing the present disclosure may be stored on a computer-readable medium, or may have the form of one or more signals.
  • Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.
  • FIG. 5 shows a computing processing device that can implement the method according to the present disclosure.
  • the computing processing device traditionally includes a processor 1010 and a computer program product in the form of a memory 1020 or a computer readable medium.
  • the memory 1020 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read Only Memory), EPROM, hard disk, or ROM.
  • the memory 1020 has a storage space 1030 for executing program codes 1031 of any method steps in the above methods.
  • the storage space 1030 for program codes may include various program codes 1031 respectively used to implement various steps in the above method. These program codes can be read from or written into one or more computer program products.
  • These computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards, or floppy disks.
  • Such a computer program product is usually a portable or fixed storage unit as described with reference to FIG. 6.
  • the storage unit may have storage segments, storage spaces, etc. arranged similarly to the memory 1020 in the computing processing device of FIG. 5.
  • the program code can be compressed in an appropriate form, for example.
  • the storage unit includes computer-readable codes 1031', that is, codes that can be read by, for example, a processor such as 1010. These codes, when run by a computing processing device, cause the computing processing device to execute the method described above. The various steps.
  • any reference signs placed between parentheses should not be constructed as a limitation to the claims.
  • the word “comprising” does not exclude the presence of elements or steps not listed in the claims.
  • the word “a” or “an” preceding an element does not exclude the presence of multiple such elements.
  • the present disclosure can be realized by means of hardware including several different elements and by means of a suitably programmed computer. In the unit claims listing several devices, several of these devices may be embodied in the same hardware item. The use of the words first, second, and third, etc. do not indicate any order. These words can be interpreted as names.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素驱动电路及其控制方法、显示面板，涉及显示技术领域。像素驱动电路包括：复位模块(5)；复位模块(5)包括：双栅型第一晶体管(T1)、第二晶体管(T2)；双栅型第一晶体管(T1)的第一极电连接初始信号线（Vint），双栅型第一晶体管(T1)的第二极电连接第一节点(n1)；第二晶体管(T2)的第一极电连接双栅型第一晶体管(T1)的中间节点(n5)，第二晶体管(T2)的第二极电连接发光二极管(6)的阳极；双栅型第一晶体管(T1)的两个控制极、第二晶体管(T2)的控制极均电连接复位信号线（Reset）；其中，第二晶体管(T2)与双栅型第一晶体管(T1)的一部分组成双栅型晶体管。

Description

像素驱动电路及其控制方法、显示面板
相关申请的交叉引用
本公开要求在2020年03月02日提交中国专利局、申请号为202010136752.6、名称为“一种像素驱动电路及其控制方法、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及其控制方法、显示面板。
背景技术
随着技术的不断提高，对于低频有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板的性能要求也越来越高。
概述
本公开的实施例提供一种像素驱动电路及其控制方法、显示面板。
本公开的实施例采用如下技术方案：
一方面，提供了一种像素驱动电路，用于驱动发光二极管发光，包括：复位模块；所述复位模块包括：双栅型第一晶体管、第二晶体管；
所述双栅型第一晶体管的第一极电连接初始信号线，所述双栅型第一晶体管的第二极电连接第一节点；所述第二晶体管的第一极电连接所述双栅型第一晶体管的中间节点，所述第二晶体管的第二极电连接所述发光二极管的阳极；
所述双栅型第一晶体管的两个控制极、所述第二晶体管的控制极均电连接复位信号线；所述复位模块用于在所述复位信号线的复位信号的控制下，使用所述初始信号线的初始信号对所述第一节点和所述发光二极管的所述阳极进行复位；
其中，所述第二晶体管与所述双栅型第一晶体管的一部分组成双栅型晶体管。
可选地，还包括：
驱动模块，电连接所述第一节点、第二节点和第三节点，被配置为在所述第一节点的电压的控制下将所述第二节点和所述第三节点之间的路径导通，并使所述路径中产生用于使所述发光二极管发光的电流。
可选地，还包括：第一发光控制模块和第二发光控制模块；
所述第一发光控制模块电连接发光控制信号线、所述第二节点和所述阳极，所述第二发光控制模块电连接所述发光控制信号线、电压信号线和所述第三节点；
所述第一发光控制模块和所述第二发光控制模块分别被配置为在所述发光控制信号线的发光控制信号的控制下，将所述用于使所述发光二极管发光的电流传输至所述阳极。
可选地，还包括：
驱动控制模块，电连接栅极驱动信号线、数据信号线和所述第三节点，被配置为在所述栅极驱动信号线的栅极驱动信号的控制下，将所述数据信号线的数据信号写入所述第三节点。
可选地，所述驱动模块包括：双栅型第三晶体管、第四晶体管和存储电容；
其中，所述双栅型第三晶体管的两个控制极均电连接所述栅极驱动信号线，所述双栅型第三晶体管的第一极电连接所述第一节点，所述双栅型第三晶体管的第二极电连接到所述第二节点；所述第四晶体管的控制极电连接所述第一节点，所述第四晶体管的第一极电连接到所述第二节点，所述第四晶体管的第二极电连接所述第三节点；所述存储电容的第一端电连接所述电压信号线，所述存储电容的第二端电连接所述第一节点。
可选地，所述第一发光控制模块包括第五晶体管；
其中，所述第五晶体管的控制极电连接所述发光控制信号线，所述第五晶体管的第一极电连接所述阳极，所述第五晶体管的第二极电连接所述第二节点。
可选地，所述第二发光控制模块包括第六晶体管；
所述第六晶体管的控制极电连接所述发光控制信号线，所述第六晶体管的第一极电连接所述第三节点，所述第六晶体管的第二极电连接所述电压信 号线。
可选地，所述驱动控制模块包括第七晶体管，所述第七晶体管的控制极电连接所述栅极驱动信号线，所述第七晶体管的第一极电连接所述第三节点，所述第七晶体管的第二极电连接所述数据信号线。
可选地，所述双栅型第一晶体管、所述第二晶体管、所述双栅型第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管均为P型薄膜晶体管。
可选地，所述双栅型第一晶体管、所述第二晶体管、所述双栅型第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管均为P型低温多晶硅薄膜晶体管。
可选地，所述双栅型第一晶体管和所述第二晶体管为N型氧化物薄膜晶体管，所述双栅型第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管均为P型低温多晶硅薄膜晶体管。
可选地，所述发光二极管为有机发光二极管或者微型发光二极管。
另一方面，提供了一种显示面板，包括上述所述的像素驱动电路。
可选地，所述显示面板为有机发光二极管显示面板、Micro LED显示面板或Mini LED显示面板。
再一方面，提供了一种控制方法，用于控制上述所述的像素驱动电路，双栅型第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管均为P型薄膜晶体管，所述方法包括：
在第一时段，向发光控制信号线输入具有第一电平的发光控制信号，向栅极驱动信号线输入具有所述第一电平的栅极驱动信号，向复位信号线输入第一复位信号以使双栅型第一晶体管和第二晶体管打开，向数据信号线输入具有所述第一电平的数据信号，向电压信号线输入具有所述第一电平的电压信号，向初始信号线输入具有所述第二电平的电压信号；
在第二时段，向所述发光控制信号线输入具有所述第一电平的所述发光控制信号，向所述栅极驱动信号线输入具有所述第二电平的所述栅极驱动信号，向所述复位信号线输入第二复位信号以使所述双栅型第一晶体管和所述第二晶体管关闭，向所述数据信号线输入具有所述第一电平的所述数据信号，向所述电压信号线输入具有所述第一电平的所述电压信号，向所述初始信号 线输入具有所述第二电平的所述电压信号；
在第三时段，向所述发光控制信号线输入具有所述第二电平的所述发光控制信号，向所述栅极驱动信号线输入具有所述第一电平的所述栅极驱动信号，向所述复位信号线输入所述第二复位信号以使所述双栅型第一晶体管和所述第二晶体管关闭，向所述数据信号线输入具有所述第一电平的所述数据信号，向所述电压信号线输入具有所述第一电平的所述电压信号，向所述初始信号线输入具有所述第二电平的所述电压信号；
其中，所述第一电平的电压值大于所述第二电平的电压值。
可选地，在所述双栅型第一晶体管、所述第二晶体管均为P型薄膜晶体管时，所述第一复位信号为具有所述第二电平的复位信号，所述第二复位信号为具有所述第一电平的复位信号，所述方法还包括：
在第一时段，向复位信号线输入具有第二电平的复位信号；
在第二时段，向所述复位信号线输入具有所述第一电平的所述复位信号；
在第三时段，向所述复位信号线输入具有所述第一电平的所述复位信号。
可选地，在所述双栅型第一晶体管、所述第二晶体管均为N型薄膜晶体管时，所述第一复位信号为具有所述第一电平的复位信号，所述第二复位信号为具有所述第二电平的复位信号，所述方法还包括：
在第一时段，向复位信号线输入具有第一电平的复位信号；
在第二时段，向所述复位信号线输入具有所述第二电平的所述复位信号；
在第三时段，向所述复位信号线输入具有所述第二电平的所述复位信号。
本公开提供了一种计算处理设备，包括：
存储器，其中存储有计算机可读代码；以及
一个或多个处理器，当所述计算机可读代码被所述一个或多个处理器执行时，所述计算处理设备执行上述的控制方法。
本公开提供了一种计算机程序，包括计算机可读代码，当所述计算机可读代码在计算处理设备上运行时，导致所述计算处理设备执行上述的控制方法。
本公开提供了一种计算机可读介质，其中存储了上述的计算机程序。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它 目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图简述
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种像素驱动电路的电路图；
图2为本公开实施例提供的一种像素驱动电路的信号时序图；
图3为相关技术中的像素驱动电路图；
图4为本公开实施例提供的像素驱动电路图；
图5示意性地示出了用于执行根据本公开的方法的计算处理设备的框图；并且
图6示意性地示出了用于保持或者携带实现根据本公开的方法的程序代码的存储单元。
详细描述
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的实施例中，采用“第一”、“第二”……“第七”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本公开实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
在本公开的实施例中，将晶体管的栅极称为控制极，将源极和漏极中的一个称为第一极、另一个称为第二极。本公开实施例中，以所有晶体管的第一极称为漏极，第二极称为源极为例进行说明。
一种像素驱动电路，用于驱动发光二极管发光，该像素驱动电路包括：
双栅型第一晶体管、第二晶体管；其中，双栅型第一晶体管的第一极电 连接初始信号线、第二极电连接第一节点、两个栅极电连接复位信号线；第二晶体管的第一极电连接初始信号线、第二极电连接发光二极管的阳极、栅极电连接栅极驱动信号线。
双栅型第三晶体管、第四晶体管和存储电容；其中，双栅型第三晶体管的两个控制极均电连接栅极驱动信号线、第一极电连接第一节点、第二极电连接到第二节点；第四晶体管的控制极电连接第一节点、第一极电连接到第二节点、第二极电连接第三节点；存储电容的第一端电连接电压信号线、第二端电连接第一节点。
第五晶体管和第六晶体管；其中，第六晶体管的控制极电连接发光控制信号线、第一极电连接第三节点、第二极电连接电压信号线；第五晶体管的控制极电连接发光控制信号线、第一极电连接阳极、第二极电连接第二节点。
第七晶体管；其中第七晶体管的控制极电连接栅极驱动信号线、第一极电连接第三节点、第二极电连接数据信号线。
上述像素驱动电路可以用于驱动发光二极管发光。但是，包括上述像素驱动电路的显示面板用于低频显示时，发光二极管的阳极电压较高，阳极、第二晶体管和初始信号线容易形成漏电通路，即发生漏电现象，且漏电量会随低频时间加长而增大，从而严重影响显示效果。
在上文的基础上，本公开提供了一种像素驱动电路，用于驱动发光二极管发光，参考图1所示，该像素驱动电路包括：复位模块5；
复位模块5包括：双栅型第一晶体管T1、第二晶体管T2；双栅型第一晶体管T1的第一极电连接初始信号线Vint，双栅型第一晶体管T1的第二极电连接第一节点n1；第二晶体管T2的第一极电连接双栅型第一晶体管T1的中间节点n5，第二晶体管T2的第二极电连接阳极；双栅型第一晶体管T1的两个控制极、第二晶体管T2的控制极均电连接复位信号线Reset；复位模块5用于在复位信号线Reset的复位信号的控制下，使用初始信号线Vint的初始信号对第一节点n1和发光二极管6的阳极进行复位；
其中，第二晶体管T2与双栅型第一晶体管T1的一部分组成双栅型晶体管。
可选地，还包括：驱动模块1，电连接所述第一节点n1、第二节点n2和第三节点n3，被配置为在第一节点n1的电压的控制下将第二节点n2和第三 节点n3之间的路径导通，并使路径中产生用于使发光二极管6发光的电流。
可选地，还包括：第一发光控制模块2和第二发光控制模块3，第一发光控制模块2电连接发光控制信号线EM、第二节点n2和发光二极管6的阳极，第二发光控制模块3电连接发光控制信号线EM、电压信号线VDD和第三节点n3，第一发光控制模块2和第二发光控制模块3分别被配置为在发光控制信号线EM的发光控制信号的控制下，将用于使发光二极管6发光的电流传输至阳极。
可选地，还包括：驱动控制模块4，电连接栅极驱动信号线Gate、数据信号线Vdata和第三节点n3，被配置为在栅极驱动信号线Gate的栅极驱动信号的控制下，将数据信号线Vdata的数据信号写入第三节点n3。
上述驱动模块、第一发光控制模块、第二发光控制模块、驱动控制模块包括的具体电路结构不做限定，只要满足相应功能即可。
参考图1所示，上述双栅型第一晶体管T1包括两个串联的单栅型晶体管T1a和T1b。第二晶体管T2为单栅型晶体管，与单栅型晶体管T1a可以组成一个新的双栅晶体管T；此时，单栅型晶体管T1a和单栅型晶体管T1b仍然可以组成双栅型第一晶体管T1。
这里对于上述双栅型第一晶体管和第二晶体管的类型不做限定，其可以是薄膜晶体管，或者场效应管等。目前，多采用前者。
这里对于上述双栅型第一晶体管和第二晶体管的尺寸不做限定，示例的，双栅型第一晶体管可以选择宽长比为3um/(3+3)um的管子，此时，第二晶体管与单栅型晶体管T1a组成的双栅型晶体管可选择宽长比为3um/(3+3)um的管子。
上述第一节点、第二节点、第三节点只是为了便于描述电路结构而定义的，第一节点、第二节点、第三节点并不是一个实际的电路单元。
上述第二晶体管T2的第一极称为漏极(D)，第二极称为源极(S)，控制极称为栅极(G)。
参考图1所示，发光二极管6的阴极可以电连接接地端VSS。
这样，将复位模块中的第二晶体管的第一极电连接双栅型第一晶体管的中间节点，双栅型第一晶体管的两个控制极、第二晶体管的控制极均电连接复位信号线，从而使得第二晶体管和双栅型第一晶体管的一部分组成双栅型 晶体管。而双栅型晶体管可以大大降低阳极的漏电量，从而降低阳极漏电对显示效果的影响，进而提高产品质量。
另外，还可以通过增加一个晶体管，来实现第二晶体管的双栅结构，但是这样无疑会增加布图空间。而本公开在不增加管子的前提下，利用共栅的思想，将第二晶体管和双栅型第一晶体管的一部分组成双栅晶体管。
对比图3中实施例的布图和图4中本公开的布图，可以得到：图3中，双栅型的第一晶体管T1中的两个晶体管与第二晶体管T2横向排列；初始信号线Vint设置在双栅型的第一晶体管T1中的两个晶体管的上侧；复位信号线Reset设置为一条、分别与双栅型的第一晶体管T1中的两个晶体管电连接。
图4中，第二晶体管T2连接在晶体管T1a和晶体管T1b的中间，晶体管T1a和晶体管T1b纵向排列；初始信号线Vint设置在复位信号线Reset的下侧；复位信号线Reset设置为两条，一条与晶体管T1a电连接，另一条与晶体管T1b和第二晶体管T2电连接。晶体管T1a和晶体管T1b组成的双栅型晶体管的宽长比范围为(2～4)um/[2+(2～4)]um，第二晶体管T2的宽长比范围为(2～4)um/(2～4)um；第二晶体管与晶体管T1a组成双栅型晶体管。相较于图3，图4中晶体管T1a、晶体管T1b、第二晶体管T2的连接位置和排布位置发生变化，初始信号线Vint和复位信号线Reset相对位置发生变化；初始信号线Vint仅需要与晶体管T1a电连接即可，不需要与第二晶体管T2电连接，从而节省了部分空间；复位信号线Reset的条数虽然增多，但是初始信号线Vint的设置空间减小，两者对冲后，总体上没有增加布图空间。
因此，上述像素驱动电路没有额外增加布图(layout)空间，不会增大现有产品的尺寸，从而可应用于高分辨率(HPPI)的显示面板。
可选地，参考图1所示，上述驱动模块1包括：双栅型第三晶体管T3、第四晶体管T4和存储电容Cst。
其中，双栅型第三晶体管T3的两个控制极均电连接栅极驱动信号线Gate、第一极电连接第一节点n1、第二极电连接到第二节点n2；第四晶体管T4的控制极电连接第一节点n1、第一极电连接到第二节点n2、第二极电连接第三节点n3；存储电容Cst的第一端电连接电压信号线VDD、第二端电连接第一节点n1。需要说明的是，图1中双栅型第三晶体管T3没有绘示出串联的两个单栅型晶体管，而是用一个双栅型晶体管代替。
可选地，参考图1所示，第一发光控制模块2包括第五晶体管T5，第二发光控制模块3包括第六晶体管T6。
其中，第六晶体管T6的控制极电连接发光控制信号线EM、第一极电连接第三节点n3、第二极电连接电压信号线VDD；第五晶体管T5的控制极电连接发光控制信号线EM、第一极电连接阳极、第二极电连接第二节点n2。图1中，第五晶体管T5的第一极和第二晶体管T2的第二极可以电连接第四节点n4，第四节点n4与发光二极管的阳极电连接。
可选地，参考图1所示，驱动控制模块4包括第七晶体管T7，第七晶体管T7的控制极电连接栅极驱动信号线Gate、第一极电连接第三节点n3、第二极电连接数据信号线Vdata。
可选地，上述双栅型第一晶体管、第二晶体管、双栅型第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管均为P型薄膜晶体管。
进一步可选地，双栅型第一晶体管、第二晶体管、双栅型第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管均为P型低温多晶硅薄膜晶体管(Low Temperature Poly-silicon-Thin Film Transistor，LTPS-TFT)。低温多晶硅薄膜晶体管的电子迁移率更高，响应时间短。
可选地，上述双栅型第一晶体管和第二晶体管为N型氧化物薄膜晶体管，双栅型第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管均为P型低温多晶硅薄膜晶体管。
上述氧化物薄膜晶体管可以是铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)薄膜晶体管、氧化铟锡(Indium Tin Oxide，ITO)、氧化铟锌(Indium Zinc Oxide，IZO)等；实际多采用IGZO薄膜晶体管，其性能较佳。
可选地，上述发光二极管为有机发光二极管(Organic Light-Emitting Diode，OLED)或者微型发光二极管。
这里微型发光二极管包括Mini LED和Micro LED。
需要说明的是，若上述像素驱动电路应用于OLED显示面板，则上述发光二极管为有机发光二极管。若上述像素驱动电路应用于Mini LED显示面板或者Micro LED显示面板，则上述发光二极管为Mini LED或者Micro LED。
本公开实施例提供了一种显示面板，包括上文实施例的像素驱动电路。
上述显示面板可以是柔性显示面板(又称柔性屏)，也可以是刚性显示 面板(即不能折弯的显示面板)，这里不做限定。
上述显示面板可以是有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，还可以是Micro LED显示面板或者Mini LED显示面板，以及包括这些显示面板的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
上述显示面板具有阳极漏电量小、显示效果好、产品质量高的特点。
本公开实施例提供了一种控制方法，用于控制图1所示的像素驱动电路。需要说明的是，该控制方法可以适用于双栅型第一晶体管和第二晶体管均为P型薄膜晶体管或均为N型薄膜晶体管，且双栅型第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管均为P型薄膜晶体管，第一电平为高电平，第二电平为低电平的情况。
在双栅型第一晶体管、第二晶体管、双栅型第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管均为P型薄膜晶体管的情况下，该控制方法包括：
S01、参考图2所示，在第一时段t1，向发光控制信号线EM输入具有第一电平的发光控制信号，向栅极驱动信号线Gate输入具有第一电平的栅极驱动信号，向复位信号线Reset输入具有第二电平的复位信号，向数据信号线Vdata输入具有第一电平的数据信号，向电压信号线VDD输入具有第一电平的电压信号，向初始信号线Vint输入具有第二电平的电压信号。
在第一时段t1，双栅型第一晶体管和第二晶体管打开，初始信号线Vint的电位复位第四晶体管T4的栅极与发光二极管的阳极；由于初始信号线输入的是低电平，第四晶体管T4的栅极复位为低电平，而P型薄膜晶体管是低电平导通，因此第四晶体管T4打开；双栅型第三晶体管、第五晶体管、第六晶体管和第七晶体管关闭。此阶段可称为初始化阶段。
S02、参考图2所示，在第二时段t2，向发光控制信号线EM输入具有第一电平的发光控制信号，向栅极驱动信号线Gate输入具有第二电平的栅极驱动信号，向复位信号线Reset输入具有第一电平的复位信号，向数据信号线Vdata输入具有第一电平的数据信号，向电压信号线VDD输入具有第一电平的电压信号，向初始信号线Vint输入具有第二电平的电压信号。
在第二时段t2，双栅型第三晶体管、第七晶体管打开，第四晶体管T4的 栅极写入Vdata+Vth电压后关闭，此时第一节点n1的电压也为Vdata+Vth，其中，Vth为第四晶体管的阈值电压；双栅型第一晶体管、第二晶体管、第五晶体管、第六晶体管关闭。此阶段可称为补偿阶段。
S03、参考图2所示，在第三时段t3，向发光控制信号线EM输入具有第二电平的发光控制信号，向栅极驱动信号线Gate输入具有第一电平的栅极驱动信号，向复位信号线Reset输入具有第一电平的复位信号，向数据信号线Vdata输入具有第一电平的数据信号，向电压信号线VDD输入具有第一电平的电压信号，向初始信号线Vint输入具有第二电平的电压信号。其中，第一电平的电压值大于第二电平的电压值。
在第三时段t3，第四晶体管、第五晶体管、第六晶体管打开，双栅型第一晶体管、第二晶体管、双栅型第三晶体管、第七晶体管关闭。此时，电压信号线VDD输入的电流流入发光二极管的阳极，从而驱动发光二极管发光。此阶段可称为发光阶段。
上述数据信号线只要保证在第二时段t2中为高电平即可，在其余两个时段不做要求，上述控制方法和图4以数据信号线在三个时段均为高电平为例进行说明。
需要说明的是，N型薄膜晶体管和P型薄膜晶体管的导通条件不同，前者是栅极高电平导通，后者是栅极低电平导通。因此，针对双栅型第一晶体管、第二晶体管为N型薄膜晶体管，双栅型第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管均为P型薄膜晶体管的像素驱动电路的控制方法，只需在不同时段相应调整双栅型第一晶体管、第二晶体管的栅极输入的复位信号的电平即可。其它与上述控制方法相同，此处不再赘述。
具体地，针对双栅型第一晶体管、第二晶体管为N型薄膜晶体管，双栅型第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管均为P型薄膜晶体管的像素驱动电路，该控制方法对于复位信号的电平调整如下：
在第一时段，向复位信号线输入具有第一电平的复位信号；
在第二时段，向所述复位信号线输入具有所述第二电平的所述复位信号；
在第三时段，向所述复位信号线输入具有所述第二电平的所述复位信号。
这样，也可以实现控制像素驱动电路中的发光二极管发光。
本公开的实施例提供了一种控制方法，通过该控制方法，可以实现像素 驱动电路驱动发光二极管发光；该控制方法简单易实现。
本公开的各个部件实施例可以以硬件实现，或者以在一个或者多个处理器上运行的软件模块实现，或者以它们的组合实现。本领域的技术人员应当理解，可以在实践中使用微处理器或者数字信号处理器(DSP)来实现根据本公开实施例的计算处理设备中的一些或者全部部件的一些或者全部功能。本公开还可以实现为用于执行这里所描述的方法的一部分或者全部的设备或者装置程序(例如，计算机程序和计算机程序产品)。这样的实现本公开的程序可以存储在计算机可读介质上，或者可以具有一个或者多个信号的形式。这样的信号可以从因特网网站上下载得到，或者在载体信号上提供，或者以任何其他形式提供。
例如，图5示出了可以实现根据本公开的方法的计算处理设备。该计算处理设备传统上包括处理器1010和以存储器1020形式的计算机程序产品或者计算机可读介质。存储器1020可以是诸如闪存、EEPROM(电可擦除可编程只读存储器)、EPROM、硬盘或者ROM之类的电子存储器。存储器1020具有用于执行上述方法中的任何方法步骤的程序代码1031的存储空间1030。例如，用于程序代码的存储空间1030可以包括分别用于实现上面的方法中的各种步骤的各个程序代码1031。这些程序代码可以从一个或者多个计算机程序产品中读出或者写入到这一个或者多个计算机程序产品中。这些计算机程序产品包括诸如硬盘，紧致盘(CD)、存储卡或者软盘之类的程序代码载体。这样的计算机程序产品通常为如参考图6所述的便携式或者固定存储单元。该存储单元可以具有与图5的计算处理设备中的存储器1020类似布置的存储段、存储空间等。程序代码可以例如以适当形式进行压缩。通常，存储单元包括计算机可读代码1031’，即可以由例如诸如1010之类的处理器读取的代码，这些代码当由计算处理设备运行时，导致该计算处理设备执行上面所描述的方法中的各个步骤。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本公开的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本 公开的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本公开可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种像素驱动电路，用于驱动发光二极管发光，其中，包括：复位模块；所述复位模块包括：双栅型第一晶体管、第二晶体管；
    所述双栅型第一晶体管的第一极电连接初始信号线，所述双栅型第一晶体管的第二极电连接第一节点；所述第二晶体管的第一极电连接所述双栅型第一晶体管的中间节点，所述第二晶体管的第二极电连接所述发光二极管的阳极；
    所述双栅型第一晶体管的两个控制极、所述第二晶体管的控制极均电连接复位信号线；所述复位模块用于在所述复位信号线的复位信号的控制下，使用所述初始信号线的初始信号对所述第一节点和所述发光二极管的所述阳极进行复位；
    其中，所述第二晶体管与所述双栅型第一晶体管的一部分组成双栅型晶体管。
  2. 根据权利要求1所述的像素驱动电路，其中，还包括：
    驱动模块，电连接所述第一节点、第二节点和第三节点，被配置为在所述第一节点的电压的控制下将所述第二节点和所述第三节点之间的路径导通，并使所述路径中产生用于使所述发光二极管发光的电流。
  3. 根据权利要求2所述的像素驱动电路，其中，还包括：第一发光控制模块和第二发光控制模块；
    所述第一发光控制模块电连接发光控制信号线、所述第二节点和所述阳极，所述第二发光控制模块电连接所述发光控制信号线、电压信号线和所述第三节点；
    所述第一发光控制模块和所述第二发光控制模块分别被配置为在所述发光控制信号线的发光控制信号的控制下，将所述用于使所述发光二极管发光的电流传输至所述阳极。
  4. 根据权利要求3所述的像素驱动电路，其中，还包括：
    驱动控制模块，电连接栅极驱动信号线、数据信号线和所述第三节点，被配置为在所述栅极驱动信号线的栅极驱动信号的控制下，将所述数据信号线的数据信号写入所述第三节点。
  5. 根据权利要求4所述的像素驱动电路，其中，所述驱动模块包括：双 栅型第三晶体管、第四晶体管和存储电容；
    其中，所述双栅型第三晶体管的两个控制极均电连接所述栅极驱动信号线，所述双栅型第三晶体管的第一极电连接所述第一节点，所述双栅型第三晶体管的第二极电连接到所述第二节点；所述第四晶体管的控制极电连接所述第一节点，所述第四晶体管的第一极电连接到所述第二节点，所述第四晶体管的第二极电连接所述第三节点；所述存储电容的第一端电连接所述电压信号线，所述存储电容的第二端电连接所述第一节点。
  6. 根据权利要求5所述的像素驱动电路，其中，所述第一发光控制模块包括第五晶体管；
    其中，所述第五晶体管的控制极电连接所述发光控制信号线，所述第五晶体管的第一极电连接所述阳极，所述第五晶体管的第二极电连接所述第二节点。
  7. 根据权利要求6所述的像素驱动电路，其中，所述第二发光控制模块包括第六晶体管；
    所述第六晶体管的控制极电连接所述发光控制信号线，所述第六晶体管的第一极电连接所述第三节点，所述第六晶体管的第二极电连接所述电压信号线。
  8. 根据权利要求7所述的像素驱动电路，其中，所述驱动控制模块包括第七晶体管，所述第七晶体管的控制极电连接所述栅极驱动信号线，所述第七晶体管的第一极电连接所述第三节点，所述第七晶体管的第二极电连接所述数据信号线。
  9. 根据权利要求8所述的像素驱动电路，其中，所述双栅型第一晶体管、所述第二晶体管、所述双栅型第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管均为P型薄膜晶体管。
  10. 根据权利要求9所述的像素驱动电路，其中，所述双栅型第一晶体管、所述第二晶体管、所述双栅型第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管均为P型低温多晶硅薄膜晶体管。
  11. 根据权利要求8所述的像素驱动电路，其中，所述双栅型第一晶体管和所述第二晶体管为N型氧化物薄膜晶体管，所述双栅型第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管和所述第七晶体管均为P 型低温多晶硅薄膜晶体管。
  12. 根据权利要求1-11任一项所述的像素驱动电路，其中，所述发光二极管为有机发光二极管或者微型发光二极管。
  13. 一种显示面板，其中，包括权利要求1-12任一项所述的像素驱动电路。
  14. 根据权利要求13所述的显示面板，其中，所述显示面板为有机发光二极管显示面板、Micro LED显示面板或Mini LED显示面板。
  15. 一种控制方法，用于控制如权利要求8所述的像素驱动电路，其中，双栅型第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管均为P型薄膜晶体管，所述方法包括：
    在第一时段，向发光控制信号线输入具有第一电平的发光控制信号，向栅极驱动信号线输入具有所述第一电平的栅极驱动信号，向复位信号线输入第一复位信号以使双栅型第一晶体管和第二晶体管打开，向数据信号线输入具有所述第一电平的数据信号，向电压信号线输入具有所述第一电平的电压信号，向初始信号线输入具有所述第二电平的电压信号；
    在第二时段，向所述发光控制信号线输入具有所述第一电平的所述发光控制信号，向所述栅极驱动信号线输入具有所述第二电平的所述栅极驱动信号，向所述复位信号线输入第二复位信号以使所述双栅型第一晶体管和所述第二晶体管关闭，向所述数据信号线输入具有所述第一电平的所述数据信号，向所述电压信号线输入具有所述第一电平的所述电压信号，向所述初始信号线输入具有所述第二电平的所述电压信号；
    在第三时段，向所述发光控制信号线输入具有所述第二电平的所述发光控制信号，向所述栅极驱动信号线输入具有所述第一电平的所述栅极驱动信号，向所述复位信号线输入所述第二复位信号以使所述双栅型第一晶体管和所述第二晶体管关闭，向所述数据信号线输入具有所述第一电平的所述数据信号，向所述电压信号线输入具有所述第一电平的所述电压信号，向所述初始信号线输入具有所述第二电平的所述电压信号；
    其中，所述第一电平的电压值大于所述第二电平的电压值。
  16. 根据权利要求15所述的控制方法，其中，在所述双栅型第一晶体管、所述第二晶体管均为P型薄膜晶体管时，所述第一复位信号为具有所述第二 电平的复位信号，所述第二复位信号为具有所述第一电平的复位信号，所述方法还包括：
    在第一时段，向复位信号线输入具有所述第二电平的复位信号；
    在第二时段，向所述复位信号线输入具有所述第一电平的所述复位信号；
    在第三时段，向所述复位信号线输入具有所述第一电平的所述复位信号。
  17. 根据权利要求15所述的控制方法，其中，在所述双栅型第一晶体管、所述第二晶体管均为N型薄膜晶体管时，所述第一复位信号为具有所述第一电平的复位信号，所述第二复位信号为具有所述第二电平的复位信号，所述方法还包括：
    在第一时段，向复位信号线输入具有第一电平的复位信号；
    在第二时段，向所述复位信号线输入具有所述第二电平的所述复位信号；
    在第三时段，向所述复位信号线输入具有所述第二电平的所述复位信号。
  18. 一种计算处理设备，其中，包括：
    存储器，其中存储有计算机可读代码；以及
    一个或多个处理器，当所述计算机可读代码被所述一个或多个处理器执行时，所述计算处理设备执行如权利要求15至17任一项所述的控制方法。
  19. 一种计算机程序，包括计算机可读代码，当所述计算机可读代码在计算处理设备上运行时，导致所述计算处理设备执行根据权利要求15至17任一项所述的控制方法。
  20. 一种计算机可读介质，其中存储了如权利要求19所述的计算机程序。
PCT/CN2021/077905 2020-03-02 2021-02-25 像素驱动电路及其控制方法、显示面板 WO2021175150A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/432,467 US20230360599A1 (en) 2020-03-02 2021-02-25 Pixel drive circuit, control method thereof and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010136752.6A CN111199709A (zh) 2020-03-02 2020-03-02 一种像素驱动电路及其控制方法、显示面板
CN202010136752.6 2020-03-02

Publications (1)

Publication Number Publication Date
WO2021175150A1 true WO2021175150A1 (zh) 2021-09-10

Family

ID=70746619

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/077905 WO2021175150A1 (zh) 2020-03-02 2021-02-25 像素驱动电路及其控制方法、显示面板

Country Status (3)

Country Link
US (1) US20230360599A1 (zh)
CN (1) CN111199709A (zh)
WO (1) WO2021175150A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114038427A (zh) * 2021-11-08 2022-02-11 维信诺科技股份有限公司 像素电路和显示面板

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111199709A (zh) * 2020-03-02 2020-05-26 京东方科技集团股份有限公司 一种像素驱动电路及其控制方法、显示面板
CN114830222B (zh) * 2020-10-27 2024-04-16 京东方科技集团股份有限公司 显示面板及其驱动方法和显示装置
GB2614684A (en) * 2021-04-01 2023-07-12 Boe Technology Group Co Ltd Pixel driving circuit, driving method therefor, and display panel
US12190820B2 (en) 2021-04-26 2025-01-07 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel circuit, pixel driving method and display device
CN114495802B (zh) * 2022-03-22 2024-03-08 京东方科技集团股份有限公司 像素驱动电路、驱动方法及显示面板
CN115101022A (zh) * 2022-06-30 2022-09-23 厦门天马显示科技有限公司 一种像素驱动电路、显示面板及显示装置
DE112023000098T5 (de) * 2023-05-08 2025-03-06 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Anzeigepanel und anzeigeendgerät

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867446A (zh) * 2014-02-25 2015-08-26 三星显示有限公司 有机发光显示设备
CN205722744U (zh) * 2016-03-10 2016-11-23 信利（惠州）智能显示有限公司 一种oled像素驱动电路
CN107342040A (zh) * 2016-04-29 2017-11-10 三星显示有限公司 显示装置
CN107369690A (zh) * 2016-05-11 2017-11-21 三星显示有限公司 显示装置
CN107452772A (zh) * 2016-05-31 2017-12-08 三星显示有限公司 有机发光显示设备
CN108470538A (zh) * 2018-05-31 2018-08-31 昆山国显光电有限公司 像素电路及其驱动方法
US20190081090A1 (en) * 2017-09-08 2019-03-14 Samsung Display Co., Ltd. Display device
US20190206320A1 (en) * 2018-01-02 2019-07-04 Samsung Display Co., Ltd. Pixel of organic light emitting display device and organic light emitting display device having the same
CN110033734A (zh) * 2019-04-25 2019-07-19 京东方科技集团股份有限公司 一种显示驱动电路及其驱动方法、显示装置
US20190288052A1 (en) * 2016-05-16 2019-09-19 Samsung Display Co., Ltd. Display device
CN110349997A (zh) * 2018-04-03 2019-10-18 三星显示有限公司 有机发光二极管显示器
CN110648629A (zh) * 2019-10-31 2020-01-03 厦门天马微电子有限公司 显示面板及其制作方法、显示装置
CN111199709A (zh) * 2020-03-02 2020-05-26 京东方科技集团股份有限公司 一种像素驱动电路及其控制方法、显示面板

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10157572B2 (en) * 2016-11-01 2018-12-18 Innolux Corporation Pixel driver circuitry for a display device
KR102676492B1 (ko) * 2016-11-30 2024-06-18 엘지디스플레이 주식회사 박막 트랜지스터 및 이를 이용한 표시패널
CN106710529B (zh) * 2016-12-19 2019-02-05 上海天马有机发光显示技术有限公司 一种像素驱动电路、驱动方法及有机发光显示面板
CN107316606B (zh) * 2017-07-31 2019-06-28 上海天马有机发光显示技术有限公司 一种像素电路、其驱动方法显示面板及显示装置
CN107591124B (zh) * 2017-09-29 2019-10-01 上海天马微电子有限公司 像素补偿电路、有机发光显示面板及有机发光显示装置
KR102497286B1 (ko) * 2018-07-09 2023-02-08 삼성디스플레이 주식회사 디스플레이 장치
KR102643466B1 (ko) * 2018-11-21 2024-03-05 삼성디스플레이 주식회사 유기 발광 표시 장치
CN110599964A (zh) * 2019-06-26 2019-12-20 合肥维信诺科技有限公司 像素驱动电路及显示装置
CN110648631A (zh) * 2019-09-30 2020-01-03 昆山国显光电有限公司 像素电路、方法、显示面板及装置
CN110610684B (zh) * 2019-10-29 2021-03-30 厦门天马微电子有限公司 一种有机电致发光显示面板及显示装置
CN111091783B (zh) * 2019-12-24 2022-02-15 武汉天马微电子有限公司 有机发光显示面板和显示装置

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867446A (zh) * 2014-02-25 2015-08-26 三星显示有限公司 有机发光显示设备
CN205722744U (zh) * 2016-03-10 2016-11-23 信利（惠州）智能显示有限公司 一种oled像素驱动电路
CN107342040A (zh) * 2016-04-29 2017-11-10 三星显示有限公司 显示装置
CN107369690A (zh) * 2016-05-11 2017-11-21 三星显示有限公司 显示装置
US20190288052A1 (en) * 2016-05-16 2019-09-19 Samsung Display Co., Ltd. Display device
CN107452772A (zh) * 2016-05-31 2017-12-08 三星显示有限公司 有机发光显示设备
US20190081090A1 (en) * 2017-09-08 2019-03-14 Samsung Display Co., Ltd. Display device
US20190206320A1 (en) * 2018-01-02 2019-07-04 Samsung Display Co., Ltd. Pixel of organic light emitting display device and organic light emitting display device having the same
CN110349997A (zh) * 2018-04-03 2019-10-18 三星显示有限公司 有机发光二极管显示器
CN108470538A (zh) * 2018-05-31 2018-08-31 昆山国显光电有限公司 像素电路及其驱动方法
CN110033734A (zh) * 2019-04-25 2019-07-19 京东方科技集团股份有限公司 一种显示驱动电路及其驱动方法、显示装置
CN110648629A (zh) * 2019-10-31 2020-01-03 厦门天马微电子有限公司 显示面板及其制作方法、显示装置
CN111199709A (zh) * 2020-03-02 2020-05-26 京东方科技集团股份有限公司 一种像素驱动电路及其控制方法、显示面板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114038427A (zh) * 2021-11-08 2022-02-11 维信诺科技股份有限公司 像素电路和显示面板
CN114038427B (zh) * 2021-11-08 2024-03-29 维信诺科技股份有限公司 显示面板

Also Published As

Publication number Publication date
US20230360599A1 (en) 2023-11-09
CN111199709A (zh) 2020-05-26

Similar Documents

Publication Publication Date Title
WO2021175150A1 (zh) 像素驱动电路及其控制方法、显示面板
CN110648629B (zh) 显示面板及其制作方法、显示装置
US11972732B2 (en) Pixel circuit, shift register unit, gate driving circuit and display device
WO2019237735A1 (zh) 像素电路及其驱动方法、显示面板和显示装置
CN109785797B (zh) 一种amoled像素电路
CN104318894B (zh) 一种像素电路的驱动方法
US9449554B2 (en) Pixel driving circuit and driving method thereof, display apparatus
WO2015180354A1 (zh) 像素电路、像素电路的驱动方法和显示装置
US9030388B2 (en) Pixel circuit and driving method thereof
WO2019184266A1 (zh) Amoled像素驱动电路、驱动方法及终端
CN111179854A (zh) 像素驱动电路及其驱动方法、显示装置
WO2020211688A1 (zh) 像素驱动电路及方法、显示面板
WO2016150232A1 (zh) 像素电路及其驱动方法、显示装置
WO2019242557A1 (zh) 像素电路及显示装置
WO2019223410A1 (zh) 像素电路及其驱动方法、显示面板、制作方法和显示装置
WO2022061852A1 (zh) 像素驱动电路及显示面板
CN111540315A (zh) 像素驱动电路及其驱动方法、显示装置
CN106067291A (zh) 一种像素驱动电路及其驱动方法、显示装置
CN104882099B (zh) 一种像素驱动电路、阵列基板和显示装置
CN108597444B (zh) 一种硅基oled像素电路及其补偿oled电学特性变化的方法
WO2023005597A1 (zh) 像素驱动电路及显示面板
US11651735B2 (en) Pixel circuit and drive method thereof, and display panel
US20210193046A1 (en) Pixel unit, display panel and electronic device
CN113851082B (zh) 像素驱动电路及其驱动方法、显示面板
WO2022022146A1 (zh) 像素电路及其驱动方法、显示基板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21763978

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21763978

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 21763978

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 28.04.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21763978

Country of ref document: EP

Kind code of ref document: A1