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WO2019237735A1 - 像素电路及其驱动方法、显示面板和显示装置 - Google Patents

像素电路及其驱动方法、显示面板和显示装置 Download PDF

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Publication number
WO2019237735A1
WO2019237735A1 PCT/CN2019/071655 CN2019071655W WO2019237735A1 WO 2019237735 A1 WO2019237735 A1 WO 2019237735A1 CN 2019071655 W CN2019071655 W CN 2019071655W WO 2019237735 A1 WO2019237735 A1 WO 2019237735A1
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Prior art keywords
terminal
light
module
control signal
pixel circuit
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Application number
PCT/CN2019/071655
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English (en)
French (fr)
Inventor
高雪岭
羊振中
王铁石
彭锦涛
Original Assignee
京东方科技集团股份有限公司
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Priority to US16/486,201 priority Critical patent/US11869423B2/en
Publication of WO2019237735A1 publication Critical patent/WO2019237735A1/zh
Priority to US18/534,793 priority patent/US12223903B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
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    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit and a driving method thereof, a display panel, and a display device.
  • the threshold voltage of the driving transistor in each pixel unit may be different from each other due to the manufacturing process, and due to, for example, the influence of temperature changes, the threshold voltage of the driving transistor may also drift. . Therefore, the difference in the threshold voltage of each driving transistor may also cause defects such as uneven display of the display panel and inconsistent light emission brightness of the light emitting device.
  • a pixel circuit in a display is generally composed of a low temperature polysilicon thin film transistor (LTPS TFT), and the LTPS TFT has a leakage current (I off ) when it is in an off state, and the leakage current is not gentle.
  • LTPS TFT low temperature polysilicon thin film transistor
  • I off leakage current
  • tail lift phenomenon which makes it impossible to effectively lock the voltage written to the driving transistor during a frame display.
  • a first aspect of the present disclosure proposes a pixel circuit, which may include a data signal writing module, a driving module, a threshold compensation transistor, a first power supply voltage writing module, and a light emitting module.
  • the driving module includes a driving transistor, a first power voltage writing module, which is connected to a first light emitting control signal terminal, a first power voltage terminal, a source of the driving transistor and a gate thereof, and is configured to be connected to the first
  • a light-emitting control signal terminal writes a first power-supply voltage signal of the first power-supply voltage terminal to a source of a driving transistor under the control of a first light-emitting control signal terminal;
  • a data signal writing module which is The source of the driving transistor is connected, and is configured to pass the data signal of the data signal terminal to the source of the driving transistor under the control of the write control signal of the writing control terminal; the threshold compensation transistor, the gate of which is connected to the first The nodes are connected, the source is connected to the gate of
  • the threshold compensation transistor may be an oxide transistor.
  • the pixel circuit further includes: a reference signal writing module, which is connected to the reference control terminal, the reference signal terminal, the first light-emitting control signal terminal, and the first node, and is configured to control according to the reference control terminal's reference control.
  • the signal and the first light emission control signal at the first light emission control signal terminal control the potential of the first node.
  • the pixel circuit further includes: a reset module, which is connected to the reset control terminal, the reset potential terminal, and the first terminal of the light emitting module, and is configured to control the reset control signal under the control of the reset control signal of the reset control terminal.
  • the first terminal of the light emitting module and the gate of the driving transistor are reset.
  • the pixel circuit further includes: a light emitting control module, which is connected to a second light emitting control signal terminal, a drain of the driving transistor, and a first terminal of the light emitting module, and is configured to control the second light emitting control.
  • the light emitting module is driven to emit light under the control of the second light emitting control signal at the signal end.
  • the reference signal writing module includes a reference signal writing transistor, a gate of which is connected to a reference control terminal, a source of which is connected to a first node, and a drain of which is connected to the reference signal terminal; and a first capacitor , Connected between the first light-emitting control signal end and the first node.
  • the data signal writing module includes a data writing transistor, a gate of which is connected to the data writing control terminal, a source of which is connected to the data signal terminal, and a drain of which is connected to the source of the driving transistor.
  • the first power supply voltage writing module includes: a first power supply voltage writing transistor, a gate of which is connected to a first light emitting control signal terminal, a source of which is connected to the first power supply voltage terminal, and a drain of which is connected to a driver The sources of the transistors are connected.
  • the driving module further includes: a second capacitor connected between the first power voltage terminal and the gate of the driving transistor.
  • the light-emitting control module includes a light-emitting control transistor, a gate of which is connected to a second light-emitting control signal terminal, a source of which is connected to a drain of a driving transistor, and a drain of which is connected to a first terminal of the light-emitting module;
  • the light emitting module includes an organic light emitting diode OLED, an anode of the OLED serves as a first end of the light emitting module, and a cathode of the OLED serves as a second end of the light emitting module.
  • OLED organic light emitting diode
  • the reset module includes a reset transistor, a gate of which is connected to the reset control terminal, a source of which is connected to the first terminal of the light emitting module, and a drain of which is connected to the reset potential terminal.
  • the second power voltage at the second power voltage terminal is lower than the reset potential at the reset potential terminal.
  • a method for driving any pixel circuit may include: in a data write and threshold compensation phase, the write control The write control signal at the terminal is at the first level, the data signal at the data signal terminal is written to the source of the driving transistor, and the reference control signal at the reference control terminal transitions from the first level to the second level, and the first emits light
  • the level of the control signal transitions from the first level to the second level, pulls up the level of the first node, and compensates the gate potential of the driving transistor under the control of the first node
  • the second light-emitting control signal at the second light-emitting control signal terminal is at a first level, and the driving current of the driving transistor flows to the light-emitting module to drive the light-emitting module to emit light.
  • the pixel circuit further includes: a reference signal writing module connected to the reference control terminal, the reference signal terminal, the first light-emitting control signal terminal, and the first node; the method further includes: a first initialization stage and In the second initialization phase, in the first initialization phase, the reference control signal of the reference control terminal is at the first level, and the reference signal of the reference signal terminal is passed to the first node; in the second initialization phase, the reference control signal of the reference control terminal is from The first level jumps to a second level, the level of the first light emission control signal jumps from the first level to the second level, and the level of the first node is raised.
  • the pixel circuit further includes: a reset module connected to the reset control terminal, the reset potential terminal, and the first terminal of the light emitting module; in the second initialization phase, the reset control signal of the reset control terminal is at the first One level, transfers the reset potential from the reset potential terminal to the first terminal of the light emitting module and the gate of the driving transistor.
  • the reference signal at the reference signal terminal is adjusted based on the threshold voltage offset of the threshold compensation transistor.
  • the pixel circuit further includes: a light-emitting control module, which is connected to the second light-emitting control signal terminal, the drain of the driving transistor, and the first terminal of the light-emitting module; after the data writing and threshold compensation stages Before the light-emitting phase, the method further includes a pre-light-emitting phase.
  • the pre-light-emitting phase the first light-emitting control signal at the first light-emitting control signal terminal is at a first level, and the first power source is turned on. The first power supply voltage at the voltage terminal is transmitted to the source of the driving transistor.
  • the gate potential of the driving transistor is compensated to the sum of the potential of the data signal and the threshold potential of the driving transistor.
  • the first level is lower than the second level.
  • a display panel including any pixel circuit as described in the first aspect of the present disclosure.
  • a display device including the display panel according to the third aspect of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 shows a specific circuit diagram of the pixel circuit shown in FIG. 1;
  • FIG. 3 shows a flowchart of a method for driving a pixel circuit in the above embodiment
  • FIG. 4 shows an exemplary driving timing diagram of the pixel circuit shown in FIG. 1 or FIG. 2;
  • FIG. 6 is a graph showing a relationship between a current flowing through itself and a gate-source voltage difference Vg obtained by simulation when a different threshold voltage is set for the threshold compensation transistor M1 in the pixel circuit shown in FIG. 2, and Schematic graph of current flowing through an OLED.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the connection mode of the drain and source of each transistor can be interchanged. Therefore, there is practically no difference between the drain and source of each transistor in the embodiments of the present disclosure.
  • one of the poles is called the drain and the other is called the source.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit 100 may include a data signal writing module 110, a driving module 120, a threshold compensation transistor M1, a first power supply voltage writing module 130, and a light emitting module 140.
  • the driving module 120 may include a driving transistor. DTFT.
  • the data signal writing module 110 may be connected to the data writing control terminal Gate (n), the data signal terminal Data (n), and the source of the driving transistor DTFT.
  • the data signal writing module 110 is used for transmitting the data signal Date (n) of the data signal terminal to the source of the driving transistor under the control of the data writing control signal of the data writing control terminal Gate (n).
  • the threshold compensation transistor M1 has a gate connected to the first node N1, a source connected to the gate of the driving transistor DTFT, and a drain connected to the drain of the driving transistor DTFT.
  • the threshold compensation transistor M1 is used to perform voltage compensation on the gate of the driving transistor DTFT when the first node N1 is at an active level.
  • the first power supply voltage writing module 130 is connected to the first light-emitting control signal terminal EM (n), the first power supply voltage terminal ELVDD, and the source of the driving transistor DTFT.
  • the first power supply voltage writing module 130 is configured to write the first power supply voltage signal of the first power supply voltage terminal ELVDD to the driving transistor DTFT under the control of the first light emission control signal of the first light emission control signal terminal EM (n). Source.
  • the light-emitting module 140 has a first terminal connected to the light-emitting control module and a second terminal connected to the second power voltage terminal ELVSS.
  • the turning on of the threshold compensation transistor M1 can make the gate and drain of the driving transistor DTFT communicate with each other, thereby forming a pair of transistors that pass through the drain of the driving transistor DTFT.
  • the voltage of the gate of the driving transistor DTFT is adjusted (for example, reset or compensated).
  • LTPS low temperature polysilicon
  • TFTs thin film transistors
  • the threshold compensation transistor M1 may be, for example, an oxide transistor (Oxide TFT).
  • the Oxide TFT has the following advantages over the LTPS TFT: The current of the Oxide TFT in the off state is relatively small, on the order of 1.0E-13, and the current in the off state is gentle. Therefore, when Oxide TFT is used instead of LTPS TFT for voltage compensation, the leakage current in the pixel circuit is very small, so the problem of inconsistent light emission brightness of the light emitting device in the pixel circuit can be significantly improved.
  • the pixel circuit 100 shown in FIG. 1 may further include a reference signal writing module 150, which is connected to the first node N1 for controlling the potential of the N1 node.
  • the reference signal writing module 150 may also be connected to a reference control terminal Gate (n-2), a reference signal terminal Vref, and a first light emission control signal terminal EM (n).
  • the reference signal writing module 150 is configured to control the potential of the first node N1 according to the reference control signal of the reference control terminal Gate (n-2) and the first light emission control signal of the first light emission control signal terminal EM (n).
  • the pixel circuit 100 shown in FIG. 1 may further include a reset module 160, which may be connected to the reset control terminal Gate (n-1), the reset potential terminal Vint, and the first terminal of the light emitting module.
  • the reset module 160 is configured to reset the first end of the light emitting module under the control of the reset control signal of the reset control terminal Gate (n-1).
  • the pixel circuit 100 shown in FIG. 1 may further include a light emitting control module 170, which may be connected to the second light emitting control signal terminal EM (n + 1), the drain of the driving transistor, and the light emitting module, and it may It is configured to drive the light emitting module to emit light under the control of the second light emission control signal of the second light emission control signal terminal EM (n + 1).
  • a light emitting control module 170 which may be connected to the second light emitting control signal terminal EM (n + 1), the drain of the driving transistor, and the light emitting module, and it may It is configured to drive the light emitting module to emit light under the control of the second light emission control signal of the second light emission control signal terminal EM (n + 1).
  • FIG. 2 shows a specific circuit diagram of the pixel circuit shown in FIG. 1.
  • the reference signal writing module 150 may include a reference signal writing transistor M2 and a first capacitor C1.
  • the gate of the reference signal writing transistor M2 may be connected to the reference control terminal Gate (n-2), the source is connected to the first node N1, and the drain is connected to the reference signal terminal Vref.
  • the reference signal writing transistor M2 is used for transmitting the reference signal of the reference signal terminal Vref to the first node N1 under the control of the reference control signal of the reference control terminal Gate (n-2).
  • the first capacitor C1 may be connected between the first light-emitting control signal terminal EM (n) and the first node N1; the first capacitor C1 is used for a sudden change of the light-emitting control signal at the first light-emitting control signal terminal EM (n). At this time, the voltage at the first node N1 is changed accordingly to maintain a constant voltage difference across the first capacitor C1.
  • the data signal writing module 110 may include a data writing transistor M3.
  • the gate of the data writing transistor M3 is connected to the data writing control terminal Gate (n), the source is connected to the data signal terminal Date (n), and the drain is connected to the source of the driving transistor DTFT.
  • the data writing transistor M3 is used to write the data signal of the data signal terminal Date (n) to the source of the driving transistor DTFT under the control of the write control signal of the write control terminal Gate (n).
  • the driving module 120 may further include a second capacitor C2.
  • the second capacitor C2 is connected between the gate of the driving transistor DTFT and the first power voltage terminal ELVDD.
  • the second capacitor C2 is used to maintain the stability of the gate voltage of the DTFT after the compensation of the threshold voltage of the driving transistor DTFT is completed.
  • the first power supply voltage writing module 130 may include a first power supply voltage writing transistor M4.
  • the gate of the first power supply voltage writing transistor M4 is connected to the first light emitting control signal terminal EM (n), the source is connected to the first power supply voltage terminal ELVDD, and the drain is connected to the source of the driving transistor DTFT.
  • the first power supply voltage writing transistor M4 is used to write the first power supply voltage of the first power supply voltage terminal ELVDD to the gate of the driving transistor DTFT under the control of the first light emission control signal of the first light emission control signal terminal EM (n). pole.
  • the reset module 160 may include a reset transistor M5.
  • the gate of the reset transistor M5 is connected to the reset control terminal Gate (n-1), the source is connected to the first terminal of the light emitting module 140, and the drain is connected to the reset potential terminal Vint.
  • the reset transistor M5 is used to reset the first terminal of the light emitting module 140 and the gate of the driving transistor under the control of the reset control signal of the reset control terminal Gate (n-1).
  • the light emitting module 140 may include a light emitting device, such as an organic light emitting diode (OLED).
  • a light emitting device such as an organic light emitting diode (OLED).
  • OLED organic light emitting diode
  • the anode of the OLED is used as the first end of the light emitting module
  • the cathode of the OLED is used as the second end of the light emitting module.
  • the light emission control module 170 may include a light emission control transistor M6.
  • the gate of the light-emitting control transistor M6 is connected to the second light-emitting control signal terminal EM (n + 1), the source is connected to the drain of the driving transistor DTFT, and the drain is connected to the first terminal of the light-emitting module 140.
  • the light-emitting control transistor M6 is used to transmit the driving current flowing through the driving transistor DTFT to the light-emitting module 140 under the control of the second light-emitting control signal of the second light-emitting control signal terminal EM (n + 1) to drive the light-emitting module 140.
  • the OLED does not emit light
  • the voltage of the reset signal of the potential terminal Vint is lower than the second power voltage of the second power voltage terminal ELVSS.
  • the first power voltage of the first power voltage terminal ELVDD should be higher than the second power voltage of the second power voltage terminal ELVSS.
  • the threshold compensation transistor M1 is an N-type transistor (oxide N-type transistor), and the driving transistor DTFT, the reference signal writing transistor M2, the data writing transistor M3, the first power supply voltage writing transistor M4, and the reset
  • the transistor M5 and the light emission control transistor M6 are both p-type transistors, for example. Based on the description and teaching of this implementation in the present disclosure, those skilled in the art can easily think of the implementation of the embodiments of the present disclosure using N-type transistors or a combination of N-type and P-type transistors without creative work. Therefore, These implementations are also within the protection scope of the present disclosure.
  • FIG. 2 only shows an example circuit structure of a pixel circuit according to an embodiment of the present disclosure, and in fact, each module in the pixel circuit may have various circuit structures, and the present disclosure does not limit this.
  • Embodiments of the present disclosure also provide a method for driving the above-mentioned pixel circuit.
  • a flowchart of a method for driving the pixel circuit in the above-mentioned embodiment is shown in FIG. 3, and an exemplary driving timing chart of the pixel circuit shown in FIG. 1 or FIG. 2 is shown in FIG. 4.
  • 5a-5e show the conduction states of the transistors in the pixel circuit corresponding to the stages T1-T5 in FIG. 3, respectively.
  • the driving method may include a data writing and threshold compensation stage T3 and a light emitting stage T5.
  • the reference control signal of the reference control terminal Gate (n-2) can be set to the second level
  • the reset control signal of the reset control terminal Gate (n-1) can be set to the second level.
  • the reference control signal of the reference control terminal Gate (n-2) can be set to the second level
  • the reset control signal of the reset control terminal Gate (n-1) can be set to the second level
  • the data writing can be set.
  • the data writing control signal of the control terminal Gate (n) is a second level
  • the first light emission control signal of the first light emission control signal EM (n) is set to the first level
  • the second light emission control signal terminal EM (n) is set +1)
  • the second light emission control signal is at a first level
  • the data signal at the data signal terminal Data (n) is set to an invalid data signal.
  • the driving method may further include a first initialization stage T1 and a second initialization stage T2.
  • the reference control signal of the reference control terminal Gate (n-2) can be set to a first level
  • the reset control signal of the reset control terminal Gate (n-1) can be set to a second level.
  • Set the data write control signal of the data write control terminal Gate (n) to the second level set the first light emission control signal of the first light emission control signal EM (n) to the first level
  • set the second light emission control signal The second light-emitting control signal at the terminal EM (n + 1) is a first level
  • the data signal at the data signal terminal Data (n) is set to an invalid data signal.
  • the reference control signal of the reference control terminal Gate (n-2) can be set to the second level
  • the reset control signal of the reset control terminal Gate (n-1) can be set to the first level
  • the data can be set.
  • the data writing control signal of the write control terminal Gate (n) is at a second level
  • the first light emission control signal of the first light emission control signal EM (n) is set to a second level
  • the second light emission control signal terminal EM is set
  • the (n + 1) second light emission control signal is at a first level
  • the data signal at the data signal terminal Data (n) is set to an invalid data signal.
  • the foregoing driving method may include a pre-light-emitting phase T4 after the data writing and threshold compensation phase T3 and before the light-emitting phase T5.
  • the reference control signal of the reference control terminal Gate (n-2) is set to the second level
  • the reset control signal of the reset control terminal Gate (n-1) is set to the second level
  • the data writing is set
  • the data writing control signal to the control terminal Gate (n) is set to the second level
  • the first light emission control signal of the first light emission control signal EM (n) is set to the first level
  • the second light emission control signal terminal EM The second light-emitting control signal of n + 1) is at a second level
  • the data signal of the data signal terminal Data (n) is set to an invalid data signal.
  • the threshold voltage of the threshold compensation transistor is shifted.
  • the threshold compensation transistor is an N-type transistor
  • the threshold voltage of the N-type transistor will shift to a negative direction after it is operated for a period of time.
  • the voltage signal applied to the gate of the threshold compensation transistor needs to be adjusted, that is, the reference signal at the reference signal terminal can be adjusted based on the threshold voltage offset of the threshold compensation transistor .
  • the first level is a low-level VGL and the second level is a high-level VGH.
  • the threshold compensation transistor is an N-type transistor (for example, an oxide N-type transistor), and the other transistors are P-type transistors. Because, the first level (low level) is an effective level for turning on the threshold compensation transistor M1, and the second level (high level) is for turning on other modules or transistors other than the threshold compensation transistor. Active level.
  • each transistor can be configured as a P-type or N-type transistor.
  • the internal connection structure of the pixel circuit needs to be inverted, and Each drive signal is adjusted.
  • Example operations of a pixel circuit according to an embodiment of the present disclosure will be described below with reference to FIGS. 4, 2, and 5a-5e.
  • the reference control signal of the reference control terminal Gate (n-2) is at the first level, and the reference signal writing transistor M2 is turned on, so that the reference signal of the reference signal terminal Gate (n-2) is transferred.
  • the voltage of the first node N1 is the reference signal Vref, and the threshold compensation transistor M1 is turned off.
  • the conduction state of each transistor is shown in FIG. 5a.
  • the reference control signal of the reference control terminal Gate (n-2) transitions from the first level to the second level, so that the reference signal writing transistor M2 is turned off.
  • the first light-emitting control signal of the first light-emitting control signal terminal EM (n) jumps from the first level VGL to the second level VGH, pulls up the level of the first node N1, so that the voltage of the first node N1 Vref + (VGH-VGL).
  • the threshold compensation transistor M1 After the potential of the first node N1 becomes high, the threshold compensation transistor M1 is turned on, and at this time, the reset control signal of the reset control terminal Gate (n) is at the first level, so that the reset transistor M5 is turned on, thereby resetting the potential
  • the reset potential of the terminal Vint is transferred to the anode of the organic light emitting diode OLED via the reset transistor M5, and further transferred to the gate of the driving transistor DTFT via the threshold compensation transistor M1.
  • resetting the anode voltage of the OLED and the gate voltage of the driving transistor DTFT is achieved.
  • the potential of the anode of the OLED and the gate of the driving transistor DTFT are both Vint, and since Vint ⁇ ELVSS, it is ensured that the OLED does not emit light.
  • the conduction state of each transistor is shown in FIG. 5b.
  • Figure 5b also shows the current flow of the pixel circuit at this time, that is, from the reset transistor M5 to the light-emission control transistor M6 to the threshold compensation transistor M1, all the way to the gate of the driving transistor DTFT.
  • the potential of the first node N1 can be maintained at Vref + (VGH-VGL) due to the existence of the first capacitor C1.
  • the reset control signal of the reset control terminal Gate (n-1) transitions from the first level to the second level, and the reset transistor M5 is turned off.
  • the data writing control signal of the data writing control terminal Gate (n) is at the second level, the data signal writing transistor M3 is turned on, and the data signal of the data signal terminal Data (n) is passed to the source of the driving transistor DTFT, The gate voltage of the driving transistor is compensated via the threshold compensation transistor M1.
  • the voltage of the source of the driving transistor DTFT is Vdata
  • the gate voltage of the compensated driving transistor DTFT is Vdata + Vth.
  • the conduction state of each transistor is shown in FIG. 5c.
  • Figure 5c also shows the current flow in the pixel circuit at this time, that is, from the data writing transistor M3 to the source of the driving transistor DTFT to the threshold compensation transistor, all the way to the gate of the driving transistor DTFT.
  • the first light-emission control signal of the first light-emission control signal terminal EM (n) transitions from the second level to the first level, so that the data signal writing transistor M4 is turned on, and the first power voltage terminal The first power supply voltage of ELVDD is transferred to the source of the driving transistor DTFT. And, because EM (n) changes from high to low, the level of the first node N1 is coupled back to Vref from Vref + (VGH-VGL). Due to the existence of the second capacitor C2, the voltage of the gate of the driving transistor DTFT is maintained at Vdata + Vth. In the pre-emission phase T4, the conduction state of each transistor is shown in FIG. 5d.
  • the second light-emitting control signal of the second light-emitting control signal terminal EM (n + 1) becomes the first level
  • the light-emitting control transistor M6 is turned on
  • the first power voltage of the first power voltage terminal ELVDD passes data
  • the driving current generated by the writing transistor M4, the driving transistor DTFT, and the light emitting control transistor M6 flows into the OLED, and drives the OLED to emit light.
  • the conduction state of each transistor is shown in FIG. 5e.
  • FIG. 5e also shows the circuit flow in the driving circuit at this time, that is, from the first power supply voltage writing transistor M4 to the driving transistor DTFT to the light emitting control transistor M6, all the way to the light emitting device OLED.
  • the driving current IOLED satisfies the following saturation current formula:
  • ⁇ n is the channel mobility of the driving transistor
  • Cox is the channel capacitance per unit area of the driving transistor
  • W and L are the channel width and channel length of the driving transistor
  • Vgs is the gate-source voltage of the driving transistor (the driving transistor ’s Gate voltage and source voltage difference).
  • the current flowing through the OLED has nothing to do with the threshold voltage of the driving transistor DTFT. It can be seen that the method for driving a pixel circuit according to the embodiment of the present disclosure better achieves compensation for the threshold voltage of the driving transistor DTFT.
  • the reference signal can be written into the control signal of the control terminal Gate (n-2) into the control signal, the reset control signal of the reset control terminal Gate (n-1), and
  • the data writing control signals of the data writing control end Gate (n) are set to be delayed for a period of time, for example, the outputs of the front and rear stage shift registers in the pixel circuit can be used as the three control signals, respectively.
  • the first light emission control signal of the first light emission control signal terminal EM (n) and the second light emission control signal of the second light emission control signal terminal EM (n + 1) may also be set to be delayed from each other for a period of time.
  • the operation timing of each signal shown in FIG. 4 is only exemplary, and the present disclosure does not limit it.
  • FIG. 6 is a graph showing the relationship between the current flowing through itself and its gate-source voltage difference Vg obtained by simulation when the threshold compensation transistor M1 is set with different threshold voltages in the pixel circuit shown in FIG. 2; and A schematic graph of the current flowing through the OLED during this period.
  • the threshold voltage of the threshold compensation transistor M1 will shift.
  • an oxide N-type transistor is used as the threshold compensation transistor, and a threshold voltage thereof may be shifted in a negative direction. Therefore, for example, simulation software such as SmartSpice can be used to set different threshold voltages for the threshold compensation transistor M1 in the pixel circuit shown in FIG. 2 to obtain the current flowing through the threshold compensation transistor M1 under different threshold voltages.
  • Simulation diagram As shown in the upper diagram of FIG. 6, it is a relationship curve between the current flowing through itself and the gate-source voltage difference Vg obtained by simulation when different threshold voltages are set for the threshold compensation transistor M1. As shown in the upper diagram of FIG.
  • the threshold voltages of the threshold compensation transistor M1 are respectively set to 0V (before offset) and -5V (after offset), thereby obtaining two corresponding current curves.
  • the lower graph of FIG. 6 shows a schematic graph of the current flowing through the OLED during this period. It can be seen from the lower graph of FIG. 6 that under the above-mentioned different threshold voltage settings, the curves of the current flowing through the OLED can be close to coincide. This further illustrates that the pixel circuit according to the embodiment of the present disclosure can better compensate the threshold voltage of the driving transistor, so as to overcome the defect that the light emitting devices of the pixel circuits do not have the same brightness. Moreover, it can also be seen in the upper graph of FIG.
  • the current of the oxide transistor in the off state is relatively small and relatively gentle. Therefore, when an oxide transistor is used as the threshold compensation transistor, it can be ensured that after the data voltage writing to the driving transistor and the threshold voltage compensation are completed, the compensated state after writing the Data data can be maintained more stably.
  • An embodiment of the present disclosure further provides a display panel including a pixel circuit provided by any one of the embodiments of the present disclosure.
  • An embodiment of the present disclosure further provides a display device including the display panel provided above in the present disclosure.
  • the display device may include any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种像素电路、显示面板、显示装置及驱动方法。该像素电路包括数据信号写入模块、驱动模块、阈值补偿晶体管、第一电源电压写入模块、发光模块，其中驱动模块中包含驱动晶体管。该像素电路、显示面板、显示装置及驱动方法，可对驱动晶体管进行阈值电压补偿，提高了驱动电流的均匀性，进而提高了显示面板显示的均匀性，同时减小漏电流，使得发光模块的发光亮度一致。

Description

像素电路及其驱动方法、显示面板和显示装置
相关申请的交叉引用
本申请要求于2018年6月13日提交的中国专利申请号201810608546.3的优先权，该中国专利申请的全文通过引用的方式结合于此以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体地，涉及像素电路及其驱动方法、显示面板、显示装置。
背景技术
在有机发光二极管(OLED)显示面板中，各个像素单元中的驱动晶体管的阈值电压由于制备工艺可能彼此之间存在差异，而且由于例如温度变化的影响，驱动晶体管的阈值电压也会产生漂移的现象。因此，各个驱动晶体管的阈值电压的不同也可能会导致显示面板显示不均匀、发光器件的发光亮度不一致等不良。
并且，当前，显示器(例如，OLED显示器)中的像素电路通常由低温多晶硅薄膜晶体管(LTPS TFT)构成，而LTPS TFT在处于截止状态时存在漏电流(I off)，并且该漏电流并不平缓且存在翘尾现象，使得在一帧显示画面期间，不能有效地锁住写入到驱动晶体管的电压。
发明内容
为了解决上述问题，本公开的第一方面提出了一种像素电路，该像素电路可以包括：数据信号写入模块、驱动模块、阈值补偿晶体管、第一电源电压写入模块、发光模块，其中所述驱动模块中包括驱动晶体管，第一电源电压写入模块，其与第一发光控制信号端、第一电源电压端、驱动晶体管的源极及其栅极相连，并且被配置为在所述第一发光控制信号端的第一发光控制信号的控制下将所述第一电源电压端的第一电源电压信号写入驱动晶体管的源极；数 据信号写入模块，其与写入控制端、数据信号端、驱动晶体管的源极相连，并且被配置为在写入控制端的写入控制信号的控制下将所述数据信号端的数据信号传递到驱动晶体管的源极；阈值补偿晶体管，其栅极与第一节点相连，源极与驱动晶体管的栅极相连，其漏极与驱动晶体管的漏极相连，并且被配置为在第一节点处于有效电平的情况下对驱动晶体管的栅极进行电压补偿；发光模块，其第一端与驱动晶体管的漏极相连，第二端连接到第二电源电压端。
在一个示例中，所述阈值补偿晶体管可以为氧化物晶体管。
在一个示例中，所述像素电路还包括：参考信号写入模块，其与参考控制端、参考信号端、第一发光控制信号端和第一节点相连，并且被配置为根据参考控制端的参考控制信号和第一发光控制信号端的第一发光控制信号来控制第一节点的电位。
在一个示例中，所述像素电路还包括：复位模块，其与复位控制端、复位电位端和发光模块的第一端相连，并且被配置为在复位控制端的复位控制信号的控制下对所述发光模块的第一端和驱动晶体管的栅极进行复位。
在一个示例中，所述像素电路还包括：发光控制模块，其与第二发光控制信号端、驱动晶体管的漏极和发光模块的第一端相连，并且被配置为在所述第二发光控制信号端的第二发光控制信号的控制下驱动所述发光模块发光。
在一个示例中，所述参考信号写入模块包括：参考信号写入晶体管，其栅极与参考控制端相连，源极与第一节点相连，漏极与参考信号端相连；以及，第一电容，连接在第一发光控制信号端和第一节点之间。
在一个示例中，所述数据信号写入模块包括：数据写入晶体管，其栅极与数据写入控制端相连，源极与数据信号端相连，漏极与驱动晶体管的源极相连。
在一个示例中，所述第一电源电压写入模块包括：第一电源电压写入晶体管，其栅极与第一发光控制信号端相连，源极与第一电源电压端相连，漏极与驱动晶体管的源极相连。
在一个示例中，所述驱动模块还包括：第二电容，其连接在第一电源电压端和驱动晶体管的栅极之间。
在一个示例中，所述发光控制模块包括：发光控制晶体管，其栅极与第二 发光控制信号端相连，源极与驱动晶体管的漏极相连，漏极与发光模块的第一端相连；
在一个示例中，所述发光模块包括：有机发光二极管OLED，所述OLED的阳极作为所述发光模块的第一端，所述OLED的阴极作为所述发光模块的第二端。
在一个示例中，所述复位模块包括复位晶体管，其栅极与复位控制端相连，源极与发光模块的第一端相连，漏极与复位电位端相连。
在一个示例中，第二电源电压端的第二电源电压低于复位电位端的复位电位。
本公开的第二方面，提供了一种用于驱动如本公开第一方面所述的任一像素电路的方法，所述方法可以包括：在数据写入及阈值补偿阶段，所述写入控制端的写入控制信号处于第一电平，将所述数据信号端的数据信号写入驱动晶体管的源极，并且参考控制端的参考控制信号从第一电平跳变至第二电平，第一发光控制信号的电平从第一电平跳变至第二电平，拉高所述第一节点的电平，在所述第一节点的控制下，对所述驱动晶体管的栅极电位进行补偿；在发光阶段，所述第二发光控制信号端的第二发光控制信号处于第一电平，所述驱动晶体管的驱动电流流向所述发光模块，驱动所述发光模块发光。
在一个示例中，所述像素电路还包括：参考信号写入模块，与参考控制端、参考信号端、第一发光控制信号端和第一节点相连；所述方法还包括：第一初始化阶段和第二初始化阶段，在第一初始化阶段，参考控制端的参考控制信号处于第一电平，将所述参考信号端的参考信号传递至第一节点；在第二初始化阶段，参考控制端的参考控制信号从第一电平跳变至第二电平，第一发光控制信号的电平从第一电平跳变至第二电平，拉高所述第一节点的电平。
在一个示例中，所述像素电路还包括：复位模块，与复位控制端、复位电位端和发光模块的第一端相连；在所述第二初始化阶段，所述复位控制端的复位控制信号处于第一电平，将复位电位端的复位电位传递至发光模块的第一端和所述驱动晶体管的栅极。
在一个示例中，在所述像素电路工作预设时间后，所述参考信号端的参考信号基于阈值补偿晶体管的阈值电压的偏移而调整。
在一个示例中，所述像素电路还包括：发光控制模块，其与第二发光控制信号端、驱动晶体管的漏极和发光模块的第一端相连；在所述数据写入及阈值补偿阶段后、在所述发光阶段前，所述方法还包括：预发光阶段，在所述预发光阶段，所述第一发光控制信号端的第一发光控制信号处于第一电平，将所述第一电源电压端的第一电源电压传递至所述驱动晶体管的源极。
在一个示例中，在数据写入及阈值补偿阶段，所述驱动晶体管的栅极电位被补偿至所述数据信号的电位与所述驱动晶体管的阈值电位之和。
在一个示例中，所述第一电平低于所述第二电平。
本公开的第三方面，还提供了一种显示面板，包括如本公开第一方面所述的任一像素电路。
本公开的第四方面，还提供了一种显示装置，包括如本公开第三方面所述的显示面板。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1示出了根据本公开的实施例的一种像素电路的结构示意图；
图2示出了图1所示的像素电路的一种具体电路图；
图3示出了用于驱动上述实施例中的像素电路的方法的流程图；
图4示出了如图1或图2所示的像素电路的示例性的驱动时序图；
图5a-5e示出了与图3中的T1-T5各阶段分别对应的像素电路中各晶体管的导通状态；以及
图6是示出了在图2所示的像素电路中对阈值补偿晶体管M1设置不同的阈值电压时仿真得到的流过其自身的电流与其栅源极电压差Vg之间的关系曲线图、以及流过OLED的电流的示意曲线图。
具体实施方式
将参照附图详细描述根据本公开的各个实施例。这里，需要注意的是，在 附图中，将相同的附图标记赋予基本上具有相同或类似结构和功能的组成部分，并且将省略关于它们的重复描述。
为使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合本公开的实施例的附图，对本公开的实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本实施例中，每个晶体管的漏极和源极的连接方式可以互换，因此，本公开实施例中各晶体管的漏极、源极实际是没有区别的。这里，仅仅是为了区分晶体管除栅极之外的两极，而将其中一极称为漏极，另一极称为源极。
图1示出了根据本公开的实施例的一种像素电路的结构示意图。如图1所示，该像素电路100可以包括数据信号写入模块110、驱动模块120、阈值补偿晶体管M1、第一电源电压写入模块130、发光模块140，其中，驱动模块120可以包括驱动晶体管DTFT。
例如，数据信号写入模块110，其可以与数据写入控制端Gate(n)、数据信号端Data(n)、驱动晶体管DTFT的源极相连。该数据信号写入模块110用于在数据写入控制端Gate(n)的数据写入控制信号的控制下将数据信号端的数据信号Date(n)传递到驱动晶体管的源极。
阈值补偿晶体管M1，其栅极与第一节点N1相连，其源极与驱动晶体管DTFT的栅极相连，其漏极与驱动晶体管DTFT的漏极相连。该阈值补偿晶体 管M1用于在第一节点N1处于有效电平的情况下对驱动晶体管DTFT的栅极进行电压补偿。
第一电源电压写入模块130，其与第一发光控制信号端EM(n)、第一电源电压端ELVDD和驱动晶体管DTFT的源极相连。该第一电源电压写入模块130用于在第一发光控制信号端EM(n)的第一发光控制信号的控制下将第一电源电压端ELVDD的第一电源电压信号写入驱动晶体管DTFT的源极。
发光模块140，其第一端与发光控制模块相连，第二端连接到第二电源电压端ELVSS。
当第一节点N1处于使阈值补偿晶体管M1导通的有效电平时，该阈值补偿晶体管M1的导通可以使得驱动晶体管DTFT的栅漏极之间连通，从而形成经过驱动晶体管DTFT的漏极而对驱动晶体管DTFT的栅极的电压进行调整(例如，复位或补偿)的路径。
然而，传统像素电路中通常使用低温多晶硅(LTPS)薄膜晶体管(TFT)来对驱动晶体管DTFT进行阈值电压补偿，但LTPS TFT在处于截止状态时的电流(I off)明显且I off存在翘尾现象，这使得像素电路中存在漏电流而不能很好地锁住Data资料补偿后的电压。
考虑到上述问题，在本公开的实施例中，阈值补偿晶体管M1可以例如采用氧化物晶体管(Oxide TFT)。该Oxide TFT相对于LTPS TFT具备以下优点：Oxide TFT在处于截止状态时的电流比较小，数量级在1.0E-13，且截止状态时的电流平缓。因此，当采用Oxide TFT来取代LTPS TFT以用于电压补偿时，像素电路中的漏电流非常小，因而可以显著改善像素电路中发光器件的发光亮度不一致的问题。
在一个示例中，图1所示的像素电路100还可以包括参考信号写入模块150，该模块连接在第一节点N1处以用于控制N1节点的电位。例如，该参考信号写入模块150还可以与参考控制端Gate(n-2)、参考信号端Vref、第一发光控制信号端EM(n)相连。该参考信号写入模块150用于根据参考控制端Gate(n-2)的参考控制信号和第一发光控制信号端EM(n)的第一发光控制信号来控制第一节点N1的电位。
在一个示例中，图1所示的像素电路100还可以包括复位模块160，其可 以与复位控制端Gate(n-1)、复位电位端Vint和发光模块的第一端相连。该复位模块160用于在复位控制端Gate(n-1)的复位控制信号的控制下，对发光模块的第一端进行复位。
在一个示例中，图1所示的像素电路100还可以包括发光控制模块170，其可以与第二发光控制信号端EM(n+1)、驱动晶体管的漏极和发光模块相连，并且其可以被配置为在第二发光控制信号端EM(n+1)的第二发光控制信号的控制下驱动发光模块发光。
图2示出了图1所示的像素电路的一种具体电路图。如图2所示的像素电路，其中，参考信号写入模块150可以包括参考信号写入晶体管M2和第一电容C1。例如，参考信号写入晶体管M2的栅极可以与参考控制端Gate(n-2)相连，源极与第一节点N1相连，漏极与参考信号端Vref相连。该参考信号写入晶体管M2用于在参考控制端Gate(n-2)的参考控制信号的控制下，将参考信号端Vref的参考信号传递到第一节点N1处。该第一电容C1可以连接在第一发光控制信号端EM(n)和第一节点N1之间；该第一电容C1用于在第一发光控制信号端EM(n)的发光控制信号发生突变时，相应改变第一节点N1处的电压，以维持第一电容C1两端恒定的电压差。
在一个示例中，数据信号写入模块110可以包括数据写入晶体管M3。数据写入晶体管M3的栅极与数据写入控制端Gate(n)相连，源极与数据信号端Date(n)相连，漏极与驱动晶体管DTFT的源极相连。该数据写入晶体管M3用于在写入控制端Gate(n)的写入控制信号的控制下，将数据信号端Date(n)的数据信号写入驱动晶体管DTFT的源极。
在一个示例中，驱动模块120还可以包括第二电容C2。该第二电容C2连接在驱动晶体管DTFT的栅极和第一电源电压端ELVDD之间。该第二电容C2用于在驱动晶体管DTFT的阈值电压的补偿完成后维持DTFT的栅极电压的稳定。
在一个示例中，第一电源电压写入模块130可以包括第一电源电压写入晶体管M4。该第一电源电压写入晶体管M4的栅极与第一发光控制信号端EM(n)相连，源极与第一电源电压端ELVDD相连，漏极与驱动晶体管DTFT的源极相连。该第一电源电压写入晶体管M4用于在第一发光控制信号端 EM(n)的第一发光控制信号的控制下将第一电源电压端ELVDD的第一电源电压写入驱动晶体管DTFT的栅极。
在一个示例中，复位模块160可以包括复位晶体管M5。该复位晶体管M5的栅极与复位控制端Gate(n-1)相连，源极与发光模块140的第一端相连，漏极与复位电位端Vint相连。该复位晶体管M5用于在复位控制端Gate(n-1)的复位控制信号的控制下对发光模块140的第一端和驱动晶体管的栅极进行复位。
在一个示例中，发光模块140可以包括发光器件，例如有机发光二极管(OLED)。例如，将该OLED的阳极作为发光模块的第一端，其阴极作为发光模块的第二端。
在一个示例中，发光控制模块170可以包括发光控制晶体管M6。该发光控制晶体管M6的栅极与第二发光控制信号端EM(n+1)相连，源极与驱动晶体管DTFT的漏极相连，漏极与发光模块140的第一端相连。该发光控制晶体管M6用于在第二发光控制信号端EM(n+1)的第二发光控制信号的控制下，将流过驱动晶体管DTFT的驱动电流传递到发光模块140以驱动其发光。
并且，例如，为了保证在将复位电位端Vint的复位电位传递到发光模块140的第一端(OLED的阳极)时，OLED不发光，则需要满足OLED的阳极电压低于其阴极电压，即复位电位端Vint的复位信号的电压低于第二电源电压端ELVSS的第二电源电压。
当然，为了保证发光器件的后续正常发光，第一电源电压端ELVDD的第一电源电压应当高于第二电源电压端ELVSS的第二电源电压。
本公开的实施例以阈值补偿晶体管M1为N型晶体管(氧化物N型晶体管)，而驱动晶体管DTFT、参考信号写入晶体管M2、数据写入晶体管M3、第一电源电压写入晶体管M4、复位晶体管M5以及发光控制晶体管M6均为P型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到本公开实施例采用N型晶体管或N型和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
应当了解，图2仅示出了根据本公开的实施例的像素电路的一种示例电 路结构，而实际上，像素电路中各模块可以具有各种电路结构，本公开不对此做出限制。
本公开的实施例还提供了一种用于驱动上述像素电路的方法。例如，在图3示出了用于驱动上述实施例中的像素电路的方法的流程图，并且在图4中示出了如图1或图2所示的像素电路的示例性的驱动时序图，以及在图5a-图5e中示出了与图3中的T1-T5各阶段分别对应的像素电路中各晶体管的导通状态。
如图3所示，在一帧显示时间段内，该驱动方法可以包括数据写入及阈值补偿阶段T3、发光阶段T5。
在数据写入及阈值补偿阶段T3，可以设置参考控制端Gate(n-2)的参考控制信号为第二电平，设置复位控制端Gate(n-1)的复位控制信号为第二电平，设置数据写入控制端Gate(n)的数据写入控制信号为第一电平，设置第一发光控制信号EM(n)的第一发光控制信号为第二电平，设置第二发光控制信号端EM(n+1)的第二发光控制信号为第二电平，设置数据信号端Data(n)的数据信号为有效数据信号。
在发光阶段T5，可以设置参考控制端Gate(n-2)的参考控制信号为第二电平，设置复位控制端Gate(n-1)的复位控制信号为第二电平，设置数据写入控制端Gate(n)的数据写入控制信号为第二电平，设置第一发光控制信号EM(n)的第一发光控制信号为第一电平，设置第二发光控制信号端EM(n+1)的第二发光控制信号为第一电平，设置数据信号端Data(n)的数据信号为无效数据信号。
在一个示例中，上述驱动方法，还可以包括第一初始化阶段T1和第二初始化阶段T2。
例如，在第一初始化阶段T1，可以设置参考控制端Gate(n-2)的参考控制信号为第一电平，设置复位控制端Gate(n-1)的复位控制信号为第二电平，设置数据写入控制端Gate(n)的数据写入控制信号为第二电平，设置第一发光控制信号EM(n)的第一发光控制信号为第一电平，设置第二发光控制信号端EM(n+1)的第二发光控制信号为第一电平，设置数据信号端Data(n)的数据信号为无效数据信号。
在第二初始化阶段T2，可以设置参考控制端Gate(n-2)的参考控制信号为第二电平，设置复位控制端Gate(n-1)的复位控制信号为第一电平，设置数据写入控制端Gate(n)的数据写入控制信号为第二电平，设置第一发光控制信号EM(n)的第一发光控制信号为第二电平，设置第二发光控制信号端EM(n+1)的第二发光控制信号为第一电平，设置数据信号端Data(n)的数据信号为无效数据信号。
在一个示例中，上述驱动方法可以在数据写入及阈值补偿阶段T3之后、在发光阶段T5之前，还包括预发光阶段T4。在该预发光阶段T4，设置参考控制端Gate(n-2)的参考控制信号为第二电平，设置复位控制端Gate(n-1)的复位控制信号为第二电平，设置数据写入控制端Gate(n)的数据写入控制信号为第二电平，设置第一发光控制信号EM(n)的第一发光控制信号为第一电平，设置第二发光控制信号端EM(n+1)的第二发光控制信号为第二电平，设置数据信号端Data(n)的数据信号为无效数据信号。
通常，在像素电路工作一段时间后，阈值补偿晶体管的阈值电压会发生偏移。例如，如果该阈值补偿晶体管是N型晶体管，由于N型晶体管的阈值电压为高电平，那么当它工作了一段时间后，该N型晶体管的阈值电压会朝负向偏移。此时，为了避免该阈值补偿晶体管在应当截止时被导通，需要调整施加到该阈值补偿晶体管的栅极的电压信号，即可以基于阈值补偿晶体管的阈值电压的偏移调整参考信号端的参考信号。
在本公开的实施例中，例如，第一电平为低电平VGL，第二电平为高电平VGH。并且，如前所述，在本公开的实施例中，阈值补偿晶体管为N型晶体管(例如，氧化物N型晶体管)，其它晶体管均为P型晶体管。因为，第一电平(低电平)是使得阈值补偿晶体管M1导通的有效电平，而第二电平(高电平)是使得除阈值补偿晶体管外的其它模块或其它晶体管导通的有效电平。
当然，本公开不对像素电路中所使用的各晶体管的类型做出限定，例如，可以将各晶体管均配置为P型或N型晶体管，这时需要将像素电路的内部连接结构进行翻转，并对各驱动信号做出调整。
下面将参考图4、图2、和图5a-5e来描述根据本公开实施例的像素电路的示例操作。
在第一初始化阶段T1，参考控制端Gate(n-2)的参考控制信号处于第一电平，参考信号写入晶体管M2导通，使得参考信号端Gate(n-2)的参考信号被传递至第一节点N1。此时，第一节点N1的电压为参考信号Vref，阈值补偿晶体管M1截止。在第一初始化阶段T1期间，各晶体管的导通状态如图5a所示。
在第二初始化阶段T2，参考控制端Gate(n-2)的参考控制信号从第一电平跳变至第二电平，使得参考信号写入晶体管M2截止。同时，第一发光控制信号端EM(n)的第一发光控制信号从第一电平VGL跳变至第二电平VGH，拉高第一节点N1的电平，使得第一节点N1的电压为Vref+(VGH-VGL)。第一节点N1的电位变高后，使得阈值补偿晶体管M1导通，并且此时复位控制端Gate(n)的复位控制信号为第一电平，使得复位晶体管M5导通，由此，复位电位端Vint的复位电位经由复位晶体管M5传递到有机发光二极管OLED的阳极，并且进一步经由阈值补偿晶体管M1传递到驱动晶体管DTFT的栅极。因而，实现了对OLED的阳极和驱动晶体管DTFT的栅极电压的复位。此时，OLED的阳极以及驱动晶体管DTFT的栅极的电位均为Vint，并且由于Vint<ELVSS，保证了OLED不发光。DTFT的源极的电压为Vint-Vth，使得驱动晶体管DTFT的栅源极之间的电压差为Vgs＝Vth，驱动晶体管DTFT此时处于截止状态(完成OFF Bias偏置)，从而可以改善OLED的短期残像不良现象。在第二初始化阶段T2，各晶体管的导通状态如图5b所示。图5b还示出了该像素电路此时的电流流向，即从复位晶体管M5到发光控制晶体管M6再到阈值补偿晶体管M1，一直流向驱动晶体管DTFT的栅极。
在数据写入及阈值补偿阶段T3，由于第一电容C1的存在，第一节点N1的电位可以保持为Vref+(VGH-VGL)。复位控制端Gate(n-1)的复位控制信号从第一电平跳变至第二电平，复位晶体管M5截止。数据写入控制端Gate(n)的数据写入控制信号为第二电平，数据信号写入晶体管M3导通，数据信号端Data(n)的数据信号被传递到驱动晶体管DTFT的源极，并经由阈值补偿晶体管M1对驱动晶体管的栅极电压进行补偿。此时，驱动晶体管DTFT的源极的电压为Vdata，补偿后的驱动晶体管DTFT的栅极电压为Vdata+Vth。在数据写入及阈值补偿阶段T3，各晶体管的导通状态如图5c所示。图5c还示出 了此时该像素电路中的电流流向，即从数据写入晶体管M3到驱动晶体管DTFT的源极再到阈值补偿晶体管，一直流向驱动晶体管DTFT的栅极。
在预发光阶段T4，第一发光控制信号端EM(n)的第一发光控制信号从第二电平跳变至第一电平，使得数据信号写入晶体管M4导通，第一电源电压端ELVDD的第一电源电压被传递至驱动晶体管DTFT的源极。并且，由于EM(n)由高变低，使得第一节点N1的电平由Vref+(VGH-VGL)被耦合回到Vref。由于第二电容C2的存在，驱动晶体管DTFT的栅极的电压保持在Vdata+Vth。在预发光阶段T4，各晶体管的导通状态如图5d所示。
在发光阶段T5，第二发光控制信号端EM(n+1)的第二发光控制信号变为第一电平，发光控制晶体管M6导通，第一电源电压端ELVDD的第一电源电压经由数据写入晶体管M4、驱动晶体管DTFT和发光控制晶体管M6产生的驱动电流流入OLED，驱动OLED发光。在发光阶段T5，各晶体管的导通状态如图5e所示。图5e还示出了此时驱动电路中的电路流向，即从第一电源电压写入晶体管M4到驱动晶体管DTFT再到发光控制晶体管M6，一直流向发光器件OLED。
驱动电流IOLED满足如下饱和电流公式：
I OLED＝K(Vgs-Vth) 2＝K(Vdata+Vth-ELVDD-Vth) 2＝K(Vdata-ELVDD) 2
其中，
Figure PCTCN2019071655-appb-000001
μ n为驱动晶体管的沟道迁移率，Cox为驱动晶体管单位面积的沟道电容，W和L分别为驱动晶体管的沟道宽度和沟道长度，Vgs为驱动晶体管的栅源电压(驱动晶体管的栅极电压与源极电压之差)。
由上式可以看出，流经OLED的电流与驱动晶体管DTFT的阈值电压无关。由此可见，根据本公开的实施例的用于驱动像素电路的方法较好地实现了对驱动晶体管DTFT的阈值电压的补偿。
例如，如图4所示的各信号的操作时序，可以将参考信号写入控制端Gate(n-2)的参考信号写入控制信号、复位控制端Gate(n-1)的复位控制信号和数据写入控制端Gate(n)的数据写入控制信号设置为相继延迟一段时间，例如，可以使用像素电路中前后级移位寄存器的输出分别作为上述三个控制信号。例如，也可以将第一发光控制信号端EM(n)的第一发光控制信号和第二发光控制信号端EM(n+1)的第二发光控制信号也设置为彼此延迟一段时间。图4 所示的各信号的操作时序仅是示例性的，本公开不对其做出限制。
图6示出了在图2所示的像素电路中对阈值补偿晶体管M1设置不同的阈值电压时仿真得到的流过其自身的电流与其栅源极电压差Vg之间的关系曲线图、以及在此期间流过OLED的电流的示意曲线图。
如前所述，当像素电路工作了一段时间后，阈值补偿晶体管M1的阈值电压会发生偏移。在本公开的实施例中，使用氧化物N型晶体管作为该阈值补偿晶体管，其阈值电压可能朝负向偏移。于是，例如，可以使用SmartSpice等仿真软件，通过对如图2所示的像素电路中的阈值补偿晶体管M1设置不同的阈值电压，得到在不同阈值电压的情况下，流过阈值补偿晶体管M1的电流的仿真示意图。如图6的上图所示为对阈值补偿晶体管M1设置不同的阈值电压时仿真得到的流过其自身的电流与其栅源极电压差Vg之间的关系曲线图。如图6的上图所示，例如，阈值补偿晶体管M1的阈值电压被分别设置为0V(偏移前)和-5V(偏移后)，从而得到两条对应的电流曲线。图6的下图所示为在此期间流过OLED的电流的示意曲线图。从图6的下图中可以看出，在上述的不同阈值电压的设置下，流过OLED的电流的曲线却可以接近重合。这更说明了，根据本公开的实施例的像素电路可以较好地实现对于驱动晶体管的阈值电压的补偿，以克服各像素电路的发光器件彼此发光亮度不一致的缺陷。并且，在图6的上图还可以看出，氧化物晶体管在处于截止状态下的电流比较小，并且较为平缓。因此，当使用氧化物晶体管作为阈值补偿晶体管时，可以保证在完成了对驱动晶体管的数据电压写入和阈值电压补偿后，可以较稳定地将Data资料写入后补偿好的状态保持住。
本公开的实施例还提供一种显示面板，该显示面板包括本公开任一实施例提供的像素电路。
本公开的实施例还提供一种显示装置，该显示装置包括本公开上述提供的显示面板。例如，显示装置可以包括手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改 或改进，均属于本公开要求保护的范围。

Claims (22)

  1. 一种像素电路，包括数据信号写入模块、驱动模块、阈值补偿晶体管、第一电源电压写入模块、发光模块，其中所述驱动模块中包括驱动晶体管，其中，
    第一电源电压写入模块，其与第一发光控制信号端、第一电源电压端、驱动晶体管的源极及其栅极相连，并且第一电源电压写入模块被配置为在所述第一发光控制信号端的第一发光控制信号的控制下将所述第一电源电压端的第一电源电压信号写入驱动晶体管的源极；
    数据信号写入模块，其与写入控制端、数据信号端、驱动晶体管的源极相连，并且数据信号写入模块被配置为在写入控制端的写入控制信号的控制下将所述数据信号端的数据信号传递到驱动晶体管的源极；
    阈值补偿晶体管，其栅极与第一节点相连，源极与驱动晶体管的栅极相连，其漏极与驱动晶体管的漏极相连，并且阈值补偿晶体管被配置为在第一节点处于有效电平的情况下对驱动晶体管的栅极进行电压补偿；
    发光模块，其第一端与驱动晶体管的漏极相连，第二端连接到第二电源电压端。
  2. 如权利要求1所述的像素电路，其中，所述阈值补偿晶体管为氧化物晶体管。
  3. 如权利要求1-2任一所述的像素电路，其中，所述像素电路还包括：
    参考信号写入模块，其与参考控制端、参考信号端、第一发光控制信号端和第一节点相连，并且参考信号写入模块被配置为根据参考控制端的参考控制信号和第一发光控制信号端的第一发光控制信号来控制第一节点的电位。
  4. 如权利要求1-3任一所述的像素电路，其中，所述像素电路还包括：
    复位模块，其与复位控制端、复位电位端和发光模块的第一端相连，并且复位模块被配置为在复位控制端的复位控制信号的控制下对所述发光模块的第一端和驱动晶体管的栅极进行复位。
  5. 如权利要求1-4任一所述的像素电路，其中，所述像素电路还包括：
    发光控制模块，其与第二发光控制信号端、驱动晶体管的漏极和发光模块的第一端相连，被配置为在所述第二发光控制信号端的第二发光控制信号的控制下驱动所述发光模块发光。
  6. 如权利要求3所述的像素电路，其中，所述参考信号写入模块包括：
    参考信号写入晶体管，其栅极与参考控制端相连，源极与第一节点相连，漏极与参考信号端相连；以及，
    第一电容，连接在第一发光控制信号端和第一节点之间。
  7. 如权利要求1-6任一所述的像素电路，其中，所述数据信号写入模块包括：
    数据写入晶体管，其栅极与数据写入控制端相连，源极与数据信号端相连，漏极与驱动晶体管的源极相连。
  8. 如权利要求1-7任一所述的像素电路，其中，所述第一电源电压写入模块包括：
    第一电源电压写入晶体管，其栅极与第一发光控制信号端相连，源极与第一电源电压端相连，漏极与驱动晶体管的源极相连。
  9. 如权利要求1-8任一所述的像素电路，其中，所述驱动模块还包括：
    第二电容，连接在第一电源电压端和驱动晶体管的栅极之间。
  10. 如权利要求5所述的像素电路，其中，所述发光控制模块包括：
    发光控制晶体管，其栅极与第二发光控制信号端相连，源极与驱动晶体管的漏极相连，漏极与发光模块的第一端相连。
  11. 如权利要求1-10任一所述的像素电路，其中，所述发光模块包括：
    有机发光二极管OLED，所述OLED的阳极作为所述发光模块的第一端，所述OLED的阴极作为所述发光模块的第二端。
  12. 如权利要求4所述的像素电路，其中，所述复位模块包括复位晶体管，其栅极与复位控制端相连，源极与发光模块的第一端相连，漏极与复位电位端相连。
  13. 如权利要求12所述的像素电路，其中，第二电源电压端的第二电源电压低于复位电位端的复位电位。
  14. 一种用于驱动如权利要求1-13任一所述的像素电路的方法，包括：
    在数据写入及阈值补偿阶段，所述写入控制端的写入控制信号处于第一电平，将所述数据信号端的数据信号写入驱动晶体管的源极，并且参考控制端的参考控制信号从第一电平跳变至第二电平，第一发光控制信号的电平从第一电平跳变至第二电平，拉高所述第一节点的电平，在所述第一节点的控制 下，对所述驱动晶体管的栅极电位进行补偿；
    在发光阶段，所述第二发光控制信号端的第二发光控制信号处于第一电平，所述驱动晶体管的驱动电流流向所述发光模块，驱动所述发光模块发光。
  15. 如权利要求14所述的方法，其中，所述像素电路还包括：
    参考信号写入模块，其与参考控制端、参考信号端、第一发光控制信号端和第一节点相连；
    所述方法还包括：第一初始化阶段和第二初始化阶段，
    在第一初始化阶段，参考控制端的参考控制信号处于第一电平，将所述参考信号端的参考信号传递至第一节点；
    在第二初始化阶段，参考控制端的参考控制信号从第一电平跳变至第二电平，第一发光控制信号的电平从第一电平跳变至第二电平，拉高所述第一节点的电平。
  16. 如权利要求14-15任一所述的方法，其中，所述像素电路还包括：
    复位模块，其与复位控制端、复位电位端和发光模块的第一端相连；
    在所述第二初始化阶段，所述复位控制端的复位控制信号处于第一电平，将复位电位端的复位电位传递至发光模块的第一端和所述驱动晶体管的栅极。
  17. 如权利要求15所述的方法，其中，在所述像素电路工作预设时间后，所述参考信号端的参考信号基于阈值补偿晶体管的阈值电压的偏移而调整。
  18. 如权利要求14-17任一所述的方法，其中，所述像素电路还包括：
    发光控制模块，其与第二发光控制信号端、驱动晶体管的漏极和发光模块的第一端相连；
    在所述数据写入及阈值补偿阶段后、在所述发光阶段前，所述方法还包括：
    预发光阶段，
    在所述预发光阶段，所述第一发光控制信号端的第一发光控制信号处于第一电平，将所述第一电源电压端的第一电源电压传递至所述驱动晶体管的源极。
  19. 如权利要求14-18任一所述的方法，其中，在数据写入及阈值补偿阶段，所述驱动晶体管的栅极电位被补偿至所述数据信号的电位与所述驱动晶体管的阈值电位之和。
  20. 如权利要求14-18任一所述的方法，其中，所述第一电平低于所述第二电平。
  21. 一种显示面板，包括如权利要求1-13任一所述的像素电路。
  22. 一种显示装置，包括如权利要求21所述的显示面板。
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