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WO2018188390A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2018188390A1
WO2018188390A1 PCT/CN2018/070792 CN2018070792W WO2018188390A1 WO 2018188390 A1 WO2018188390 A1 WO 2018188390A1 CN 2018070792 W CN2018070792 W CN 2018070792W WO 2018188390 A1 WO2018188390 A1 WO 2018188390A1
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Prior art keywords
transistor
pole
terminal
control
signal terminal
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Application number
PCT/CN2018/070792
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English (en)
French (fr)
Inventor
青海刚
黄炜赟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/464,390 priority Critical patent/US11100866B2/en
Publication of WO2018188390A1 publication Critical patent/WO2018188390A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display device including the pixel circuit.
  • OLED displays have a wide viewing angle, high brightness, and high contrast compared to the current mainstream display technology, Thin Film Transistor Liquid Crystal Display (TFT-LCD).
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the driving method of the OLED display can be divided into a passive matrix type (PM, Passive Matrix) and an active matrix type (AM, Active Matrix).
  • PM Passive Matrix
  • AM Active Matrix
  • passive matrix drives have the advantages of large display information, low power consumption, long device life, and high picture contrast.
  • the threshold voltage of the driving transistor is different due to the unevenness of the process process, and the driving transistors at different positions of the display panel are different. Since the current flowing through the light emitting device is related to the threshold voltage of the driving transistor, the brightness of the light emitting device may be different for the same data driving signal, thereby affecting the picture uniformity of the entire OLED display and its light quality. Moreover, due to the internal resistance of the display, there will be differences in the supply voltage at different locations of the display. Since the current flowing through the light emitting device is related to the power supply voltage of the display, this also causes different luminance of the light emitting device to appear for the same data signal, thereby affecting the uniformity of the display screen.
  • a pixel circuit includes: an initialization signal terminal, a scan signal terminal, a data signal terminal, a first power terminal, a second power terminal, a reference voltage terminal, a data signal terminal, and a lighting signal control terminal. a reset signal terminal, a data write sub-circuit, a threshold compensation sub-circuit, an illumination control sub-circuit, a reset sub-circuit, a storage capacitor, a drive transistor, and a light-emitting device.
  • the data writing sub-circuit is connected to the scanning signal terminal, the data signal terminal and the first end of the storage capacitor, and is configured to transmit the data signal input from the data signal terminal to the storage under the control of the scanning signal input from the scanning signal terminal.
  • the first end of the capacitor is connected to the scanning signal terminal, the data signal terminal and the first end of the storage capacitor, and is configured to transmit the data signal input from the data signal terminal to the storage under the control of the scanning signal input from the scanning signal terminal. The first end of the capacitor.
  • the threshold compensation sub-circuit is coupled to the first pole, the second pole, the node, the scan signal terminal, the reference voltage terminal, and the first pole of the light emitting device of the driving transistor, and is configured to pre-store a threshold voltage of the driving transistor in the storage capacitor.
  • the light-emitting control sub-circuit is connected to the first power terminal, the first end of the storage capacitor, the first pole of the driving transistor, and the light-emission control signal end, and is configured to control the driving under the control of the light-emitting control signal input from the light-emitting control signal end
  • the transistor drives the light emitting device to emit light.
  • the reset sub-circuit is connected to the node, the reset signal terminal, and the initialization signal terminal, and is configured to transmit an initialization signal input from the initialization signal terminal to the node under control of a reset signal input from the reset signal terminal.
  • a second end of the storage capacitor, a control electrode of the driving transistor is connected to the node, and a second pole of the light emitting device is connected to the second power terminal.
  • Vss is a voltage value input from the second power supply terminal
  • Vref is a reference voltage value input from the reference voltage terminal
  • the illumination control subcircuit includes a first transistor and a second transistor. a first pole of the first transistor is connected to a second pole of the second transistor and a first power terminal, and a second pole of the first transistor is connected to the threshold compensating sub-circuit and a first pole of the driving transistor And the control electrode of the first transistor is connected to the light emission control signal end. a first pole of the second transistor is coupled to the first end of the storage capacitor and the data write subcircuit, a second pole of the second transistor is coupled to the light emission control subcircuit, and the second transistor The control electrode is connected to the illumination control signal terminal.
  • the threshold compensation subcircuit includes a third transistor and a fourth transistor.
  • a first pole of the third transistor is connected to a reference voltage terminal
  • a second pole of the third transistor is connected to a second pole of the driving transistor and a first pole of the light emitting device, and control of the third transistor The pole is connected to the scanning signal terminal.
  • a first pole of the fourth transistor is coupled to a first pole of the driving transistor
  • a second pole of the fourth transistor is coupled to the node
  • a gate of the fourth transistor is coupled to the scan signal terminal.
  • the threshold compensation subcircuit includes a third transistor and a fourth transistor.
  • the first pole of the third transistor is connected to the reference voltage terminal, the second pole is connected to the first pole of the driving transistor, and the gate of the third transistor is connected to the scan signal terminal.
  • a first pole of the fourth transistor is coupled to a second pole of the driving transistor, a second pole of the fourth transistor is coupled to the node, and a gate of the fourth transistor is coupled to the scan signal terminal.
  • the data write subcircuit comprises a fifth transistor. a first pole of the fifth transistor is connected to the data signal end, a second pole of the fifth transistor is connected to the first end of the storage capacitor and the light emission control sub-circuit, and the control electrode of the fifth transistor is connected Scan the signal end.
  • the reset subcircuit comprises a sixth transistor.
  • the first pole of the sixth transistor is connected to the initialization signal terminal, the second pole of the sixth transistor is connected to the node, and the control pole of the sixth transistor is connected to the reset signal terminal.
  • a driving method of any of the above pixel circuits includes a reset phase, a threshold compensation phase, and an illumination phase.
  • the reset phase the initialization signal input from the initialization signal terminal is transmitted to the node under the control of the reset signal input from the reset signal terminal.
  • the threshold compensation phase the threshold voltage of the drive transistor is pre-stored in the storage capacitor.
  • the control driving transistor drives the light-emitting device to emit light under the control of the light-emission control signal input from the light-emission control signal terminal.
  • Vss is a voltage value input from the second power terminal
  • Vref is a reference voltage value input from the reference voltage terminal
  • a display device comprising any of the above pixel circuits.
  • a pixel circuit includes: an initialization signal terminal, a scan signal terminal, a data signal terminal, a first power terminal, a second power terminal, a reference voltage terminal, a data signal terminal, and a lighting signal control terminal. And a reset signal terminal, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a driving transistor, a storage capacitor, and a light emitting device.
  • a first pole of the first transistor is connected to a second pole of the second transistor and a first power terminal, and a second pole of the first transistor is connected to a first pole of the fourth transistor and the driving transistor a first pole, and a control pole of the first transistor is coupled to the light emission control signal terminal.
  • a first pole of the second transistor is connected to a first end of the storage capacitor and a second pole of the fifth transistor, and a second pole of the second transistor is connected to a first pole and a first pole of the first transistor a power terminal, and a control electrode of the second transistor is coupled to the light emission control signal terminal.
  • a first pole of the third transistor is connected to a reference voltage terminal
  • a second pole of the third transistor is connected to a second pole of the driving transistor and a first pole of the light emitting device, and control of the third transistor The pole is connected to the scanning signal terminal.
  • a first pole of the fourth transistor is connected to a first pole of the driving transistor, a second pole of the fourth transistor is connected to a second pole and a node of the sixth transistor, and a gate of the fourth transistor is connected The scanning signal terminal.
  • a first pole of the fifth transistor is connected to the data signal end
  • a second pole of the fifth transistor is connected to the first end of the storage capacitor and the first pole of the second transistor
  • the fifth transistor The control electrode is connected to the scanning signal terminal.
  • the first pole of the sixth transistor is connected to the initialization signal terminal, the second pole of the sixth transistor is connected to the node, and the control pole of the sixth transistor is connected to the reset signal terminal.
  • a first end of the storage capacitor is coupled to a first pole of the second transistor and a second pole of the fifth transistor, and a second end of the storage capacitor is coupled to the node.
  • a first pole of the driving transistor is connected to a second pole of the first transistor and a first pole of the fourth transistor, and a second pole of the driving transistor is connected to the first pole of the light emitting device and the first A second pole of the three transistors, and a control electrode of the drive transistor is coupled to the node.
  • the first pole of the light emitting device is connected to the second pole of the third transistor and the second pole of the driving transistor, and the second pole of the light emitting device is connected to the second power terminal.
  • a pixel circuit includes: an initialization signal terminal, a scan signal terminal, a data signal terminal, a first power terminal, a second power terminal, a reference voltage terminal, a data signal terminal, and a lighting signal control terminal. And a reset signal terminal, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a driving transistor, a storage capacitor, and a light emitting device.
  • a first pole of the first transistor is connected to a second pole of the second transistor and a first power terminal, and a second pole of the first transistor is connected to a first pole of the fourth transistor and the driving transistor a first pole, and a control pole of the first transistor is coupled to the light emission control signal terminal.
  • a first pole of the second transistor is connected to a first end of the storage capacitor and a second pole of the fifth transistor, and a second pole of the second transistor is connected to a first pole and a first pole of the first transistor a power terminal, and a control electrode of the second transistor is coupled to the light emission control signal terminal.
  • a first pole of the third transistor is connected to a reference voltage terminal
  • a second pole of the third transistor is connected to a second pole of the first transistor and a first pole of the driving transistor
  • a control pole of the third transistor Connect the scanning signal terminal.
  • the first pole of the fourth transistor is connected to the second pole of the driving transistor, the second pole of the fourth transistor is connected to the node, and the gate of the fourth transistor is connected to the scan signal line.
  • a first pole of the fifth transistor is connected to the data signal end
  • a second pole of the fifth transistor is connected to the first end of the storage capacitor and the first pole of the second transistor
  • the fifth transistor The control electrode is connected to the scanning signal terminal.
  • the first pole of the sixth transistor is connected to the initialization signal terminal, the second pole of the sixth transistor is connected to the node, and the control pole of the sixth transistor is connected to the reset signal terminal.
  • a first end of the storage capacitor is coupled to a first pole of the second transistor and a second pole of the fifth transistor, and a second end of the storage capacitor is coupled to the node.
  • a first pole of the driving transistor is connected to a second pole of the first transistor and a second pole of the third transistor, and a second pole of the driving transistor is connected to the first pole of the light emitting device and the first A first pole of the four transistors, and a control electrode of the drive transistor is coupled to the node.
  • the first pole of the light emitting device is connected to the first pole of the fourth transistor and the second pole of the driving transistor, and the second pole of the light emitting device is connected to the second power terminal.
  • the driving in the storage capacitor is pre-existing
  • the threshold voltage of the transistor cancels with the threshold voltage in the current that drives the light-emitting device to emit light, thereby eliminating the influence of the variation of the threshold voltage of the driving transistor in the pixel circuit on the luminance of the light-emitting device, thereby ensuring the quality of the display picture.
  • the gate-source voltage of the driving transistor DTFT has no relationship with the voltage value input from the first power supply terminal, and therefore, the current flowing through the light-emitting device is not affected by the internal resistance of the display device, thereby solving the IR- Drop problem.
  • 1 is a circuit diagram of a conventional pixel circuit
  • FIG. 2 is a structural block diagram of a pixel circuit in accordance with an embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of a pixel circuit in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a timing chart of a driving method of the pixel circuit shown in FIG. 3;
  • FIG. 5 is an equivalent circuit diagram of the pixel circuit shown in FIG. 3 in a reset phase
  • FIG. 6 is an equivalent circuit diagram of the pixel circuit shown in FIG. 3 in a threshold compensation phase
  • FIG. 7 is an equivalent circuit diagram of the pixel circuit shown in FIG. 3 in an illuminating phase
  • FIG. 8 is a circuit diagram of another pixel circuit in accordance with an embodiment of the present disclosure.
  • FIG. 9 is an equivalent circuit diagram of the pixel circuit shown in FIG. 8 in a threshold compensation phase.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics. Since the source and drain of the transistor are interchangeable under certain conditions, there is no essential difference in the description of the source and drain connections.
  • one of the poles is referred to as a first pole
  • the other pole is referred to as a second pole
  • the gate is referred to as a gate.
  • the transistors can be classified into N-type and P-type according to characteristics, and the following embodiments are described in which transistors are P-type transistors.
  • Figure 1 illustrates a circuit diagram of a conventional pixel circuit.
  • the pixel circuit includes: a scan signal terminal Vscan(n), a data signal terminal Vdata, a first power terminal VDD, a second power terminal VSS, a first switching transistor M1, a driving transistor M2, a storage capacitor C1, and Light emitting device D1.
  • the control electrode of the first switching transistor M1 is connected to the scan signal terminal Vscan(n)
  • the first pole of the first switching transistor M1 is connected to the data signal terminal Vdata
  • the second pole of the first switching transistor M1 is controlled by the driving transistor M2. Extremely connected.
  • the first electrode of the driving transistor M2 is connected to the first power supply terminal VDD, and the second electrode of the driving transistor M2 is connected to one end of the light emitting device D1.
  • the storage capacitor C1 is connected between the gate electrode of the driving transistor M2 and the first electrode.
  • the first switching transistor M1 is turned on in response to receiving an active level from the scanning signal terminal Vscan(n), thereby transmitting the data signal input from the data signal terminal Vdata to the gate electrode of the driving transistor M2.
  • the driving transistor M2 is turned on in response to receiving a valid data signal, thereby transmitting a power supply signal input from the power supply terminal to one end of the light emitting device D1, so that the light emitting device D1 emits light.
  • the storage capacitor C1 is configured to maintain the stability of the voltage difference between the first pole and the control electrode of the drive transistor M2 for one frame time.
  • an active level is received from the scanning signal terminal Vscan(n) of the pixel circuit of the nth row, thereby the storage capacitor C1 is input through the data signal input from the data signal terminal Vdata. Charging. Then, an invalid level is input to the scanning signal terminal Vscan(n) of the pixel circuit of the nth row.
  • the storage capacitor C1 maintains the charging voltage, thereby ensuring that the driving transistor M2 of the row of pixel units outputs a stable current, so that the light-emitting device D1 of the row of pixel units continues to emit light until the end of one frame time.
  • One frame time is usually the time when the same row of pixel circuits receives two active levels from the scanning signal terminal Vscan(n).
  • the inventors have recognized that in the pixel circuit shown in FIG. 1, since the current flowing through the light emitting device D1 is related to the threshold voltage of the driving transistor M2 and the power supply voltage VDD, the light emitting device D1 is applied to the same data driving signal Vdata.
  • the brightness may vary, affecting the picture uniformity of the entire OLED display and its illumination quality.
  • the pixel circuit includes: an initialization signal terminal Init, a scan signal terminal G(n), a data signal terminal Data, a first power terminal EL VDD, a second power terminal EL VSS, a reference voltage terminal Ref, and a data signal.
  • Terminal Data illuminating signal control terminal EM(n), reset signal terminal Reset, data writing sub-circuit 3, threshold compensating sub-circuit 2, illuminating control sub-circuit 1, reset sub-circuit 4, storage capacitor Cst, driving transistor DTFT, and illuminating Device OLED.
  • the data writing sub-circuit 3 is connected to the scanning signal terminal G(n), the data signal terminal Data, and the first end of the storage capacitor Cst, and is configured to be under the control of the scanning signal input from the scanning signal terminal G(n)
  • the data signal input from the data signal terminal Data is transmitted to the first end of the storage capacitor Cst.
  • the threshold compensating sub-circuit 2 is connected to the first pole, the second pole, the node P, the scanning signal terminal G(n), the reference voltage terminal Ref and the first pole of the light emitting device OLED of the driving transistor DTFT, and is configured to be in the storage capacitor Cst
  • the threshold voltage of the driving transistor DTFT is prestored.
  • the light emission control sub-circuit 1 is connected to the first power supply terminal EL VDD, the first end of the storage capacitor Cst, the first electrode of the drive transistor DTFT, and the light emission control signal terminal EM(n), and is configured to be at the slave illumination control signal terminal EM ( n) Controlling the driving transistor DTFT to drive the light emitting device OLED to emit light under the control of the input light emitting control signal.
  • the reset sub-circuit 4 is connected to the node P, the reset signal end Reset, and the initialization signal terminal Init, and is configured to transmit the initialization signal input from the initialization signal terminal Init to the node P under the control of the reset signal input from the reset signal terminal Reset. .
  • the second end of the storage capacitor Cst, the control electrode of the driving transistor DTFT are connected to the node P, and the second electrode of the light emitting device OLED is connected to the second power supply terminal EL VSS.
  • the threshold voltage of the driving transistor DTFT is canceled by the threshold voltage in the current for driving the light-emitting device OLED to emit light, thereby eliminating the influence of the variation of the threshold voltage of the driving transistor DTFT in the pixel circuit on the luminance of the light-emitting device OLED, thereby ensuring the quality of the display picture.
  • the gate-source voltage of the driving transistor DTFT has no relationship with the voltage value input from the first power supply terminal EL VDD, and therefore, the current flowing through the light-emitting device OLED is not affected by the display device
  • the internal resistance affects the IR-drop problem.
  • FIG. 3 illustrates a specific circuit diagram of the pixel circuit shown in FIG. 2 in accordance with an embodiment of the present disclosure.
  • the light emission control sub-circuit 1 may include a first transistor T1 and a second transistor T2.
  • the first pole of the first transistor T1 is connected to the second pole of the second transistor T2 and the first power terminal EL VDD
  • the second pole of the first transistor T1 is connected to the threshold compensating sub-circuit 2 and the first pole of the driving transistor DTFT
  • the control electrode of a transistor T1 is connected to the light-emission control signal terminal EM(n).
  • the first terminal of the second transistor T2 is connected to the first end of the storage capacitor Cst and the data writing sub-circuit 3, the second electrode of the second transistor T2 is connected to the illumination control sub-circuit 1, and the control electrode of the second transistor T2 is connected to the illumination control Signal terminal EM(n).
  • the first transistor T1 and the second transistor T2 are turned on. At this time, the first electrode and the control electrode of the driving transistor DTFT are connected by the storage capacitor Cst.
  • the threshold compensation sub-circuit 2 includes a third transistor T3 and a fourth transistor T4.
  • the first pole of the third transistor T3 is connected to the reference voltage terminal Ref
  • the second pole of the third transistor T3 is connected to the second pole of the driving transistor DTFT and the first pole of the light emitting device OLED
  • the gate of the third transistor T3 is connected to the scan signal End G(n).
  • the first electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor DTFT
  • the second electrode of the fourth transistor T4 is connected to the node P
  • the control electrode of the fourth transistor T4 is connected to the scanning signal terminal G(n).
  • the third transistor T3 and the fourth transistor T4 are turned on. At this time, the diode formed by the driving transistor DTFT tube through the fourth transistor T4 is turned on. Since the third transistor T3 is turned on, the reference voltage Vref input from the reference voltage terminal Ref at this time is charged by the drive transistor DTFT storage capacitor Cst. As the charge continues to flow, the potential of the node P continues to rise. When the potential of the node P rises to Vref ⁇
  • the data writing sub-circuit 3 includes a fifth transistor T5.
  • the first electrode of the fifth transistor T5 is connected to the data signal terminal Data
  • the second electrode of the fifth transistor T5 is connected to the first end of the storage capacitor Cst and the light emission control sub-circuit 1
  • the control electrode of the fifth transistor T5 is connected to the scanning signal terminal G. (n).
  • the fifth transistor T5 is turned on. At this time, the data signal Vdata input from the data signal terminal Data is transmitted to the first end of the storage capacitor Cst through the fifth transistor T5.
  • the reset sub-circuit 4 includes a sixth transistor T6.
  • the first pole of the sixth transistor T6 is connected to the initialization signal terminal Init, the second pole of the sixth transistor T6 is connected to the node P, and the gate of the sixth transistor T6 is connected to the reset signal terminal Reset.
  • the sixth transistor T6 when an active level is input from the Reset signal terminal Reset terminal, the sixth transistor T6 is turned on. At this time, the initialization signal input from the initialization signal terminal Init is transmitted to the node P through the sixth transistor T6 to effect reset of the node P.
  • the term "active level" refers to the level at which the respective transistor is turned on. For example, when the corresponding transistor is a P-type transistor, the active level is a low level; when the corresponding transistor is an N-type transistor, the active level is a high level.
  • the embodiment provides a driving method for the above pixel circuit.
  • the driving method includes: in the reset phase, the initialization signal input from the initialization signal terminal is transmitted to the node under control of the reset signal input from the reset signal terminal; in the threshold compensation phase, the threshold voltage of the driving transistor is pre-stored in the storage capacitor And in the illuminating phase, controlling the driving transistor to drive the illuminating device to emit light under the control of the illuminating control signal input from the illuminating control signal terminal.
  • the driving in the storage capacitor is pre-existing when the light-emitting device is driven to emit light in the light-emitting phase
  • the threshold voltage of the transistor cancels with the threshold voltage in the current that drives the light-emitting device to emit light, thereby eliminating the influence of the variation of the threshold voltage of the driving transistor in the pixel circuit on the luminance of the light-emitting device, thereby ensuring the quality of the display picture.
  • the gate-source voltage of the driving transistor DTFT has no relationship with the voltage value input from the first power supply terminal, and therefore, the current flowing through the light-emitting device is not affected by the internal resistance of the display device. , thus solving the problem of IR-drop.
  • each transistor shown in FIG. 3 is a P-type transistor, and the effective level of each transistor is at a low level.
  • a low level is input from the reset signal terminal Reset
  • a high level is input from the light emission control signal terminal Em(n)
  • a high level is input from the scanning signal terminal G(n).
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off, and the sixth transistor T6 is turned on.
  • the equivalent circuit diagram is shown in Figure 5. Since the sixth transistor T6 is turned on, the initialization signal input from the initialization signal terminal Init is transmitted to the gate electrode of the driving transistor DTFT through the sixth transistor T6, so that the gate electrode of the driving transistor DTFT is reset to prepare for the next stage of threshold compensation. . At the same time, since the first transistor T1 is turned off, no current flows through the driving transistor DTFT at this stage, and thus the light emitting device OLED does not emit light.
  • a high level is input from the reset signal terminal Reset, a high level is input from the light-emission control signal terminal Em(n), a low level is input from the scan signal terminal G(n), and a data signal terminal Data is input. Enter a high level.
  • the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned off, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on.
  • the equivalent circuit is shown in Figure 6.
  • the fourth transistor T4 since the fourth transistor T4 is turned on, the driving transistor DTFT is diode-connected. Since the third transistor T3 is turned on, the reference level Vref input from the reference level terminal Ref is transmitted to the first electrode of the light emitting device OLED through the third transistor T3.
  • the voltage value input from the second power supply terminal EL VSS is Vss
  • the reference voltage value output from the reference voltage terminal Ref is Vref
  • the reference voltage value Vref is relatively close to the voltage value Vss input from the second power supply terminal EL VSS, and the voltage difference between Vref and Vss is mainly used to ensure that no current flows through the light during the threshold compensation phase.
  • the device OLED while the reference voltage Vref enters the first pole of the light emitting device OLED, can reset the light emitting device OLED, eliminates no composite carriers on the internal light emitting interface of the light emitting device OLED, and alleviates the aging of the light emitting device OLED.
  • 0.3V is only an example. Other voltage differences can be set by those skilled in the art in light of the teachings of the present disclosure.
  • the reference voltage Vref is set to be larger than the absolute value of the threshold voltage of the driving transistor DTFT larger than the initialization signal input from the initialization signal terminal Init.
  • the gate electrode of the driving transistor DTFT is still an initialization signal, and therefore, the diode formed by the driving transistor DTFT through the fourth transistor T4 is turned on, so that the reference voltage Vref charges the storage capacitor Cst through the driving transistor DTFT.
  • the potential of the node P continues to rise.
  • the driving transistor DTFT is turned off, and charging is ended. Since the fifth transistor T5 is turned on, the data voltage input from the data signal terminal Data is transmitted to the first terminal of the storage capacitor Cst. Therefore, at the end of the threshold compensation phase, the voltage difference across the storage capacitor Cst is:
  • V(Cst) Vdata ⁇ (Vref ⁇
  • the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off, and the first transistor T1 and the second transistor T2 are turned on.
  • the equivalent circuit is shown in Figure 7. In this stage, the first power supply voltage VDD input from the first power supply terminal EL VDD is transmitted to the first terminal of the storage capacitor Cst through the second transistor T2.
  • ). Therefore, the potential jump of the node P becomes VDD-V(Cst) VDD-Vdata+(Vref ⁇
  • ) VDD-Vdata+Vref ⁇
  • Vsg VDD ⁇ (VDD ⁇ Vdata+Vref ⁇
  • ) Vdata ⁇ Vref+
  • the current flowing through the light emitting device OLED is:
  • I oled K(Vsg-
  • ) 2 K(Vdata-Vref+
  • ) 2 K(Vdata-Vref) 2 , where K is a constant related to the process and design.
  • the light-emitting current of the light-emitting device OLED is only related to the data voltage Vdata and the reference voltage Vref, and is independent of the threshold voltage Vthd of the driving transistor DTFT and the first power source VDD.
  • FIG. 8 illustrates another specific circuit diagram of the pixel circuit shown in FIG. 2 in accordance with an embodiment of the present disclosure.
  • the specific circuit diagram shown in FIG. 8 differs from FIG. 3 only in the threshold compensation sub-circuit 2. Therefore, only the threshold compensation sub-circuit 2 in FIG. 8 will be described in detail below, and the same portions as those in FIG. 3 will not be described again.
  • the threshold compensation sub-circuit 2 includes a third transistor T3 and a fourth transistor T4.
  • the control electrode of the third transistor T3 is connected to the scanning signal terminal G(n)
  • the first electrode of the third transistor T3 is connected to the reference voltage terminal Ref
  • the second electrode of the third transistor T3 is connected to the first electrode of the driving transistor DTFT.
  • the control electrode of the fourth transistor T4 is connected to the scanning signal terminal G(n)
  • the first electrode of the fourth transistor T4 is connected to the second electrode of the driving transistor DTFT
  • the second electrode of the fourth transistor T4 is connected to the node P.
  • the driving method of the pixel circuit as shown in FIG. 8 is basically the same as the above-described driving method, and the only difference is the threshold compensation phase. Therefore, the threshold compensation phase of the pixel circuit shown in FIG. 8 will be described below only in conjunction with FIG. 4, and the rest of the stages will not be repeated.
  • a high level is input from the reset signal terminal Reset and the light emission control signal terminal, and a low level is input from the scanning signal terminal G(n).
  • the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned off, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on.
  • the equivalent circuit is shown in Figure 9.
  • the fourth transistor since the fourth transistor is turned on, the driving transistor DTFT is diode-connected. Since the third transistor T3 is turned on, the reference voltage input from the reference voltage terminal Ref is transmitted to the first electrode of the driving transistor DTFT.
  • the voltage value input from the second power supply terminal EL VSS is Vss
  • the reference voltage value output from the reference voltage terminal Ref is Vref
  • the reference voltage value Vref is relatively close to the voltage value Vss input from the second power supply terminal EL VSS, and the voltage difference between Vref and Vss is mainly used to ensure that no current flows through the light during the threshold compensation phase.
  • the device OLED while the reference voltage Vref enters the first pole of the light emitting device OLED, can reset the light emitting device OLED, eliminates no composite carriers on the internal light emitting interface of the light emitting device OLED, and alleviates the aging of the light emitting device OLED.
  • 0.3V is only an example. Other voltage differences can be set by those skilled in the art in light of the teachings of the present disclosure.
  • the reference voltage Vref is set to be larger than the absolute value of the threshold voltage of the driving transistor DTFT larger than the initialization signal input from the initialization signal terminal Init.
  • the gate electrode of the driving transistor DTFT is still an initialization signal, and therefore, the diode formed by the driving transistor DTFT through the fourth transistor T4 is turned on, so that the reference voltage Vref charges the storage capacitor Cst through the driving transistor DTFT.
  • the potential of the node P continues to rise.
  • the driving transistor DTFT is turned off, and charging is ended. Since the fifth transistor T5 is turned on, the data voltage input from the data signal terminal Data is transmitted to the first terminal of the storage capacitor Cst. Therefore, at the end of the threshold compensation phase, the voltage difference across the storage capacitor Cst is:
  • V(Cst) Vdata ⁇ (Vref ⁇
  • the source gate voltage Vsg of the driving transistor DTFT is:
  • the current flowing through the light emitting device OLED is:
  • I oled K (Vsg-
  • ) 2 K (Vdata-Vref +
  • ) 2 K (Vdata-Vref) 2, K is a constant related to the process and design.
  • the light-emitting current of the light-emitting device OLED is only related to the data voltage Vdata and the reference voltage Vref, and is independent of the threshold voltage Vthd of the driving transistor DTFT and the first power supply voltage VDD.
  • an embodiment of the present disclosure further provides a display device including any of the above pixel circuits.

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Abstract

一种像素电路及其驱动方法、显示装置。像素电路包括初始化信号端(Init)、扫描信号端(G(n))、数据信号端(Data)、第一电源端(ELVDD)、第二电源端(ELVSS)、参考电压端(Ref)、发光信号控制端(EM(n))、复位信号端(Reset)、数据写入子电路(3)、阈值补偿子电路(2)、发光控制子电路(1)、复位子电路(4)、存储电容器(Cst)、驱动晶体管(DTFT)以及发光器件(OLED)，其中阈值补偿子电路(2)配置成在存储电容器(Cst)中预存驱动晶体管(DTFT)的阈值电压。

Description

像素电路及其驱动方法、显示装置
相关申请的交叉引用
本申请要求享有2017年4月14日提交的中国专利申请No.201710245409.3的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示技术领域，并且特别地涉及一种像素电路及其驱动方法、包括所述像素电路的显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器相比现在的主流显示技术——薄膜晶体管液晶显示器(Thin Film Transisitor Liquid Crystal Display，TFT-LCD)而言，具有广视角、高亮度、高对比度、低能耗、体积更轻薄等优点，因而是目前平板显示技术关注的焦点。
OLED显示器的驱动方法可以分为被动矩阵式(PM，Passive Matrix)和主动矩阵式(AM，Active Matrix)两种。相比被动矩阵式驱动，主动矩阵式驱动具有显示信息量大、功耗低、器件寿命长、画面对比度高等优点。
尽管已经提出了许多用于主动矩阵式驱动方法的像素电路，但是其仍然必不可免的存在以下问题：驱动晶体管的阈值电压由于工艺制程的不均匀而导致显示面板不同位置的驱动晶体管存在差异。由于流过发光器件的电流与驱动晶体管的阈值电压相关，因此针对同样的数据驱动信号，发光器件的亮度可能不同，从而影响整个OLED显示器的画面均匀性及其发光质量。而且，由于显示器的内部电阻的存在，显示器的不同位置处的电源电压将存在差异。由于流过发光器件的电流与显示器的电源电压相关，因此这也会导致对于同样的数据信号而出现不同的发光器件亮度，从而影响显示画面的均匀性。
发明内容
本公开的目的在于提供一种改进的像素电路、像素驱动方法和显 示装置，其能够至少部分地缓解或消除以上提到的问题中的一个或多个。
根据本公开的一方面，提供了一种像素电路，包括：初始化信号端、扫描信号端、数据信号端、第一电源端、第二电源端、参考电压端、数据信号端、发光信号控制端、复位信号端、数据写入子电路、阈值补偿子电路、发光控制子电路、复位子电路、存储电容器、驱动晶体管以及发光器件。
数据写入子电路与扫描信号端、数据信号端和存储电容器的第一端连接，并且配置成在从扫描信号端输入的扫描信号的控制下，将从数据信号端输入的数据信号传输至存储电容器的第一端。
阈值补偿子电路与驱动晶体管的第一极、第二极、节点、扫描信号端、参考电压端和发光器件的第一极连接，并且配置成在存储电容器中预存驱动晶体管的阈值电压。
发光控制子电路与第一电源端、存储电容器的第一端、驱动晶体管的第一极以及发光控制信号端连接，并且配置成在从发光控制信号端输入的发光控制信号的控制下，控制驱动晶体管驱动发光器件发光。
复位子电路与所述节点、复位信号端以及初始化信号端连接，并且配置成在从复位信号端输入的复位信号的控制下，将从初始化信号端输入的初始化信号传输至所述节点。
存储电容器的第二端、驱动晶体管的控制极与所述节点连接，并且发光器件的第二极与第二电源端连接。
根据一些实施例，0＜Vref-Vss≤0.3，其中Vss为从所述第二电源端输入的电压值，Vref为从所述参考电压端输入的参考电压值。
根据一些实施例，所述发光控制子电路包括第一晶体管和第二晶体管。所述第一晶体管的第一极连接所述第二晶体管的第二极和第一电源端，所述第一晶体管的第二极连接所述阈值补偿子电路和所述驱动晶体管的第一极，并且所述第一晶体管的控制极连接发光控制信号端。所述第二晶体管的第一极连接所述存储电容器的第一端和所述数据写入子电路，所述第二晶体管的第二极连接所述发光控制子电路，并且所述第二晶体管的控制极连接所述发光控制信号端。
根据一些实施例，所述阈值补偿子电路包括第三晶体管和第四晶体管。所述第三晶体管的第一极连接参考电压端，所述第三晶体管的 第二极连接所述驱动晶体管的第二极和所述发光器件的第一极，并且所述第三晶体管的控制极连接扫描信号端。所述第四晶体管的第一极连接所述驱动晶体管的第一极，所述第四晶体管的第二极连接所述节点，并且所述第四晶体管的控制极连接所述扫描信号端。
根据一些实施例，所述阈值补偿子电路包括第三晶体管和第四晶体管。所述第三晶体管的第一极连接参考电压端，第二极连接所述驱动晶体管的第一极，并且所述第三晶体管的控制极连接扫描信号端。所述第四晶体管的第一极连接所述驱动晶体管的第二极，所述第四晶体管的第二极连接所述节点，并且所述第四晶体管的控制极连接所述扫描信号端。
根据一些实施例，所述数据写入子电路包括第五晶体管。所述第五晶体管的第一极连接数据信号端，所述第五晶体管的第二极连接所述存储电容器的第一端和所述发光控制子电路，并且所述第五晶体管的控制极连接扫描信号端。
根据一些实施例，所述复位子电路包括第六晶体管。所述第六晶体管的第一极连接初始化信号端，所述第六晶体管的第二极连接所述节点，并且所述第六晶体管的控制极连接复位信号端。
根据本公开的另一方面，提供了一种上述任一种像素电路的驱动方法。上述方法包括复位阶段、阈值补偿阶段和发光阶段。在所述复位阶段，在从复位信号端输入的复位信号的控制下，将从初始化信号端输入的初始化信号传输至节点。在所述阈值补偿阶段，在存储电容器中预存驱动晶体管的阈值电压。在所述发光阶段，在从发光控制信号端输入的发光控制信号的控制下，控制驱动晶体管驱动发光器件发光。
根据一些实施例，在所述阈值补偿阶段中，0＜Vref-Vss≤0.3，其中Vss为从所述第二电源端输入的电压值，Vref为从所述参考电压端输入的参考电压值。
根据本公开的又一方面，提供了一种显示装置，包括上述任一种像素电路。
根据本公开另外的方面，提供了一种像素电路，包括：初始化信号端、扫描信号端、数据信号端、第一电源端、第二电源端、参考电压端、数据信号端、发光信号控制端、复位信号端、第一晶体管、第 二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、驱动晶体管、存储电容器以及发光器件。
所述第一晶体管的第一极连接所述第二晶体管的第二极和第一电源端，所述第一晶体管的第二极连接所述第四晶体管的第一极和所述驱动晶体管的第一极，并且所述第一晶体管的控制极连接发光控制信号端。
所述第二晶体管的第一极连接所述存储电容器的第一端和所述第五晶体管的第二极，所述第二晶体管的第二极连接所述第一晶体管的第一极和第一电源端，并且所述第二晶体管的控制极连接所述发光控制信号端。
所述第三晶体管的第一极连接参考电压端，所述第三晶体管的第二极连接所述驱动晶体管的第二极和所述发光器件的第一极，并且所述第三晶体管的控制极连接扫描信号端。
所述第四晶体管的第一极连接所述驱动晶体管的第一极，所述第四晶体管的第二极连接第六晶体管的第二极和节点，并且所述第四晶体管的控制极连接所述扫描信号端。
所述第五晶体管的第一极连接数据信号端，所述第五晶体管的第二极连接所述存储电容器的第一端和所述第二晶体管的第一极，并且所述第五晶体管的控制极连接扫描信号端。
所述第六晶体管的第一极连接初始化信号端，所述第六晶体管的第二极连接所述节点，并且所述第六晶体管的控制极连接复位信号端。
所述存储电容器的第一端连接所述第二晶体管的第一极和所述第五晶体管的第二极，并且所述存储电容器的第二端连接所述节点。
所述驱动晶体管的第一极连接所述第一晶体管的第二极和所述第四晶体管的第一极，所述驱动晶体管的第二极连接所述发光器件的第一极和所述第三晶体管的第二极，并且所述驱动晶体管的控制极连接所述节点。
所述发光器件的第一极连接所述第三晶体管的第二极和所述驱动晶体管的第二极，并且所述发光器件的第二极连接第二电源端。
根据本公开另外的方面，提供了一种像素电路，包括：初始化信号端、扫描信号端、数据信号端、第一电源端、第二电源端、参考电压端、数据信号端、发光信号控制端、复位信号端、第一晶体管、第 二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、驱动晶体管、存储电容器、发光器件。
所述第一晶体管的第一极连接所述第二晶体管的第二极和第一电源端，所述第一晶体管的第二极连接所述第四晶体管的第一极和所述驱动晶体管的第一极，并且所述第一晶体管的控制极连接发光控制信号端。
所述第二晶体管的第一极连接所述存储电容器的第一端和所述第五晶体管的第二极，所述第二晶体管的第二极连接所述第一晶体管的第一极和第一电源端，并且所述第二晶体管的控制极连接所述发光控制信号端。
所述第三晶体管的第一极连接参考电压端，所述第三晶体管的第二极连接第一晶体管的第二极和所述驱动晶体管的第一极，并且所述第三晶体管的控制极连接扫描信号端。
所述第四晶体管的第一极连接所述驱动晶体管的第二极，所述第四晶体管的第二极连接节点，并且所述第四晶体管的控制极连接所述扫描信号线。
所述第五晶体管的第一极连接数据信号端，所述第五晶体管的第二极连接所述存储电容器的第一端和所述第二晶体管的第一极，并且所述第五晶体管的控制极连接扫描信号端。
所述第六晶体管的第一极连接初始化信号端，所述第六晶体管的第二极连接所述节点，并且所述第六晶体管的控制极连接复位信号端。
所述存储电容器的第一端连接所述第二晶体管的第一极和所述第五晶体管的第二极，并且所述存储电容器的第二端连接所述节点。
所述驱动晶体管的第一极连接所述第一晶体管的第二极和所述第三晶体管的第二极，所述驱动晶体管的第二极连接所述发光器件的第一极和所述第四晶体管的第一极，并且所述驱动晶体管的控制极连接所述节点。
所述发光器件的第一极连接所述第四晶体管的第一极和所述驱动晶体管的第二极，并且所述发光器件的第二极连接第二电源端。
在本实施例中的像素电路及其驱动方法中，通过在阈值补偿阶段中将驱动晶体管的阈值电压预先存储在存储电容器中，当在发光阶段驱动发光器件发光时，预存在存储电容器中的驱动晶体管的阈值电压 与驱动发光器件发光的电流中的阈值电压抵消，从而消除像素电路中驱动晶体管的阈值电压的变化对发光器件的发光亮度的影响，从而保证显示画面的质量。进一步地，在发光控制阶段，驱动晶体管DTFT的栅源电压与从第一电源端输入的电压值没有关系，因此，流过发光器件的电流不受显示装置的内阻影响，从而解决了IR-drop的问题。
附图说明
图1为常规的像素电路的电路图；
图2为根据本公开的实施例的像素电路的结构框图；
图3为根据本公开的实施例的一种像素电路的电路图；
图4为图3所示的像素电路的驱动方法的时序图；
图5为图3所示的像素电路在复位阶段的等效电路图；
图6为图3所示的像素电路在阈值补偿阶段的等效电路图；
图7为图3所示的像素电路在发光阶段的等效电路图；
[根据细则91更正 24.01.2018]　
[根据细则91更正 24.01.2018]　
图8为根据本公开的实施例的另一像素电路的电路图；以及
[根据细则91更正 24.01.2018]　
图9为图8所示的像素电路在阈值补偿阶段的等效电路图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
需要指出的是，本公开实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件。由于晶体管的源极和漏极在一定条件下是可以互换的，所以其源极、漏极从连接关系的描述上并无本质区别。在本公开实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，并且将栅极称为控制极。晶体管按照特性区分可以分为N型和P型，以下实施例中是以晶体管为P型晶体管进行说明的。当采用P型晶体管时，第一极为P型晶体管的源极，第二极为P型晶体管的漏极，并且当栅极输入低电平时，P型晶体管导通。N型晶体管的情况相反。本领域技术人员在本公开的教导下，可以采用N型晶体管来替换附图中的一个或多个P型晶体管而不脱离本公开的精神和范围。
图1图示了一种常规的像素电路的电路图。如图1所示，该像素电路包括：扫描信号端Vscan(n)、数据信号端Vdata、第一电源端VDD、第二电源端VSS、第一开关晶体管M1、驱动晶体管M2、存储电容器C1和发光器件D1。第一开关晶体管M1的控制极与扫描信号端Vscan(n)连接，第一开关晶体管M1的第一极与数据信号端Vdata连接，并且第一开关晶体管M1的第二极与驱动晶体管M2的控制极连接。驱动晶体管M2的第一极与第一电源端VDD连接，并且驱动晶体管M2的第二极与发光器件D1的一端连接。存储电容器C1连接在驱动晶体管M2的控制极与第一极之间。第一开关晶体管M1响应于从扫描信号端Vscan(n)接收到有效电平而导通，从而将从数据信号端Vdata输入的数据信号传输至驱动晶体管M2的控制极。驱动晶体管M2响应于接收到有效的数据信号而导通，从而将从电源端输入的电源信号传输至发光器件D1的一端，使得发光器件D1发光。流过发光器件D1的电流由驱动晶体管M2的第一极与控制极之间的电压差Vgs和驱动晶体管M2的阈值电压Vth决定，其中Vsg＝VDD-Vdata。存储电容器C1配置成在一帧的时间内维持驱动晶体管M2的第一极与控制极之间的电压差的稳定。
当多个如图1所示的像素电路级联时，从第n行像素电路的扫描信号端Vscan(n)接收到有效电平，从而通过从数据信号端Vdata输入的数据信号对存储电容器C1充电。然后，向第n行像素电路的扫描信号端Vscan(n)输入无效电平。此时，存储电容器C1维持充电电压，从而保证该行像素单元的驱动晶体管M2输出稳定的电流，使得该行像素单元的发光器件D1持续发光直到一帧时间结束。一帧时间通常为同一行像素电路从扫描信号端Vscan(n)接收到两次有效电平的时间。
在第n行像素单元的充电完成后，从第n+1行像素电路的扫描信号端Vscan(n+1)接收到有效电平，从而通过从数据信号端Vdata输入的数据信号对存储电容器C1充电。然后，向第n+1行像素电路的扫描信号端Vscan(n+1)输入无效电平。此时，存储电容器C1维持充电电压，从而保证该行像素单元的驱动晶体管M2输出稳定的电流，使得该行像素单元的发光器件D1持续发光直到一帧时间结束。如此依序下去，直到对最后一行像素单元充电完成后，从第一行像素单元开始重新充电。本发明人认识到，在如图1所示的像素电路中，由于流过发光器件D1 的电流与驱动晶体管M2的阈值电压和电源电压VDD相关，因此针对同样的数据驱动信号Vdata，发光器件D1的亮度可能不同，从而影响整个OLED显示器的画面均匀性及其发光质量。
有鉴于此，本公开的实施例提供了一种像素电路。如图2所示，该像素电路包括：初始化信号端Init、扫描信号端G(n)、数据信号端Data、第一电源端EL VDD、第二电源端EL VSS、参考电压端Ref、数据信号端Data、发光信号控制端EM(n)、复位信号端Reset、数据写入子电路3、阈值补偿子电路2、发光控制子电路1、复位子电路4、存储电容器Cst、驱动晶体管DTFT以及发光器件OLED。数据写入子电路3与扫描信号端G(n)、数据信号端Data和存储电容器Cst的第一端连接，并且配置成在从扫描信号端G(n)输入的扫描信号的控制下，将从数据信号端Data输入的数据信号传输至存储电容器Cst的第一端。阈值补偿子电路2与驱动晶体管DTFT的第一极、第二极、节点P、扫描信号端G(n)、参考电压端Ref和发光器件OLED的第一极连接，并且配置成在存储电容器Cst中预存驱动晶体管DTFT的阈值电压。发光控制子电路1与第一电源端EL VDD、存储电容器Cst的第一端、驱动晶体管DTFT的第一极以及发光控制信号端EM(n)连接，并且配置成在从发光控制信号端EM(n)输入的发光控制信号的控制下，控制驱动晶体管DTFT驱动发光器件OLED发光。复位子电路4与节点P、复位信号端Reset以及初始化信号端Init连接，并且配置成在从复位信号端Reset输入的复位信号的控制下，将从初始化信号端Init输入的初始化信号传输至节点P。存储电容器Cst的第二端、驱动晶体管DTFT的控制极与节点P连接，并且发光器件OLED的第二极与第二电源端EL VSS连接。在本实施例中的上述像素电路中，通过在阈值补偿阶段中将驱动晶体管DTFT的阈值电压预先存储在存储电容器Cst中，当在发光阶段驱动发光器件OLED发光时，预存在存储电容器Cst中的驱动晶体管DTFT的阈值电压与驱动发光器件OLED发光的电流中的阈值电压抵消，从而消除像素电路中驱动晶体管DTFT的阈值电压的变化对发光器件OLED的发光亮度的影响，从而保证显示画面的质量。进一步地，如以下详细描述的，在发光控制阶段，驱动晶体管DTFT的栅源电压与从第一电源端EL VDD输入的电压值没有关系，因此，流过发光器件OLED的电流不受显示装置的内阻影响，从而解决了IR-drop的问 题。
图3图示了根据本公开实施例的如图2所示的像素电路的具体电路图。如图3所示，发光控制子电路1可以包括第一晶体管T1和第二晶体管T2。第一晶体管T1的第一极连接第二晶体管T2的第二极和第一电源端EL VDD，第一晶体管T1的第二极连接阈值补偿子电路2和驱动晶体管DTFT的第一极，并且第一晶体管T1的控制极连接发光控制信号端EM(n)。第二晶体管T2的第一极连接存储电容器Cst的第一端和数据写入子电路3，第二晶体管T2的第二极连接发光控制子电路1，并且第二晶体管T2的控制极连接发光控制信号端EM(n)。
具体的，当从发光控制信号端输入有效电平时，第一晶体管T1和第二晶体管T2导通。此时，驱动晶体管DTFT的第一极和控制极通过存储电容器Cst连接。
可选地，如图3所示，阈值补偿子电路2包括第三晶体管T3和第四晶体管T4。第三晶体管T3的第一极连接参考电压端Ref，第三晶体管T3的第二极连接驱动晶体管DTFT的第二极和发光器件OLED的第一极，并且第三晶体管T3的控制极连接扫描信号端G(n)。第四晶体管T4的第一极连接驱动晶体管DTFT的第一极，第四晶体管T4的第二极连接节点P，并且第四晶体管T4的控制极连接扫描信号端G(n)。
具体的，当从扫描信号端G(n)输入有效电平时，第三晶体管T3、第四晶体管T4导通。此时，驱动晶体管DTFT管通过第四晶体管T4形成的二极管是导通的。由于第三晶体管T3导通，此时从参考电压端Ref输入的参考电压Vref通过驱动晶体管DTFT存储电容器Cst充电。随着电荷的不断流入，节点P的电位不断上升。当节点P的电位上升到Vref-|Vthd|(Vthd为驱动晶体管DTFT的阈值电压)时，驱动晶体管DTFT截止，充电结束。
可选地，如图3所示，数据写入子电路3包括第五晶体管T5。第五晶体管T5的第一极连接数据信号端Data，第五晶体管T5的第二极连接存储电容器Cst的第一端和发光控制子电路1，并且第五晶体管T5的控制极连接扫描信号端G(n)。
具体的，当从扫描信号端G(n)输入有效电平时，第五晶体管T5导通。此时，从数据信号端Data输入的数据信号Vdata通过第五晶体管T5传输至存储电容器Cst的第一端。
可选地，如图3所示，复位子电路4包括第六晶体管T6。第六晶体管T6的第一极连接初始化信号端Init，第六晶体管T6的第二极连接节点P，并且第六晶体管T6的控制极连接复位信号端Reset。
具体的，当从复位信号端Reset端输入有效电平时，第六晶体管T6导通。此时，从初始化信号端Init输入的初始化信号通过第六晶体管T6传输至节点P，以实现对节点P的复位。
如本文中所使用的，术语“有效电平”是指使得相应的晶体管导通的电平。例如，当相应的晶体管为P型晶体管时，有效电平为低电平；当相应的晶体管为N型晶体管时，有效电平为高电平。
相应的，本实施例提供了一种用于上述像素电路的驱动方法。该驱动方法包括：在复位阶段，在从复位信号端输入的复位信号的控制下，将从初始化信号端输入的初始化信号传输至节点；在阈值补偿阶段，在存储电容器中预存驱动晶体管的阈值电压；以及在发光阶段，在从发光控制信号端输入的发光控制信号的控制下，控制驱动晶体管驱动发光器件发光。
在本实施例中的上述像素电路的驱动方法中，通过在阈值补偿阶段中将驱动晶体管的阈值电压预先存储在存储电容器中，当在发光阶段驱动发光器件发光时，预存在存储电容器中的驱动晶体管的阈值电压与驱动发光器件发光的电流中的阈值电压抵消，从而消除像素电路中驱动晶体管的阈值电压的变化对发光器件的发光亮度的影响，从而保证显示画面的质量。进一步地，如以下详细描述的，在发光控制阶段，驱动晶体管DTFT的栅源电压与从第一电源端输入的电压值没有关系，因此，流过发光器件的电流不受显示装置的内阻影响，从而解决了IR-drop的问题。
为了使本实施例中的像素电路及其驱动方法更加清楚，以下结合图4所示的时序图来详细描述如图3所示的像素电路的工作原理和工作过程。
需要指出的是，以图3所示的各个晶体管为P型晶体管为例，此时各个晶体管的有效电平为低电平。
如图4所示，在复位阶段t1中，从复位信号端Reset输入低电平，从发光控制信号端Em(n)输入高电平，并且从扫描信号端G(n)输入高电平。此时，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四 晶体管T4、第五晶体管T5截止，并且第六晶体管T6导通。等效电路图如图5所示。由于第六晶体管T6导通，因此从初始化信号端Init输入的初始化信号通过第六晶体管T6传输至驱动晶体管DTFT的控制极，使得驱动晶体管DTFT的控制极复位，以便为下阶段的阈值补偿做准备。同时，由于第一晶体管T1截止，因此该阶段没有电流流过驱动晶体管DTFT，因此发光器件OLED不发光。
在阈值补偿阶段t2中，从复位信号端Reset输入高电平，从发光控制信号端Em(n)输入高电平，从扫描信号端G(n)输入低电平，并且从数据信号端Data输入高电平。此时，第一晶体管T1、第二晶体管T2、第六晶体管T6截止，并且第三晶体管T3、第四晶体管T4、第五晶体管T5导通。等效电路如图6所示。在该阶段中，由于第四晶体管T4导通，因此驱动晶体管DTFT为二极管连接。由于第三晶体管T3导通，从参考电平端Ref输入的参考电平Vref通过第三晶体管T3传输至发光器件OLED的第一极。
可选地，在示例实施例中，从第二电源端EL VSS输入的电压值为Vss，从参考电压端Ref输出的参考电压值为Vref，并且0＜Vref-Vss≤0.3。
在这样的实施例中，参考电压值Vref与从第二电源端EL VSS输入的电压值Vss较为接近，并且Vref和Vss之间的压差主要用于确保在阈值补偿阶段，没有电流流过发光器件OLED，同时参考电压Vref进入发光器件OLED的第一极可以对发光器件OLED进行复位，消除发光器件OLED内部发光界面上没有复合的载流子，缓解发光器件OLED的老化。当然，如本领域技术人员将认识到的，0.3V仅仅是一个示例。本领域技术人员根据本公开的教导，可以设置其它的电压差值。
在阈值补偿阶段t2中，将参考电压Vref设置成比从初始化信号端Init输入的初始化信号大驱动晶体管DTFT的阈值电压的绝对值以上。此时，驱动晶体管DTFT的控制极仍然为初始化信号，因此，驱动晶体管DTFT通过第四晶体管T4形成的二极管导通，使得参考电压Vref通过驱动晶体管DTFT对存储电容器Cst充电。随着电荷的不断流入，节点P的电位不断上升。当节点P的电位上升到比参考电压Vref小驱动晶体管DTFT的阈值电压时，驱动晶体管DTFT截止，充电结束。由于第五晶体管T5导通，因此从数据信号端Data输入的数据电压传 输至存储电容器Cst的第一端。因此，在阈值补偿阶段结束时，存储电容器Cst两端的电压差为：
V(Cst)＝Vdata-(Vref-|Vthd|)，其中Vthd为驱动晶体管DTFT的阈值电压。
在发光阶段t3中，从复位信号端Reset和扫描信号端G(n)输入高电平，从发光控制信号端Em(n)输入低电平。此时，第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6都截止，并且第一晶体管T1和第二晶体管T2导通。等效电路如图7所示。在该阶段中，从第一电源端EL VDD输入的第一电源电压VDD通过第二晶体管T2传输至存储电容器Cst的第一端。由于存储电容器Cst的自举作用，存储电容器Cst两端的电压差不变，即仍旧为V(Cst)＝Vdata-(Vref-|Vthd|)。因此，节点P的电位跳变成VDD-V(Cst)＝VDD-Vdata+(Vref-|Vthd|)＝VDD-Vdata+Vref-|Vthd|。由于驱动晶体管DTFT的控制极与第一节点P连接，因此驱动晶体管DTFT的控制极的电位同样为VDD-Vdata+Vref-|Vthd|。另一方面，从第一电源端EL VDD输入的第一电源电压VDD通过第一晶体管T1传输至驱动晶体管DTFT的第一极。因此，在该阶段中，驱动晶体管DTFT的源栅电压为：
Vsg＝VDD-(VDD-Vdata+Vref-|Vthd|)＝Vdata-Vref+|Vthd|，其中，Vth为驱动晶体管DTFT的阈值电压。
由于第一电源端EL VDD所输入的第一电源电压VDD可以保证驱动晶体管DTFT工作在饱和状态，因此流过发光器件OLED的电流为：
I oled＝K(Vsg-|Vth|) 2＝K(Vdata-Vref+|Vthd|-|Vthd|) 2＝K(Vdata-Vref) 2，其中K为与工艺和设计有关的常数。
由上式可以知道，发光器件OLED的发光电流只与数据电压Vdata和参考电压Vref有关，而与驱动晶体管DTFT的阈值电压Vthd和第一电源电源VDD均无关。
图8图示了根据本公开实施例的如图2所示的像素电路的另一具体电路图。图8所示的具体电路图与图3的不同之处仅在于阈值补偿子电路2。因此，以下仅对图8中的阈值补偿子电路2进行详细描述，而与图3相同的部分不再赘述。如图8所示，阈值补偿子电路2包括第三晶体管T3和第四晶体管T4。第三晶体管T3的控制极连接扫描信号端G(n)，第三晶体管T3的第一极连接参考电压端Ref，并且第三晶 体管T3的第二极连接驱动晶体管DTFT的第一极。第四晶体管T4的控制极连接扫描信号端G(n)，第四晶体管T4的第一极连接驱动晶体管DTFT的第二极，第四晶体管T4的第二极连接节点P。
相应地，对于如图8所示的像素电路的驱动方法，与上述驱动方法基本相同，区别仅在于阈值补偿阶段。因此以下仅结合图4对如图8所示的像素电路的阈值补偿阶段进行描述，其余阶段则不再重复说明。
如图4所示，在阈值补偿阶段t2中，从复位信号端Reset和发光控制信号端输入高电平，并且从扫描信号端G(n)输入低电平。此时，第一晶体管T1、第二晶体管T2、第六晶体管T6截止，并且第三晶体管T3、第四晶体管T4、第五晶体管T5导通。等效电路如图9所示。在该阶段中，由于第四晶体管导通，驱动晶体管DTFT为二极管连接。由于第三晶体管T3导通，从参考电压端Ref输入的参考电压传输至驱动晶体管DTFT的第一极。
可选地，在示例实施例中，从第二电源端EL VSS输入的电压值为Vss，从参考电压端Ref输出的参考电压值为Vref，并且0＜Vref-Vss≤0.3。
在这样的实施例中，参考电压值Vref与从第二电源端EL VSS输入的电压值Vss较为接近，并且Vref和Vss之间的压差主要用于确保在阈值补偿阶段，没有电流流过发光器件OLED，同时参考电压Vref进入发光器件OLED的第一极可以对发光器件OLED进行复位，消除发光器件OLED内部发光界面上没有复合的载流子，缓解发光器件OLED的老化。当然，如本领域技术人员将认识到的，0.3V仅仅是一个示例。本领域技术人员根据本公开的教导，可以设置其它的电压差值。
在阈值补偿阶段t2中，将参考电压Vref设置成比从初始化信号端Init输入的初始化信号大驱动晶体管DTFT的阈值电压的绝对值以上。此时，驱动晶体管DTFT的控制极仍然为初始化信号，因此，驱动晶体管DTFT通过第四晶体管T4形成的二极管导通，使得参考电压Vref通过驱动晶体管DTFT对存储电容器Cst充电。随着电荷的不断流入，节点P的电位不断上升。当节点P的电位上升到比参考电压Vref小驱动晶体管DTFT的阈值电压时，驱动晶体管DTFT截止，充电结束。由于第五晶体管T5导通，因此从数据信号端Data输入的数据电压传输至存储电容器Cst的第一端。因此，在阈值补偿阶段结束时，存储电 容器Cst两端的电压差为：
V(Cst)＝Vdata-(Vref-|Vthd|)；Vthd为驱动晶体管DTFT的阈值电压。
与之前的描述类似地，驱动晶体管DTFT的源栅电压Vsg为：
Vsg＝V(C st)＝Vdata-Vref+|Vthd|，其中，Vth为驱动晶体管DTFT的阈值电压。
由于从第一电源端EL VDD输入的第一电源电压VDD可以保证驱动晶体管DTFT工作在饱和状态，因此流过发光器件OLED的电流为：
I oled＝K(Vsg-|Vth|) 2＝K(Vdata-Vref+|Vthd|-|Vthd|) 2＝K(Vdata-Vref) 2，K为与工艺和设计有关的常数。
由上式可以知道，发光器件OLED的发光电流只与数据电压Vdata和参考电压Vref有关，而与驱动晶体管DTFT的阈值电压Vthd和第一电源电压VDD均无关。
进一步地，本公开的实施例还提供了一种包括上述任意一种像素电路的显示装置。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (12)

  1. 一种像素电路，包括：初始化信号端、扫描信号端、数据信号端、第一电源端、第二电源端、参考电压端、数据信号端、发光信号控制端、复位信号端、数据写入子电路、阈值补偿子电路、发光控制子电路、复位子电路、存储电容器、驱动晶体管以及发光器件，
    其中，
    数据写入子电路与扫描信号端、数据信号端和存储电容器的第一端连接，并且配置成在从扫描信号端输入的扫描信号的控制下，将从数据信号端输入的数据信号传输至存储电容器的第一端；
    阈值补偿子电路与驱动晶体管的第一极、第二极、节点、扫描信号端、参考电压端和发光器件的第一极连接，并且配置成在存储电容器中预存驱动晶体管的阈值电压；
    发光控制子电路与第一电源端、存储电容器的第一端、驱动晶体管的第一极以及发光控制信号端连接，并且配置成在从发光控制信号端输入的发光控制信号的控制下，控制驱动晶体管驱动发光器件发光；
    复位子电路与所述节点、复位信号端以及初始化信号端连接，并且配置成在从复位信号端输入的复位信号的控制下，将从初始化信号端输入的初始化信号传输至所述节点；
    存储电容器的第二端、驱动晶体管的控制极与所述节点连接；并且
    发光器件的第二极与第二电源端连接。
  2. 根据权利要求1所述的像素电路，其中，0＜Vref-Vss≤0.3，其中Vss为从所述第二电源端输入的电压值，Vref为从所述参考电压端输入的参考电压值。
  3. 根据权利要求1所述的像素电路，其中，所述发光控制子电路包括第一晶体管和第二晶体管，
    所述第一晶体管的第一极连接所述第二晶体管的第二极和第一电源端，所述第一晶体管的第二极连接所述阈值补偿子电路和所述驱动晶体管的第一极，并且所述第一晶体管的控制极连接发光控制信号端；
    所述第二晶体管的第一极连接所述存储电容器的第一端和所述数据写入子电路，所述第二晶体管的第二极连接所述发光控制子电路， 并且所述第二晶体管的控制极连接所述发光控制信号端。
  4. 根据权利要求1所述的像素电路，其中，所述阈值补偿子电路包括第三晶体管和第四晶体管，
    所述第三晶体管的第一极连接参考电压端，所述第三晶体管的第二极连接所述驱动晶体管的第二极和所述发光器件的第一极，并且所述第三晶体管的控制极连接扫描信号端；
    所述第四晶体管的第一极连接所述驱动晶体管的第一极，所述第四晶体管的第二极连接所述节点，并且所述第四晶体管的控制极连接所述扫描信号端。
  5. 根据权利要求1所述的像素电路，其中，所述阈值补偿子电路包括第三晶体管和第四晶体管，其中，
    所述第三晶体管的第一极连接参考电压端，第二极连接所述驱动晶体管的第一极，并且所述第三晶体管的控制极连接扫描信号端；
    所述第四晶体管的第一极连接所述驱动晶体管的第二极，所述第四晶体管的第二极连接所述节点，并且所述第四晶体管的控制极连接所述扫描信号端。
  6. 根据权利要求1所述的像素电路，其中，所述数据写入子电路包括第五晶体管，
    所述第五晶体管的第一极连接数据信号端，所述第五晶体管的第二极连接所述存储电容器的第一端和所述发光控制子电路，并且所述第五晶体管的控制极连接扫描信号端。
  7. 根据权利要求1所述的像素电路，其中，所述复位子电路包括第六晶体管，
    所述第六晶体管的第一极连接初始化信号端，所述第六晶体管的第二极连接所述节点，并且所述第六晶体管的控制极连接复位信号端。
  8. 一种如权利要求1-7中任一项所述的像素电路的驱动方法，包括复位阶段、阈值补偿阶段和发光阶段，其中
    在所述复位阶段，在从复位信号端输入的复位信号的控制下，将从初始化信号端输入的初始化信号传输至节点；
    在所述阈值补偿阶段，在存储电容器中预存驱动晶体管的阈值电压；并且
    在所述发光阶段，在从发光控制信号端输入的发光控制信号的控 制下，控制驱动晶体管驱动发光器件发光。
  9. 根据权利要求8所述的像素电路的驱动方法，其中，在所述阈值补偿阶段中，0＜Vref-Vss≤0.3，其中Vss为从所述第二电源端输入的电压值，Vref为从所述参考电压端输入的参考电压值。
  10. 一种显示装置，包括权利要求1-7中任一项所述的像素电路。
  11. 一种像素电路，包括：初始化信号端、扫描信号端、数据信号端、第一电源端、第二电源端、参考电压端、数据信号端、发光信号控制端、复位信号端、第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、驱动晶体管、存储电容器以及发光器件，其中，
    所述第一晶体管的第一极连接所述第二晶体管的第二极和第一电源端，所述第一晶体管的第二极连接所述第四晶体管的第一极和所述驱动晶体管的第一极，并且所述第一晶体管的控制极连接发光控制信号端；
    所述第二晶体管的第一极连接所述存储电容器的第一端和所述第五晶体管的第二极，所述第二晶体管的第二极连接所述第一晶体管的第一极和第一电源端，并且所述第二晶体管的控制极连接所述发光控制信号端；
    所述第三晶体管的第一极连接参考电压端，所述第三晶体管的第二极连接所述驱动晶体管的第二极和所述发光器件的第一极，并且所述第三晶体管的控制极连接扫描信号端；
    所述第四晶体管的第一极连接所述驱动晶体管的第一极，所述第四晶体管的第二极连接第六晶体管的第二极和节点，并且所述第四晶体管的控制极连接所述扫描信号端；
    所述第五晶体管的第一极连接数据信号端，所述第五晶体管的第二极连接所述存储电容器的第一端和所述第二晶体管的第一极，并且所述第五晶体管的控制极连接扫描信号端；
    所述第六晶体管的第一极连接初始化信号端，所述第六晶体管的第二极连接所述节点，并且所述第六晶体管的控制极连接复位信号端；
    所述存储电容器的第一端连接所述第二晶体管的第一极和所述第五晶体管的第二极，并且所述存储电容器的第二端连接所述节点；
    所述驱动晶体管的第一极连接所述第一晶体管的第二极和所述第 四晶体管的第一极，所述驱动晶体管的第二极连接所述发光器件的第一极和所述第三晶体管的第二极，并且所述驱动晶体管的控制极连接所述节点；并且
    所述发光器件的第一极连接所述第三晶体管的第二极和所述驱动晶体管的第二极，并且所述发光器件的第二极连接第二电源端。
  12. 一种像素电路，包括：初始化信号端、扫描信号端、数据信号端、第一电源端、第二电源端、参考电压端、数据信号端、发光信号控制端、复位信号端、第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、驱动晶体管、存储电容器、发光器件，其中，
    所述第一晶体管的第一极连接所述第二晶体管的第二极和第一电源端，所述第一晶体管的第二极连接所述第四晶体管的第一极和所述驱动晶体管的第一极，并且所述第一晶体管的控制极连接发光控制信号端；
    所述第二晶体管的第一极连接所述存储电容器的第一端和所述第五晶体管的第二极，所述第二晶体管的第二极连接所述第一晶体管的第一极和第一电源端，并且所述第二晶体管的控制极连接所述发光控制信号端；
    所述第三晶体管的第一极连接参考电压端，所述第三晶体管的第二极连接第一晶体管的第二极和所述驱动晶体管的第一极，并且所述第三晶体管的控制极连接扫描信号端；
    所述第四晶体管的第一极连接所述驱动晶体管的第二极，所述第四晶体管的第二极连接节点，并且所述第四晶体管的控制极连接所述扫描信号线；
    所述第五晶体管的第一极连接数据信号端，所述第五晶体管的第二极连接所述存储电容器的第一端和所述第二晶体管的第一极，并且所述第五晶体管的控制极连接扫描信号端；
    所述第六晶体管的第一极连接初始化信号端，所述第六晶体管的第二极连接所述节点，并且所述第六晶体管的控制极连接复位信号端；
    所述存储电容器的第一端连接所述第二晶体管的第一极和所述第五晶体管的第二极，并且所述存储电容器的第二端连接所述节点；
    所述驱动晶体管的第一极连接所述第一晶体管的第二极和所述第 三晶体管的第二极，所述驱动晶体管的第二极连接所述发光器件的第一极和所述第四晶体管的第一极，并且所述驱动晶体管的控制极连接所述节点；并且
    所述发光器件的第一极连接所述第四晶体管的第一极和所述驱动晶体管的第二极，并且所述发光器件的第二极连接第二电源端。
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