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WO2023011327A1 - 像素驱动电路及其驱动方法、显示基板和显示装置 - Google Patents

像素驱动电路及其驱动方法、显示基板和显示装置 Download PDF

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Publication number
WO2023011327A1
WO2023011327A1 PCT/CN2022/108763 CN2022108763W WO2023011327A1 WO 2023011327 A1 WO2023011327 A1 WO 2023011327A1 CN 2022108763 W CN2022108763 W CN 2022108763W WO 2023011327 A1 WO2023011327 A1 WO 2023011327A1
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WIPO (PCT)
Prior art keywords
transistor
voltage
node
control signal
signal terminal
Prior art date
Application number
PCT/CN2022/108763
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English (en)
French (fr)
Inventor
朱莉
曹席磊
张振华
李小鑫
袁长龙
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/280,153 priority Critical patent/US12211443B2/en
Priority to GB2314600.4A priority patent/GB2619479A/en
Publication of WO2023011327A1 publication Critical patent/WO2023011327A1/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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Definitions

  • the present disclosure relates to the display field, and in particular to a pixel driving circuit and a driving method thereof, a display substrate and a display device.
  • the threshold voltage of the driving transistor will be shifted due to the bias stress, and the degree of threshold voltage shift is also inconsistent with the bias stress of the driving transistor. That is, the electrical characteristics of the drive transistor are unstable, and serious hysteresis effects will occur at this time, resulting in afterimages, flickering and other defects.
  • an embodiment of the present disclosure provides a pixel driving circuit, including: a data writing circuit, a compensation control circuit, a light emission control circuit, a voltage stabilizing circuit, and a driving transistor, and the compensation control circuit is connected to the gate of the driving transistor
  • the pole is connected to the first node
  • the compensation control circuit and the data writing circuit are connected to the second node
  • the pole is connected to the third node;
  • the data writing circuit is connected to the first control signal terminal and the data line, and is configured to write the data voltage provided by the data line into the second node in response to the control of the signal of the first control signal terminal;
  • the light emission control circuit is connected to the light emission control signal terminal and the first pole of the light emitting device, configured to control the third node and the first pole of the light emitting device in response to the control of the signal of the light emission control signal terminal between on and off;
  • the compensation control circuit is connected to the second control signal terminal, the third control signal terminal and the third voltage input terminal, configured to obtain the threshold voltage of the driving transistor in response to the control of the signal of the second control signal terminal, and writing the third voltage provided by the third voltage input terminal into the second node in response to the control of the signal of the third control signal terminal, and according to the voltage change at the second node and the threshold voltage writing into the first node a light-emitting voltage capable of performing threshold compensation on the driving transistor;
  • the voltage stabilizing circuit is configured to maintain the stability of the voltage at the third node when the compensation control circuit writes the light-emitting voltage to the first node;
  • the driving transistor the first electrode of which is connected to the first voltage input end, is configured to generate a corresponding driving current according to the light emitting voltage.
  • the voltage stabilizing circuit includes: a fifth transistor
  • the control pole of the fifth transistor is connected to the first pole of the fourth control signal terminal, the first pole of the fifth transistor is connected to the third node, and the second pole of the fifth transistor is connected to the third node. Voltage input connection.
  • the voltage stabilizing circuit includes: a voltage stabilizing capacitor
  • a first end of the voltage stabilizing capacitor is connected to the third node, and a second end of the voltage stabilizing capacitor is connected to a fourth voltage input end.
  • the fourth voltage input terminal is the light emission control signal terminal.
  • the data writing circuit includes a first transistor
  • the control pole of the first transistor is connected to the first control signal terminal, the first pole of the first transistor is connected to the data line, and the second pole of the first transistor is connected to the second node .
  • the first transistor is a double-gate low temperature polysilicon transistor.
  • the reset compensation circuit includes: a second transistor, a third transistor, and a coupling capacitor;
  • the control pole of the second transistor is connected to the second control signal terminal, the first pole of the second transistor is connected to the first node, and the second pole of the second transistor is connected to the third node connect;
  • the control pole of the third transistor is connected to the third control signal terminal, the first pole of the third transistor is connected to the third voltage input terminal, and the second pole of the third transistor is connected to the first Two-node connection;
  • a first end of the coupling capacitor is connected to the first node, and a second end of the coupling capacitor is connected to the second node.
  • the data writing circuit includes a first transistor
  • the control pole of the first transistor is connected to the first control signal terminal, the first pole of the first transistor is connected to the data line, and the second pole of the first transistor is connected to the second node ;
  • the first transistor is a low temperature polysilicon transistor, and the third transistor is an oxide transistor;
  • the first control signal terminal and the third control signal terminal are the same control signal terminal.
  • the pixel driving circuit further includes: a first reset circuit
  • the first reset circuit includes: a sixth transistor
  • the control electrode of the sixth transistor is connected to the fifth control signal terminal, the first electrode of the sixth transistor is connected to the first electrode of the light emitting device, and the second electrode of the sixth transistor is connected to the The third voltage input terminal is connected;
  • Both the second transistor and the sixth transistor are low temperature polysilicon transistors or both are oxide transistors;
  • the second control signal terminal and the fifth control signal terminal are the same control signal terminal.
  • the first transistor is a double-gate low temperature polysilicon transistor.
  • the light emission control circuit includes: a fourth transistor
  • the control pole of the fourth transistor is connected to the light-emitting control signal terminal, the first pole of the fourth transistor is connected to the third node, and the second pole of the fourth transistor is connected to the first pole of the light-emitting device.
  • the pixel driving circuit further includes: a first reset circuit
  • the first reset circuit is connected to the fifth control signal terminal, the third voltage input terminal and the first pole of the light emitting device, and is configured to reduce the third voltage to The third voltage provided by the input end is written into the first pole of the light emitting device.
  • the first reset circuit includes: a sixth transistor
  • the control electrode of the sixth transistor is connected to the fifth control signal terminal, the first electrode of the sixth transistor is connected to the first electrode of the light emitting device, and the second electrode of the sixth transistor is connected to the The third voltage input terminal is connected.
  • the pixel driving circuit further includes: a second reset circuit
  • the second reset circuit is connected to the sixth control signal terminal, the third voltage input terminal and the first node, configured to input the third voltage in response to the control of the signal of the sixth control signal terminal
  • the third voltage provided by the terminal is written into the first node.
  • the second reset circuit includes: a seventh transistor
  • the control pole of the seventh transistor is connected to the sixth control signal terminal, the first pole of the seventh transistor is connected to the third voltage input terminal, and the second pole of the seventh transistor is connected to the first voltage input terminal. A node connection.
  • the seventh transistor is an oxide transistor.
  • an embodiment of the present disclosure further provides a driving method of a pixel driving circuit, the pixel driving circuit is the pixel driving circuit provided in the first aspect, and the driving method includes:
  • the data writing circuit writes the data voltage provided by the data line into the second node in response to the control of the signal of the first control signal terminal, and the compensation control circuit responds to the second node Controlling the signal at the signal terminal to obtain the threshold voltage of the drive transistor;
  • the compensation control circuit writes the third voltage provided by the third voltage input terminal into the second node in response to the control of the signal of the third control signal terminal, and
  • the voltage change at the second node and the threshold voltage are written into the first node with a light-emitting voltage capable of threshold compensation for the driving transistor, and the voltage stabilizing circuit maintains the stability of the voltage at the third node;
  • the light-emitting control circuit conducts the connection between the third node and the first electrode of the light-emitting device in response to the control of the signal of the light-emitting control signal terminal, and the driving transistor generates a corresponding voltage according to the light-emitting voltage. driving current to drive the light emitting device to emit light.
  • an embodiment of the present disclosure further provides a display substrate, including: the pixel driving circuit provided in the second aspect above.
  • an embodiment of the present disclosure further provides a display device, including: the display substrate as provided in the above third aspect.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure
  • FIG. 3a is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 3b is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 5 is a working timing diagram of the pixel driving circuit shown in FIG. 4;
  • FIG. 6 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 9 is a working timing diagram of the pixel driving circuit shown in FIG. 7;
  • FIG. 10 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a working timing diagram of the pixel driving circuit shown in FIG. 10;
  • FIG. 13 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 16 is a working timing diagram of the pixel driving circuit shown in FIG. 15;
  • FIG. 17 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 18 is a working timing diagram of the pixel driving circuit shown in FIG. 17;
  • FIG. 19 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 20 is a working timing diagram of the pixel driving circuit shown in FIG. 19;
  • FIG. 21 is a flowchart of a driving method of a pixel driving circuit provided by an embodiment of the present disclosure.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same or similar characteristics. Since the source and drain of the transistors used are symmetrical, their There is no difference between source and drain. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of them is called the first pole, the other is called the second pole, and the gate is called the control pole. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. When a P-type transistor is used, the first pole is the source of the P-type transistor, and the second pole is the drain of the P-type transistor. The situation of the N-type transistor is opposite. .
  • the "active level" in this disclosure refers to the level capable of controlling the conduction of the corresponding transistor; specifically, for a P-type transistor, its corresponding active level is a low level; for an N-type transistor, its corresponding Active level is high level.
  • the working process of the pixel drive circuit with internal compensation function is roughly as follows: in the compensation phase, the threshold voltage of the drive transistor is obtained; Light-emitting voltage, and write the light-emitting voltage to the gate of the driving transistor; in the light-emitting stage, conduction between the drain of the driving transistor and the light-emitting device, so that the driving transistor can output a driving current to the light-emitting device.
  • the drain of the driving transistor is generally in a floating state; since the gate and drain of the driving transistor There is a parasitic capacitance between them, so in the process of writing the luminous voltage to the driving transistor, the voltage at the drain of the driving transistor will change accordingly. Changes in the drain voltage of the driving transistor will cause inconsistent bias stress on the driving transistor, and the threshold voltage of the driving transistor will be seriously shifted, resulting in a serious hysteresis effect, which will lead to afterimages, flickering and other undesirable effects.
  • the light-emitting device in the present disclosure refers to a current-driven light-emitting element including an organic light-emitting diode (Organic Light Emitting Diode, OLED for short), a light-emitting diode (Light Emitting Diode, LED for short), and the like.
  • An OLED is taken as an example for an exemplary description, wherein the first pole and the second pole of the light emitting device refer to an anode and a cathode respectively.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • the pixel driving circuit includes: a data writing circuit 1, a compensation control circuit 2, a light emission control circuit 3, and a voltage stabilizing circuit 4 and the drive transistor DTFT, the compensation control circuit 2 and the gate of the drive transistor DTFT are connected to the first node N1, the compensation control circuit 2 and the data writing circuit 1 are connected to the second node N2, the compensation control circuit 2, and the light emission control circuit 3 , the voltage stabilizing circuit 4 and the second pole of the driving transistor DTFT are connected to the third node N3.
  • the data writing circuit 1 is connected with the first control signal terminal SC1 and the data line Data, and the data writing circuit 1 is configured to write the data voltage provided by the data line Data into the control signal of the first control signal terminal SC1.
  • the light emission control circuit 3 is connected to the light emission control signal terminal EM and the first pole of the light emitting device OLED, and the light emission control circuit 3 is configured to control the third node N3 and the first electrode of the light emitting device OLED in response to the control of the signal of the light emission control signal terminal EM. On and off between one pole.
  • the compensation control circuit 2 is connected to the second control signal terminal SC2, the third control signal terminal SC3 and the third voltage input terminal, and the compensation control circuit 2 is configured to obtain the driving transistor DTFT in response to the control of the signal of the second control signal terminal SC2. Threshold voltage, and in response to the control of the signal of the third control signal terminal SC3 write the third voltage provided by the third voltage input terminal into the second node N2, and write the third voltage to the first node N2 according to the voltage change at the second node N2 and the threshold voltage to the first
  • the node N1 is written with a light emitting voltage capable of threshold compensation of the driving transistor DTFT.
  • the voltage stabilizing circuit 4 is configured to maintain the stability of the voltage at the third node N3 when the compensation control circuit 2 writes the light emitting voltage to the first node N1 .
  • the first pole of the driving transistor DTFT is connected to the first voltage input terminal, and the driving transistor DTFT is configured to generate a corresponding driving current according to the light emitting voltage.
  • the voltage stabilizing circuit 4 can write the light emitting voltage to the gate of the driving transistor DTFT by the compensation control circuit 2, Weaken or even completely eliminate the influence of the parasitic capacitance between the gate and the drain of the driving transistor DTFT on the voltage at the drain of the driving transistor DTFT, so as to maintain the stability of the voltage at the third node N3, so that the bias voltage of the driving transistor DTFT
  • the stress is basically the same, the threshold voltage of the driving transistor DTFT is basically kept stable, and the influence of the hysteresis effect can be weakened, thereby effectively improving the afterimage and flickering problems of the display device.
  • FIG. 2 is a schematic diagram of another circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure.
  • the voltage stabilizing circuit 4 includes: a fifth transistor T5; a control electrode of the fifth transistor T5 It is connected to the first pole of the fourth control signal terminal SC4, the first pole of the fifth transistor T5 is connected to the third node N3, and the second pole of the fifth transistor T5 is connected to the third voltage input terminal.
  • the signal of the fourth control signal terminal SC4 is used to control the fifth transistor T5 to be turned on, so as to transfer the third voltage provided by the third voltage input terminal.
  • a voltage (at least a constant voltage in the luminous voltage writing phase) is written into the third node N3; that is, during the luminous voltage writing phase, the voltage at the third node N3 is always the third voltage; that is, in In the light-emitting voltage writing phase, the voltage stabilizing circuit 4 in the embodiment of the present disclosure can completely eliminate the influence of the parasitic capacitance between the gate and the drain of the driving transistor DTFT on the voltage at the drain of the driving transistor DTFT.
  • Fig. 3a is a schematic diagram of another circuit structure of the pixel driving circuit provided by the embodiment of the present disclosure, as shown in Fig. 3a, which is different from the case where the voltage stabilizing circuit 4 in Fig. 2 includes a fifth transistor T5, as shown in Fig. 3a
  • the voltage stabilizing circuit 4 in the embodiment includes: a voltage stabilizing capacitor C2; a first end of the voltage stabilizing capacitor C2 is connected to the third node N3, and a second end of the voltage stabilizing capacitor C2 is connected to the fourth voltage input end.
  • the fourth voltage provided by the fourth voltage input terminal is a constant voltage at least in the writing phase of the light emitting voltage.
  • the voltage stabilizing capacitor C2 by setting the voltage stabilizing capacitor C2 at the third node N3, the influence of the parasitic capacitance between the gate and the drain of the drive transistor DTFT on the voltage at the third node N3 can be effectively weakened, so that the light-emitting voltage In the writing phase, the voltage at the third node N3 only slightly changes or remains basically unchanged. That is to say, in the phase of writing the luminous voltage, the voltage stabilizing circuit 4 in the embodiment of the present disclosure can completely and effectively improve the influence of the parasitic capacitance between the gate and the drain of the driving transistor DTFT on the voltage at the drain of the driving transistor DTFT.
  • FIG. 3b is a schematic diagram of another circuit structure of the pixel driving circuit provided by an embodiment of the present disclosure. As shown in FIG. Control signal terminal EM. That is to say, the second end of the voltage stabilizing capacitor C2 can be directly connected to the light emission control signal terminal EM configured by the light emission control circuit 3 .
  • the above-mentioned design of connecting the second terminal of the voltage stabilizing capacitor C2 to the light emission control signal terminal EM can effectively reduce the types of signals required for the pixel drive circuit on the one hand, and is conducive to simplifying product design; on the other hand, due to the second capacitor The distance to the lighting control circuit 3 is relatively short, so the connection between the second terminal of the second capacitor and the lighting control signal terminal EM is relatively easy to realize in actual products.
  • FIG. 4 is a schematic diagram of another circuit structure of the pixel driving circuit provided by an embodiment of the present disclosure.
  • the data writing circuit 1 includes a first transistor T1; wherein, the first transistor T1 The control electrode is connected to the first control signal terminal SC1, the first electrode of the first transistor T1 is connected to the data line Data, and the second electrode of the first transistor T1 is connected to the second node N2.
  • the bit compensation circuit includes: a second transistor T2, a third transistor T3, and a coupling capacitor C1; wherein, the control electrode of the second transistor T2 is connected to the second control signal terminal SC2, and the first electrode of the second transistor T2 It is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the control electrode of the third transistor T3 is connected to the third control signal terminal SC3, the first electrode of the third transistor T3 is connected to the third voltage input end, and the second electrode of the third transistor T3 is connected to the second node N2.
  • a first end of the coupling capacitor C1 is connected to the first node N1, and a second end of the coupling capacitor C1 is connected to the second node N2.
  • the light emission control circuit 3 includes: a fourth transistor T4; wherein, the control electrode of the fourth transistor T4 is connected to the light emission control signal terminal EM, the first electrode of the fourth transistor T4 is connected to the third node N3, and the fourth transistor T4 is connected to the third node N3.
  • the second pole of the four-transistor T4 is connected to the first pole of the light emitting device OLED.
  • FIG. 4 exemplifies the case where the transistors in the pixel driving circuit are all P-type transistors, for example, all the transistors in the pixel driving circuit are low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short) transistors.
  • the first voltage input end provides a first voltage VDD
  • the second voltage input end provides a second voltage VSS
  • the third voltage input end provides a third voltage Vref.
  • the third voltage Vref may be equal to or slightly lower than the first voltage VDD.
  • Fig. 5 is a working timing diagram of the pixel driving circuit shown in Fig. 4. As shown in Fig. 5, the working process of the pixel driving circuit shown in Fig. 4 may include the following stages:
  • the signal provided by the first control signal terminal SC1 is high level
  • the signal provided by the second control signal terminal SC2 is low level
  • the signal provided by the third control signal terminal SC3 is low level
  • the signal provided by the terminal EM is low level
  • the signal provided by the fourth control signal terminal SC4 is high level.
  • the second transistor T2, the third transistor T3 and the fourth transistor T4 are all turned on, and the first transistor T1 and the fifth transistor T5 are all turned off.
  • the third voltage Vref is written into the second node N2 through the third transistor T3 to reset the second node N2; the voltage VSS+Voled at the first pole of the light emitting device OLED is written through the fourth transistor T4 and the second transistor T2 input to the first node N1 to reset the first node N1; wherein, Voled is the turn-on voltage of the light emitting device OLED (the magnitude of Voled changes with the working state of the light emitting device OLED).
  • the signal provided by the first control signal terminal SC1 is low level
  • the signal provided by the second control signal terminal SC2 is low level
  • the signal provided by the third control signal terminal SC3 is high level
  • the light control signal The signal provided by terminal EM is high level
  • the signal provided by the fourth control signal terminal SC4 is high level.
  • the data voltage Vdata is written into the second node N2N2 through the first transistor T1; the first voltage VDD is charged to the first node N1 through the driving transistor DTFT and the second transistor T2, when the voltage at the first node N1 is VDD+Vth, The driving transistor DTFT is turned off, and the charging ends; wherein, Vth is the threshold voltage of the driving transistor DTFT. At this time, the voltage difference between the two ends of the coupling capacitor C1 is VDD+Vth-Vdata.
  • the signal provided by the first control signal terminal SC1 is high level
  • the signal provided by the second control signal terminal SC2 is high level
  • the signal provided by the third control signal terminal SC3 is low level
  • the signal provided by the light emission control signal terminal EM is high level
  • the signal provided by the fourth control signal terminal SC4 is low level.
  • the second transistor T2 is turned off, and the first node N1 is in a floating state.
  • the third voltage Vref is written into the second node N2 through the third transistor T3, the voltage at the second node N2 changes from Vdata to Vref, and under the bootstrap action of the coupling capacitor C1, the voltage at the first node N1 changes from VDD+Vth to It is VDD+Vth+Vref-Vdata. That is, the light emitting voltage written into the first node N1 is VDD+Vth+Vref ⁇ Vdata.
  • the third voltage Vref is written into the third node N3 through the fifth transistor T5, and the voltage at the third node N3 is always maintained at Vref, that is,
  • the bias stress of the driving transistor DTFT is basically the same, the threshold voltage of the driving transistor DTFT is basically stable, and the influence of the hysteresis effect can be weakened.
  • the signal provided by the first control signal terminal SC1 is high level
  • the signal provided by the second control signal terminal SC2 is high level
  • the signal provided by the third control signal terminal SC3 is low level
  • the light-emitting control signal The signal provided by the terminal EM is low level
  • the signal provided by the fourth control signal terminal SC4 is high level.
  • the third transistor T3 continuously writes the third voltage Vref to the second node N2 to maintain the stability of the voltage at the second node N2, which is conducive to maintaining the stability of the voltage at the first node N1; at the same time, the driving transistor DTFT according to its own The gate-source voltage Vgs outputs the driving current I.
  • K is a constant (the size is related to the electrical characteristics of the driving transistor DTFT). It can be seen from the above formula that the driving current I output by the driving transistor DTFT is only related to the data voltage Vdata and the third voltage Vref, and has nothing to do with the threshold voltage Vth of the driving transistor DTFT, so that the driving current I flowing through the light emitting device OLED can be prevented from being affected by the threshold value. The influence of voltage unevenness and drift effectively improves the uniformity of the driving current flowing through the light emitting device OLED.
  • the above-mentioned reset phase may not be required; that is, the working process of the pixel driving circuit only includes the above-mentioned compensation phase t2, light-emitting voltage writing phase t3 and light-emitting phase t4.
  • FIG. 4 exemplarily shows the situation that the voltage stabilizing circuit 4 includes the fifth transistor T5.
  • FIG. 6 is a schematic diagram of another circuit structure of the pixel driving circuit provided by the embodiment of the present disclosure. As shown in FIG. It is the same in FIG. 4 , but the voltage stabilizing circuit 4 in FIG. 6 includes a voltage stabilizing capacitor C2. FIG. 6 also only exemplarily shows the situation that the second end of the voltage stabilizing capacitor C2 is connected to the light emission control signal end EM.
  • the working sequence of the pixel driving circuit shown in FIG. 6 can also be as shown in FIG. 5 , and the specific process will not be repeated here.
  • FIG. 7 is a schematic diagram of another circuit structure of the pixel driving circuit provided by the embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of another circuit structure of the pixel driving circuit provided by the embodiment of the disclosure.
  • the pixel driving circuit not only includes a data writing circuit 1 , a compensation control circuit 2 , a light emission control circuit 3 and a voltage stabilizing circuit 4 , but also includes: a first reset circuit 5 .
  • the first reset circuit 5 is connected with the fifth control signal terminal SC5, the third voltage input terminal and the first pole of the light-emitting device OLED, and is configured to control the third voltage input terminal in response to the control signal of the fifth control signal terminal SC5.
  • the provided third voltage is written into the first pole of the light emitting device OLED.
  • the first pole of the light emitting device OLED can be reset in the reset phase.
  • the first reset circuit 5 includes: a sixth transistor T6; the control electrode of the sixth transistor T6 is connected to the fifth control signal terminal SC5, and the first electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device OLED connected, the second pole of the sixth transistor T6 is connected to the third voltage input terminal.
  • Fig. 9 is a timing diagram of the operation of the pixel driving circuit shown in Fig. 7.
  • the working process of the pixel driving circuit shown in Fig. 7 may include: a reset phase t1, a compensation phase t2, and a lighting voltage writing phase t3 and light-emitting phase t4.
  • the working sequence of the first control signal terminal SC1, the second control signal terminal SC2, the third control signal terminal SC3, the light emission control signal terminal EM and the fourth control signal terminal SC4 shown in FIG. 9 is the same as that shown in FIG. 5
  • the situation is the same, and only the working timing of the fifth control signal terminal SC5 in each stage will be described in detail below.
  • the signal provided by the fifth control signal terminal SC5 is at a low level, the sixth transistor T6 is turned on, and the third working voltage Vref is written into the first pole of the light emitting device OLED through the sixth transistor T6 to control the light emission.
  • the first pole of the device OLED is reset.
  • the third working voltage Vref can also be written into the first node N1 through the fourth transistor T4 and the second transistor T2, so as to reset the first node N1.
  • the fifth control signal terminal SC5 provides a low level
  • the sixth transistor T6 is turned off.
  • the fifth control signal terminal SC5 in FIG. 9 may also provide a low level during the compensation phase t2 and/or the luminescence voltage writing phase t3, so as to continuously control the first pole of the light emitting device OLED. This situation also belongs to the protection scope of the present disclosure.
  • FIG. 10 is a schematic diagram of another circuit structure of the pixel driving circuit provided by the embodiment of the disclosure
  • FIG. 11 is a schematic diagram of another circuit structure of the pixel driving circuit provided by the embodiment of the disclosure, as shown in FIG. 10 and FIG. 11 , in some embodiments, the pixel driving circuit not only includes a data writing circuit 1 , a compensation control circuit 2 , a light emission control circuit 3 and a voltage stabilizing circuit 4 , but also includes a second reset circuit 6 .
  • the second reset circuit 6 is connected to the sixth control signal terminal SC6, the third voltage input terminal and the first node N1, and the second reset circuit 6 is configured to control the third voltage input terminal in response to the control signal of the sixth control signal terminal SC6.
  • the provided third voltage is written into the first node N1.
  • the first node N1 can be reset in the reset phase. At this time, it is not necessary to use the voltage at the first pole of the light-emitting device OLED to reset the first node N1.
  • the light emission control circuit 3 does not need to conduct conduction between the third node N3 and the first pole of the light emitting device OLED.
  • the second reset circuit 6 includes: a seventh transistor T7; the control pole of the seventh transistor T7 is connected to the sixth control signal terminal SC6, the first pole of the seventh transistor T7 is connected to the third voltage input terminal, The second pole of the seventh transistor T7 is connected to the first node N1.
  • Fig. 12 is a timing diagram of the operation of the pixel driving circuit shown in Fig. 10.
  • the working process of the pixel driving circuit shown in Fig. 10 may include: a reset phase t1, a compensation phase t2, and a lighting voltage writing phase t3 and light-emitting phase t4.
  • the working sequence of the first control signal terminal SC1, the second control signal terminal SC2, the third control signal terminal SC3 and the fourth control signal terminal SC4 shown in FIG. 12 is the same as that of the first control signal terminal SC1 shown in FIG.
  • the second control signal terminal SC2 , the third control signal terminal SC3 and the fourth control signal terminal SC4 have the same working sequence.
  • the working timings of the light emission control signal terminal EM and the sixth control signal terminal SC6 at each stage will be described in detail.
  • the signal provided by the light emission control signal terminal EM is at high level
  • the signal provided by the sixth control signal terminal SC6 is at low level
  • the seventh transistor T7 is in the on state
  • the fourth transistor T4 is in the off state.
  • the third voltage Vref is written into the first node N1 through the seventh transistor T7 to reset the first node N1.
  • the signal provided by the luminescence control signal terminal EM is at a high level, and the signal provided by the sixth control signal terminal SC6 is at a high level; the seventh transistor T7 is in an off state, and the fourth transistor T4 is off.
  • the signal provided by the light-emitting control signal terminal EM is at low level, and the signal provided by the sixth control signal terminal SC6 is at high level; the fourth transistor T4 is in the on state, and the seventh transistor T7 is in the off state.
  • FIG. 13 is a schematic diagram of another circuit structure of the pixel driving circuit provided by the embodiment of the disclosure
  • FIG. 14 is a schematic diagram of another circuit structure of the pixel driving circuit provided by the embodiment of the disclosure, as shown in FIG. 13 and FIG. 14 , in some embodiments, the pixel driving circuit not only includes a data writing circuit 1 , a compensation control circuit 2 , a light emission control circuit 3 and a voltage stabilizing circuit 4 , but also includes the above-mentioned first reset circuit 5 and second reset circuit 6 .
  • FIG. 15 is another schematic circuit structure diagram of a pixel driving circuit provided by an embodiment of the present disclosure.
  • the first transistor T1 is a double-gate low-temperature polysilicon transistor.
  • the low-temperature polysilicon transistor has the characteristics of fast response speed, which enables the data voltage Vdata to be quickly written into the second node N2 during the compensation stage, so as to meet the high requirements of high-resolution products on the data voltage writing speed.
  • the double-gate structure design of the low-temperature polysilicon transistor can effectively reduce the leakage of the second node N2 through the first transistor T1.
  • the third transistor T3 is an oxide transistor (N-type transistor, specifically, a low-temperature polysilicon oxide transistor).
  • object transistor the first control signal terminal SC1 and the third control signal terminal SC3 are the same control signal terminal.
  • the oxide transistor has a small leakage current, which can effectively reduce the leakage current of the second node N2 passing through the third transistor T3.
  • designing the first control signal terminal SC1 and the third control signal terminal SC3 as the same control signal terminal can effectively reduce the types of signals required to be configured by the pixel driving circuit, and is beneficial to simplify product design.
  • both the second transistor T2 and the sixth transistor T6 are low temperature polysilicon transistors, and the second control signal terminal SC2 and the fifth control signal terminal SC5 are the same control signal terminal.
  • designing the sixth transistor T6 as a low-temperature polysilicon transistor can enable the third voltage Vref to be quickly written into the first electrode of the light-emitting device OLED during the reset phase, so the duration of the reset phase can be designed to be relatively short To meet the high reset speed requirements of high-resolution products; designing the second transistor T2 as a low-temperature polysilicon transistor can quickly obtain the threshold voltage of the driving transistor DTFT during the compensation phase, so the duration of the compensation phase can be designed It is relatively short to meet the high requirements of high-resolution products on compensation speed; at the same time, the second control signal terminal SC2 and the fifth control signal terminal SC5 are designed as the same control signal terminal, which can effectively reduce the pixel driving circuit.
  • the types of signals that need to be configured are conducive to simplifying product design.
  • the second node connected to the first node N1 can be
  • the transistor T2 is designed as a double-gate low-temperature polysilicon transistor, which can effectively reduce the leakage of the first node N1 through the second transistor T2.
  • FIG. 16 is a working timing diagram of the pixel driving circuit shown in FIG. 15. As shown in FIG. 16, the working process of the pixel driving circuit shown in FIG. 16 may include the following stages:
  • the signal provided by the first control signal terminal SC1 (the third control signal terminal SC3) is at a high level
  • the signal provided by the second control signal terminal SC2 (the fifth control signal terminal SC5) is at a low level
  • the light is emitted.
  • the signal provided by the control signal terminal EM is low level
  • the signal provided by the fourth control signal terminal SC4 is high level.
  • the second transistor T2, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are all turned on, and the first transistor T1 and the fifth transistor T5 are all turned off.
  • the third voltage Vref is written into the second node N2 through the third transistor T3 to reset the second node N2; the third voltage Vref is written into the first pole of the light emitting device OLED through the sixth transistor T6 to reset the light emitting device
  • the first pole of the OLED is reset, and at the same time, writes to the first node N1 through the fourth transistor T4 and the second transistor T2, so as to reset the first node N1.
  • the signal provided by the first control signal terminal SC1 (third control signal terminal SC3) is at low level
  • the signal provided by the second control signal terminal SC2 (fifth control signal terminal SC5) is at low level
  • light is emitted.
  • the signal provided by the control signal terminal EM is at a high level
  • the signal provided by the fourth control signal terminal SC4 is at a high level.
  • the first transistor T1, the second transistor T2 and the sixth transistor T6 are all turned on
  • the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are all turned off.
  • the data voltage Vdata is written into the second node N2N2 through the first transistor T1; the first voltage VDD is charged to the first node N1 through the driving transistor DTFT and the second transistor T2, when the voltage at the first node N1 is VDD+Vth, The driving transistor DTFT is turned off, and the charging is completed; at this time, the voltage difference between the two ends of the coupling capacitor C1 is VDD+Vth-Vdata.
  • the signal provided by the first control signal terminal SC1 (third control signal terminal SC3) is high level, and the signal provided by the second control signal terminal SC2 (fifth control signal terminal SC5) is high level. level, the signal provided by the light emitting control signal terminal EM is at high level, and the signal provided by the fourth control signal terminal SC4 is at low level.
  • both the third transistor T3 and the fifth transistor T5 are turned on, and the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the sixth transistor T6 are all turned off.
  • the second transistor T2 is turned off, and the first node N1 is in a floating state.
  • the third voltage Vref is written into the second node N2 through the third transistor T3, the voltage at the second node N2 changes from Vdata to Vref, and under the bootstrap action of the coupling capacitor C1, the voltage at the first node N1 changes from VDD+Vth to It is VDD+Vth+Vref-Vdata. That is, the light emitting voltage written into the first node N1 is VDD+Vth+Vref ⁇ Vdata.
  • the third voltage Vref is written into the third node N3 through the fifth transistor T5, and the voltage at the third node N3 is always maintained at Vref, that is,
  • the bias stress of the driving transistor DTFT is basically the same, the threshold voltage of the driving transistor DTFT is basically stable, and the influence of the hysteresis effect can be weakened.
  • the signal provided by the first control signal terminal SC1 (third control signal terminal SC3) is at a high level
  • the signal provided by the second control signal terminal SC2 (fifth control signal terminal SC5) is at a high level
  • the light is emitted.
  • the signal provided by the control signal terminal EM is low level
  • the signal provided by the fourth control signal terminal SC4 is high level.
  • the third transistor T3 continuously writes the third voltage Vref to the second node N2 to maintain the stability of the voltage at the second node N2, which is conducive to maintaining the stability of the voltage at the first node N1; at the same time, the driving transistor DTFT according to its own The gate-source voltage Vgs outputs the driving current I.
  • FIG. 17 is a schematic diagram of another circuit structure of the pixel driving circuit provided by the embodiment of the present disclosure. As shown in FIG. 17 , on the basis of the pixel driving circuit shown in FIG. 16 , the pixel driving circuit shown in FIG. 17 also includes: a second The reset circuit 6, the second reset circuit 6 further includes a seventh transistor T7.
  • the seventh transistor T7 connected to the first node N1 can be designed to It is an oxide transistor, which can effectively reduce the leakage of the first node N1 through the second transistor T2.
  • FIG. 18 is a working timing diagram of the pixel driving circuit shown in FIG. 17.
  • the first control signal terminal SC1 (the third control signal terminal SC3)
  • the second control signal terminal SC2 (The working sequence of the fifth control signal terminal SC5)
  • the fourth control signal terminal SC4 is the same as the first control signal terminal SC1 (the third control signal terminal SC3)
  • the second control signal terminal SC2 (the fifth control signal terminal SC2) shown in FIG. Terminal SC5)
  • the fourth control signal terminal SC4 have the same working sequence.
  • the working timings of the light emission control signal terminal EM and the sixth control signal terminal SC6 in each stage in FIG. 18 will be described in detail.
  • the signal provided by the light emission control signal terminal EM is at high level
  • the signal provided by the sixth control signal terminal SC6 is at high level
  • the seventh transistor T7 is in the on state
  • the fourth transistor T4 is in the off state.
  • the third voltage Vref is written into the first node N1 through the seventh transistor T7 to reset the first node N1.
  • the signal provided by the luminescence control signal terminal EM is at a high level, and the signal provided by the sixth control signal terminal SC6 is at a low level; the seventh transistor T7 is in an off state, and the fourth transistor T4 is off.
  • the signal provided by the light-emitting control signal terminal EM is at low level, and the signal provided by the sixth control signal terminal SC6 is at low level; the fourth transistor T4 is in the on state, and the seventh transistor T7 is in the off state.
  • FIG. 19 is a schematic diagram of another circuit structure of the pixel driving circuit provided by the embodiment of the present disclosure. As shown in FIG. 19, it is different from the second transistor T2 and the sixth transistor T6 shown in FIG. 15 which are both low-temperature polysilicon transistors.
  • the second transistor T2 and the sixth transistor T6 shown in are both oxide transistors, which can effectively reduce the leakage of the first node N1 through the second transistor T2 and reduce the leakage of the first electrode of the light emitting device OLED through the sixth transistor T6.
  • FIG. 20 is a working timing diagram of the pixel driving circuit shown in FIG. 19.
  • the first control signal terminal SC1 third control signal terminal SC3
  • fourth control signal terminal SC4 and The working sequence of the light-emitting control signal terminal EM is the same as that of the first control signal terminal SC1 (the third control signal terminal SC3), the fourth control signal terminal SC4 and the light-emitting control signal terminal EM shown in FIG. 16; in FIG. 20
  • the level state of the second control signal terminal SC2 (fifth control signal terminal SC5) in each stage shown is the same as the level of the second control signal terminal SC2 (fifth control signal terminal SC5) in each stage shown in FIG. 16 The state is reversed. The specific working process will not be repeated here.
  • the stabilizing voltage may not be the above-mentioned fifth transistor T5, but the stabilizing capacitor C2 involved in the previous embodiment, and no corresponding drawings are shown in this case.
  • each transistor in the pixel driving circuit provided by each of the above embodiments can be independently selected from an N-type transistor or a P-type transistor, and the technical solution obtained only by simply changing the type of the transistor and the corresponding timing, It should also belong to the protection scope of the present disclosure.
  • different technical features can be combined with each other, and the technical solutions obtained through the combination of technical features should also belong to the protection scope of the present disclosure.
  • an embodiment of the present disclosure also provides a driving method for a pixel driving circuit.
  • Fig. 21 is a flow chart of a driving method of a pixel driving circuit provided by an embodiment of the present disclosure.
  • the pixel driving circuit is the pixel driving circuit provided in the previous embodiment, and the specific description of the pixel driving circuit Please refer to the content in the previous embodiments, and will not go into details here; the driving method includes:
  • Step S1 in the compensation stage, the data writing circuit writes the data voltage provided by the data line to the second node in response to the control of the signal of the first control signal terminal, and the compensation control circuit responds to the control of the signal of the second control signal terminal to obtain The threshold voltage of the drive transistor.
  • Step S2 in the luminous voltage writing phase, the compensation control circuit writes the third voltage provided by the third voltage input terminal into the second node in response to the control of the signal of the third control signal terminal, and according to the voltage change at the second node and The threshold voltage is written into the first node with a light-emitting voltage capable of threshold compensation for the drive transistor, and the voltage stabilizing circuit maintains the stability of the voltage at the third node.
  • Step S3 in the light-emitting stage, the light-emitting control circuit responds to the control of the signal of the light-emitting control signal terminal to conduct between the third node and the first pole of the light-emitting device, and the driving transistor generates a corresponding driving current according to the light-emitting voltage to drive the light-emitting device glow.
  • step S1 to step S3 reference may be made to the content in the previous embodiments, which will not be repeated here.
  • the voltage stabilizing circuit can weaken or even completely eliminate The influence of the parasitic capacitance between the gate and the drain of the driving transistor on the voltage at the drain of the driving transistor to maintain the stability of the voltage at the third node, so that the bias stress on the driving transistor is basically the same, and the threshold voltage of the driving transistor It is basically stable, and the influence of the hysteresis effect can be weakened, thereby effectively improving the afterimage and flickering problems of the display device.
  • an embodiment of the present disclosure also provides a display substrate, the display substrate includes: a pixel driving circuit, the pixel driving circuit adopts the pixel driving circuit provided in the previous embodiment, and the specific description can refer to the content in the previous embodiment , which will not be repeated here.
  • Embodiments of the present disclosure also provide a display device, which includes: a display substrate, where the display substrate provided in the previous embodiments is used.
  • the display device in the embodiments of the present disclosure may be any product or component with a display function, such as electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.
  • a display function such as electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.

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Abstract

本公开提供了一种像素驱动电路，包括：数据写入电路、补偿控制电路、发光控制电路、稳压电路和驱动晶体管，补偿控制电路与驱动晶体管的栅极连接于第一节点，补偿控制电路与数据写入电路连接于第二节点，补偿控制电路、发光控制电路、稳压电路以及驱动晶体管的第二极连接于第三节点；其中，补偿控制电路配置为响应于第二控制信号端的信号的控制来获取驱动晶体管的阈值电压，以及响应于第三控制信号端的信号的控制将第三电压输入端提供的第三电压写入至第二节点，并根据第二节点处电压变化和阈值电压向第一节点写入能够对驱动晶体管进行阈值补偿的发光电压；稳压电路配置为在补偿控制电路向第一节点写入发光电压时维持第三节点处电压的稳定。

Description

像素驱动电路及其驱动方法、显示基板和显示装置 技术领域
本公开涉及显示领域，特别涉及一种像素驱动电路及其驱动方法、显示基板和显示装置。
背景技术
在现有的像素驱动电路工作于低频状态时，由于偏压应力会使驱动晶体管的阈值电压发生偏移，且随着驱动晶体管所受偏压应力的不同，其阈值电压偏移程度也不一致，即驱动晶体管的电学特性不稳定，此时会产生严重的磁滞效应，从而导致残影、闪烁等不良出现。
发明内容
第一方面，本公开实施例提供了一种像素驱动电路，包括：数据写入电路、补偿控制电路、发光控制电路、稳压电路和驱动晶体管，所述补偿控制电路与所述驱动晶体管的栅极连接于第一节点，所述补偿控制电路与所述数据写入电路连接于第二节点，所述补偿控制电路、所述发光控制电路、所述稳压电路以及所述驱动晶体管的第二极连接于第三节点；
所述数据写入电路，与第一控制信号端和数据线连接，配置为响应于所述第一控制信号端的信号的控制将所述数据线提供的数据电压写入至所述第二节点；
所述发光控制电路，与发光控制信号端和发光器件的第一极连接，配置为响应于所述发光控制信号端的信号的控制，来控制所述第三节点与所述发光器件的第一极之间的通断；
所述补偿控制电路，与第二控制信号端、第三控制信号端和第三电压输入端连接，配置为响应于所述第二控制信号端的信号的控制来获取所述驱动晶体管的阈值电压，以及响应于所述第三控制信号端的 信号的控制将所述第三电压输入端提供的第三电压写入至所述第二节点，并根据所述第二节点处电压变化和所述阈值电压向所述第一节点写入能够对所述驱动晶体管进行阈值补偿的发光电压；
所述稳压电路，配置为在所述补偿控制电路向所述第一节点写入所述发光电压时维持所述第三节点处电压的稳定；
所述驱动晶体管，其第一极与第一电压输入端连接，配置为根据所述发光电压产生相应的驱动电流。
在一些实施例中，所述稳压电路包括：第五晶体管；
所述第五晶体管的控制极与第四控制信号端的第一极连接，所述第五晶体管的第一极与所述第三节点连接，所述第五晶体管的第二极与所述第三电压输入端连接。
在一些实施例中，所述稳压电路包括：稳压电容；
所述稳压电容的第一端与所述第三节点连接，所述稳压电容的第二端与第四电压输入端连接。
在一些实施例中，所述第四电压输入端为所述发光控制信号端。
在一些实施例中，所述数据写入电路包括第一晶体管；
所述第一晶体管的控制极与所述第一控制信号端连接，所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述第二节点连接。
在一些实施例中，所述第一晶体管为双栅型低温多晶硅晶体管。
在一些实施例中，所述复位补偿电路包括：第二晶体管、第三晶体管和耦合电容；
所述第二晶体管的控制极与所述第二控制信号端连接，所述第二晶体管的第一极与所述第一节点连接，所述第二晶体管的第二极与所述第三节点连接；
所述第三晶体管的控制极与所述第三控制信号端连接，所述第三晶体管的第一极与所述第三电压输入端连接，所述第三晶体管的第二极与所述第二节点连接；
所述耦合电容的第一端与所述第一节点连接，所述耦合电容的第二端与所述第二节点连接。
在一些实施例中，所述数据写入电路包括第一晶体管；
所述第一晶体管的控制极与所述第一控制信号端连接，所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述第二节点连接；
所述第一晶体管为低温多晶硅晶体管，所述第三晶体管为氧化物晶体管；
所述第一控制信号端与所述第三控制信号端为同一控制信号端。
在一些实施例中，所述像素驱动电路还包括：第一复位电路；
所述第一复位电路包括：第六晶体管；
所述第六晶体管的控制极与所述第五控制信号端连接，所述第六晶体管的第一极与所述发光器件的第一极连接，所述第六晶体管的第二极与所述第三电压输入端连接；
所述第二晶体管和所述第六晶体管均为低温多晶硅晶体管或均为氧化物晶体管；
所述第二控制信号端与所述第五控制信号端为同一控制信号端。
在一些实施例中，所述第一晶体管为双栅型低温多晶硅晶体管。
在一些实施例中，所述发光控制电路包括：第四晶体管；
所述第四晶体管的控制极与所述发光控制信号端连接，所述第四晶体管的第一极与所述第三节点连接，所述第四晶体管的第二极与所述发光器件的第一极连接。
在一些实施例中，所述像素驱动电路还包括：第一复位电路；
所述第一复位电路，与第五控制信号端、所述第三电压输入端和发光器件的第一极连接，配置为响应于所述第五控制信号端的信号的控制将所述第三电压输入端提供的第三电压写入至所述发光器件的第一极。
在一些实施例中，所述第一复位电路包括：第六晶体管；
所述第六晶体管的控制极与所述第五控制信号端连接，所述第六晶体管的第一极与所述发光器件的第一极连接，所述第六晶体管的第二极与所述第三电压输入端连接。
在一些实施例中，所述像素驱动电路还包括：第二复位电路；
所述第二复位电路，与第六控制信号端、所述第三电压输入端和所述第一节点连接，配置为响应于所述第六控制信号端的信号的控制将所述第三电压输入端提供的第三电压写入至所述第一节点。
在一些实施例中，所述第二复位电路包括：第七晶体管；
所述第七晶体管的控制极与所述第六控制信号端连接，所述第七晶体管的第一极与所述第三电压输入端连接，所述第七晶体管的第二极与所述第一节点连接。
在一些实施例中，所述第七晶体管为氧化物晶体管。
第二方面，本公开实施例还提供了一种像素驱动电路的驱动方法，所述像素驱动电路为第一方面中提供的所述像素驱动电路，所述驱动方法包括：
补偿阶段，所述数据写入电路响应于所述第一控制信号端的信号的控制将所述数据线提供的数据电压写入至所述第二节点，所述补偿控制电路响应于所述第二控制信号端的信号的控制来获取所述驱动晶体管的阈值电压；
发光电压写入阶段，所述补偿控制电路响应于所述第三控制信号端的信号的控制将所述第三电压输入端提供的第三电压写入至所述第二节点，并根据所述第二节点处电压变化和所述阈值电压向所述第一节点写入能够对所述驱动晶体管进行阈值补偿的发光电压，所述稳压电路维持所述第三节点处电压的稳定；
发光阶段，所述发光控制电路响应于所述发光控制信号端的信号的控制将所述第三节点与所述发光器件的第一极之间导通，所述驱动晶体管根据所述发光电压产生相应的驱动电流，以驱动所述发光器件 发光。
第三方面，本公开实施例还提供了一种显示基板，包括：如上述第二方面中提供的所述像素驱动电路。
第四方面，本公开实施例还提供了一种显示装置，包括：如上述第三方面中提供的所述显示基板。
附图说明
图1为本公开实施例提供的像素驱动电路的一种电路结构示意图；
图2为本公开实施例提供的像素驱动电路的另一种电路结构示意图；
图3a为本公开实施例提供的像素驱动电路的又一种电路结构示意图；
图3b为本公开实施例提供的像素驱动电路的再一种电路结构示意图；
图4为本公开实施例提供的像素驱动电路的再一种电路结构示意图；
图5为图4所示像素驱动电路的一种工作时序图；
图6为本公开实施例提供的像素驱动电路的再一种电路结构示意图；
图7为本公开实施例提供的像素驱动电路的再一种电路结构示意图；
图8为本公开实施例提供的像素驱动电路的再一种电路结构示意图；
图9为图7所示像素驱动电路的一种工作时序图；
图10为本公开实施例提供的像素驱动电路的再一种电路结构示意图；
图11为本公开实施例提供的像素驱动电路的再一种电路结构示意图；
图12为图10所示像素驱动电路的一种工作时序图；
图13为本公开实施例提供的像素驱动电路的再一种电路结构示意图；
图14为本公开实施例提供的像素驱动电路的再一种电路结构示意图；
图15为本公开实施例提供的像素驱动电路的再一种电路结构示意图；
图16为图15所示像素驱动电路的一种工作时序图；
图17为本公开实施例提供的像素驱动电路的再一种电路结构示意图；
图18为图17所示像素驱动电路的一种工作时序图；
图19为本公开实施例提供的像素驱动电路的再一种电路结构示意图；
图20为图19所示像素驱动电路的一种工作时序图；
图21为本公开实施例提供的一种像素驱动电路的驱动方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的一种像素驱动电路及其驱动方法、显示基板和显示装置进行详细描述。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中 的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要说明的是，在本公开实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他具有相同、类似特性的器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本公开实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，当采用P型晶体管时，第一极为P型晶体管的源极，第二极为P型晶体管的漏极，N型晶体管的情况相反。本公开中的“有效电平”是指能够控制相应晶体管导通的电平；具体地，针对P型晶体管，其所对应的有效电平为低电平；针对N型晶体管，其所对应的有效电平为高电平。
具有内部补偿功能的像素驱动电路的工作过程大致如下：在补偿阶段，获取驱动晶体管的阈值电压；在发光电压写入阶段，根据数据电压和驱动晶体管的阈值电压生成能够对驱动晶体管进行阈值补偿的发光电压，并将该发光电压写入至驱动晶体管的栅极；在发光阶段，将驱动晶体管的漏极与发光器件之间导通，以使得驱动晶体管能够向发光器件输出驱动电流。
在相关技术中，在将发光电压写入至驱动晶体管的过程(即发光电压写入阶段)中，驱动晶体管的漏极一般会处于浮接状态(floating)； 由于驱动晶体管的栅极与漏极之间存在寄生电容，因此在将发光电压写入至驱动晶体管的过程中，驱动晶体管的漏极处电压会发生相应的变化。驱动晶体管的漏极电压的变化，会使得驱动晶体管所受偏压应力不一致，驱动晶体管的阈值电压会发生严重偏移，从而产生严重的磁滞效应，进而导致残影、闪烁等不良出现。
为解决相关技术中存在的至少之一的技术问题，本公开实施例提供了相应的解决方案。
本公开中的发光器件是指包括有机发光二极管(Organic Light Emitting Diode，简称OLED)、发光二极管(Light Emitting Diode，简称LED)等电流驱动型的发光元件，本公开实施例中将以发光器件为OLED为例进行示例性描述，其中发光器件的第一极和第二极分别是指阳极和阴极。
图1为本公开实施例提供的像素驱动电路的一种电路结构示意图，如图1所示，该像素驱动电路包括：数据写入电路1、补偿控制电路2、发光控制电路3、稳压电路4和驱动晶体管DTFT，补偿控制电路2与驱动晶体管DTFT的栅极连接于第一节点N1，补偿控制电路2与数据写入电路1连接于第二节点N2，补偿控制电路2、发光控制电路3、稳压电路4以及驱动晶体管DTFT的第二极连接于第三节点N3。
其中，数据写入电路1与第一控制信号端SC1和数据线Data连接，数据写入电路1配置为响应于第一控制信号端SC1的信号的控制将数据线Data提供的数据电压写入至第二节点N2。
发光控制电路3与发光控制信号端EM和发光器件OLED的第一极连接，发光控制电路3配置为响应于发光控制信号端EM的信号的控制，来控制第三节点N3与发光器件OLED的第一极之间的通断。
补偿控制电路2与第二控制信号端SC2、第三控制信号端SC3和第三电压输入端连接，补偿控制电路2配置为响应于第二控制信号端SC2的信号的控制来获取驱动晶体管DTFT的阈值电压，以及响应于第三控制信号端SC3的信号的控制将第三电压输入端提供的第三电压 写入至第二节点N2，并根据第二节点N2处电压变化和阈值电压向第一节点N1写入能够对驱动晶体管DTFT进行阈值补偿的发光电压。
稳压电路4配置为在补偿控制电路2向第一节点N1写入发光电压时维持第三节点N3处电压的稳定。
驱动晶体管DTFT其第一极与第一电压输入端连接，驱动晶体管DTFT配置为根据发光电压产生相应的驱动电流。
在本公开实施例中，通过在像素驱动电路内的第三节点N3处设置稳压电路4，该稳压电路4可在补偿控制电路2向驱动晶体管DTFT的栅极写入发光电压过程中，减弱、甚至完全消除驱动晶体管DTFT的栅极与漏极之间寄生电容对驱动晶体管DTFT的漏极处电压的影响，以维持第三节点N3处电压的稳定，从而使得驱动晶体管DTFT所受偏压应力基本一致，驱动晶体管DTFT的阈值电压基本保持稳定，能够减弱磁滞效应的影响，进而能够有效改善显示装置的残影、闪烁的问题。
图2为本公开实施例提供的像素驱动电路的另一种电路结构示意图，如图2所示，在一些实施例中，稳压电路4包括：第五晶体管T5；第五晶体管T5的控制极与第四控制信号端SC4的第一极连接，第五晶体管T5的第一极与第三节点N3连接，第五晶体管T5的第二极与第三电压输入端连接。
在补偿控制电路2向驱动晶体管DTFT的栅极写入发光电压的过程中，通过第四控制信号端SC4的信号来控制第五晶体管T5导通，以将第三电压输入端所提供的第三电压(至少在发光电压写入阶段为恒定电压)写入至第三节点N3；即，在发光电压写入阶段过程中，第三节点N3处的电压始终为第三电压；也就是说，在发光电压写入阶段，本公开实施例中的稳压电路4能够完全消除驱动晶体管DTFT的栅极与漏极之间寄生电容对驱动晶体管DTFT的漏极处电压的影响。
图3a为本公开实施例提供的像素驱动电路的又一种电路结构示意图，如图3a所示，与图2中所示稳压电路4包括第五晶体管T5的情况不同，在图3a所示实施例中的稳压电路4包括：稳压电容C2；稳 压电容C2的第一端与第三节点N3连接，稳压电容C2的第二端与第四电压输入端连接。其中，第四电压输入端所提供的第四电压至少在发光电压写入阶段为恒定电压。
在本公开实施例中，通过在第三节点N3处设置稳压电容C2，可以有效减弱驱动晶体管DTFT的栅极与漏极之间寄生电容对第三节点N3处电压的影响，使得在发光电压写入阶段中第三节点N3处的电压仅发生较小的变化或基本保持不变。也就是说，在发光电压写入阶段，本公开实施例中的稳压电路4能够完全有效改善驱动晶体管DTFT的栅极与漏极之间寄生电容对驱动晶体管DTFT的漏极处电压的影响。
图3b为本公开实施例提供的像素驱动电路的再一种电路结构示意图，如图3b所示，在一些实施例中，稳压电容C2的第二端所连接的第四电压输入端为发光控制信号端EM。也就是说，可以直接将稳压电容C2的第二端与发光控制电路3所配置的发光控制信号端EM进行连接。
上述将稳压电容C2的第二端与发光控制信号端EM进行连接的设计，其一方面可以有效减少像素驱动电路所需配置的信号种类，有利于简化产品设计；另一方面由于第二电容与发光控制电路3距离相对较近，因此在实际产品中第二电容的第二端与发光控制信号端EM的连接较容易实现。
图4为本公开实施例提供的像素驱动电路的再一种电路结构示意图，如图4所示，在一些实施例中，数据写入电路1包括第一晶体管T1；其中，第一晶体管T1的控制极与第一控制信号端SC1连接，第一晶体管T1的第一极与数据线Data连接，第一晶体管T1的第二极与第二节点N2连接。
在一些实施中，位补偿电路包括：第二晶体管T2、第三晶体管T3和耦合电容C1；其中，第二晶体管T2的控制极与第二控制信号端SC2连接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第三节点N3连接。第三晶体管T3的控制极与第三控制信号端SC3连接，第三晶体管T3的第一极与第三电压输入端连接，第 三晶体管T3的第二极与第二节点N2连接。耦合电容C1的第一端与第一节点N1连接，耦合电容C1的第二端与第二节点N2连接。
在一些实施例中，发光控制电路3包括：第四晶体管T4；其中，第四晶体管T4的控制极与发光控制信号端EM连接，第四晶体管T4的第一极与第三节点N3连接，第四晶体管T4的第二极与发光器件OLED的第一极连接。
下面将结合附图来对图4所示像素驱动电路的具体工作过程进行详细描述。图4中示例性给出了像素驱动电路内的晶体管均为P型晶体管的情况，例如像素驱动电路内的所有晶体管均为低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)晶体管。第一电压输入端提供的第一电压VDD，第二电压输入端提供第二电压VSS，第三电压输入端提供第三电压Vref。其中，第三电压Vref可以等于第一电压VDD或者略小于第一电压VDD。
图5为图4所示像素驱动电路的一种工作时序图，如图5所示，图4所示像素驱动电路的工作过程可包括如下几个阶段：
在复位阶段t1，第一控制信号端SC1提供的信号为高电平，第二控制信号端SC2提供的信号为低电平，第三控制信号端SC3提供的信号为低电平，发光控制信号端EM提供的信号为低电平，第四控制信号端SC4提供的信号为高电平。此时，第二晶体管T2、第三晶体管T3和第四晶体管T4均导通，第一晶体管T1和第五晶体管T5均截止。
第三电压Vref通过第三晶体管T3写入至第二节点N2，以对第二节点N2进行复位；发光器件OLED的第一极处的电压VSS+Voled通过第四晶体管T4和第二晶体管T2写入至第一节点N1，以对第一节点N1进行复位；其中，Voled为发光器件OLED的导通电压(Voled的大小随着发光器件OLED的工作状态而发生变化)。
在补偿阶段t2，第一控制信号端SC1提供的信号为低电平，第二控制信号端SC2提供的信号为低电平，第三控制信号端SC3提供的信号为高电平，发光控制信号端EM提供的信号为高电平，第四控制信号端SC4提供的信号为高电平。此时，第一晶体管T1和第二晶体管 T2均导通，第三晶体管T3、第四晶体管T4和第五晶体管T5均截止。
数据电压Vdata通过第一晶体管T1写入至第二节点N2N2；第一电压VDD通过驱动晶体管DTFT和第二晶体管T2对第一节点N1进行充电，当第一节点N1处电压为VDD+Vth时，驱动晶体管DTFT截止，充电结束；其中，Vth为驱动晶体管DTFT的阈值电压。此时，耦合电容C1的两端电压差为VDD+Vth-Vdata。
在发光电压写入阶段t3，第一控制信号端SC1提供的信号为高电平，第二控制信号端SC2提供的信号为高电平，第三控制信号端SC3提供的信号为低电平，发光控制信号端EM提供的信号为高电平，第四控制信号端SC4提供的信号为低电平。此时，第三晶体管T3和第五晶体管T5均导通，第一晶体管T1、第二晶体管T2和第四晶体管T4均截止。
第二晶体管T2截止，第一节点N1处于浮接状态。第三电压Vref通过第三晶体管T3写入至第二节点N2，第二节点N2处电压由Vdata变为Vref，在耦合电容C1的自举作用下，第一节点N1处电压由VDD+Vth变为VDD+Vth+Vref-Vdata。即，向第一节点N1写入发光电压为VDD+Vth+Vref-Vdata。
在第一节点N1写入发光电压的过程中，由于第五晶体管T5导通，因此第三电压Vref通过第五晶体管T5写入第三节点N3，第三节点N3处电压始终维持在Vref，即驱动晶体管DTFT所受偏压应力基本一致，驱动晶体管DTFT的阈值电压基本保持稳定，能够减弱磁滞效应的影响。
在发光阶段t4，第一控制信号端SC1提供的信号为高电平，第二控制信号端SC2提供的信号为高电平，第三控制信号端SC3提供的信号为低电平，发光控制信号端EM提供的信号为低电平，第四控制信号端SC4提供的信号为高电平。此时，第三晶体管T3和第四晶体管T4均导通，第一晶体管T1、第二晶体管T2和第五晶体管T5均截止。
第三晶体管T3持续向第二节点N2写入第三电压Vref，以维持第二节点N2处电压的稳定，有利于维持第一节点N1处电压的稳定；与 此同时，驱动晶体管DTFT根据自身的栅源电压Vgs输出驱动电流I。
其中，Vgs＝VDD+Vth+Vref-Vdata-VDD＝Vth+Vref-Vdata；根据驱动晶体管DTFT的饱和驱动电流公式可得：
I＝K*(Vgs-Vth) 2
＝K*(Vth+Vref-Vdata-Vth) 2
＝K*(Vref-Vdata) 2
其中，K为一个常量(大小与驱动晶体管DTFT的电学特性相关)。通过上式可见，驱动晶体管DTFT所输出的驱动电流I仅与数据电压Vdata和第三电压Vref相关，而与驱动晶体管DTFT的阈值电压Vth无关，从而可避免流过发光器件OLED的驱动电流受到阈值电压不均匀和漂移的影响，进而有效的提高了流过发光器件OLED的驱动电流的均匀性。
需要说明的是，在一些实施例中，也可以无需进行上述复位阶段的过程；即，像素驱动电路的工作过程仅包括上述补偿阶段t2、发光电压写入阶段t3和发光阶段t4。
需要说明的是，图4中示例性给出了稳压电路4包括第五晶体管T5的情况。图6为本公开实施例提供的像素驱动电路的再一种电路结构示意图，如图6所示，图6中的数据写入电路1、补偿控制电路2和发光控制电路3的具体电路结构与图4中相同，但图6中的稳压电路4包括稳压电容C2。图6中也仅示例性给出了稳压电容C2的第二端与发光控制信号端EM相连的情况。
图6所示像素驱动电路的工作时序也可以采用图5中所示，具体过程此处不再赘述。
图7为本公开实施例提供的像素驱动电路的再一种电路结构示意图，图8为本公开实施例提供的像素驱动电路的再一种电路结构示意图，如图7和图8所示，在一些实施例中，像素驱动电路不但包括数据写入电路1、补偿控制电路2、发光控制电路3和稳压电路4，还包括：第一复位电路5。
其中，第一复位电路5与第五控制信号端SC5、第三电压输入端 和发光器件OLED的第一极连接，配置为响应于第五控制信号端SC5的信号的控制将第三电压输入端提供的第三电压写入至发光器件OLED的第一极。在本公开实施例中，通过设置第一复位电路5，可在复位阶段对发光器件OLED的第一极进行复位。
在一些实施例中，第一复位电路5包括：第六晶体管T6；第六晶体管T6的控制极与第五控制信号端SC5连接，第六晶体管T6的第一极与发光器件OLED的第一极连接，第六晶体管T6的第二极与第三电压输入端连接。
图9为图7所示像素驱动电路的一种工作时序图，如图9所示，图7所示像素驱动电路的工作过程可包括：复位阶段t1、补偿阶段t2、发光电压写入阶段t3和发光阶段t4。其中，图9中所示第一控制信号端SC1、第二控制信号端SC2、第三控制信号端SC3、发光控制信号端EM和第四控制信号端SC4的工作时序，与图5中所示情况相同，下面仅对第五控制信号端SC5在各阶段的工作时序进行详细描述。
在复位阶段t1，第五控制信号端SC5提供的信号为低电平，第六晶体管T6导通，第三工作电压Vref通过第六晶体管T6写入至发光器件OLED的第一极，以对发光器件OLED的第一极进行复位。与此同时，第三工作电压Vref还可以通过第四晶体管T4、第二晶体管T2写入至第一节点N1，以对第一节点N1进行复位。在补偿阶段t2、发光电压写入阶段t3和发光阶段t4，第五控制信号端SC5均提供低电平，第六晶体管T6截止。
需要说明的是，在一些实施例中，图9中第五控制信号端SC5也可以在补偿阶段t2和/或发光电压写入阶段t3提供低电平，以持续对发光器件OLED的第一极进行复位，该种情况也属于本公开的保护范围。
图10为本公开实施例提供的像素驱动电路的再一种电路结构示意图，图11为本公开实施例提供的像素驱动电路的再一种电路结构示意图，如图10和图11所示，在一些实施例中，像素驱动电路不但包括数据写入电路1、补偿控制电路2、发光控制电路3和稳压电路4， 还包括：第二复位电路6。
第二复位电路6与第六控制信号端SC6、第三电压输入端和第一节点N1连接，第二复位电路6配置为响应于第六控制信号端SC6的信号的控制将第三电压输入端提供的第三电压写入至第一节点N1。在本公开实施例中，通过设置第二复位电路6，可在复位阶段对第一节点N1进行复位，此时无需再利用发光器件OLED的第一极处电压来对第一节点N1进行复位，相应地在复位阶段发光控制电路3无需再使得第三节点N3与发光器件OLED的第一极之间导通。
在一些实施例中，第二复位电路6包括：第七晶体管T7；第七晶体管T7的控制极与第六控制信号端SC6连接，第七晶体管T7的第一极与第三电压输入端连接，第七晶体管T7的第二极与第一节点N1连接。
图12为图10所示像素驱动电路的一种工作时序图，如图12所示，图10所示像素驱动电路的工作过程可包括：复位阶段t1、补偿阶段t2、发光电压写入阶段t3和发光阶段t4。其中，图12中所示第一控制信号端SC1、第二控制信号端SC2、第三控制信号端SC3和第四控制信号端SC4的工作时序，与图9中所示第一控制信号端SC1、第二控制信号端SC2、第三控制信号端SC3和第四控制信号端SC4的工作时序相同。下面仅对发光控制信号端EM和第六控制信号端SC6在各阶段的工作时序进行详细描述。
在复位阶段t1，发光控制信号端EM提供的信号处于高电平，第六控制信号端SC6提供的信号处于低电平；第七晶体管T7处于导通状态，第四晶体管T4处于截止状态。第三电压Vref通过第七晶体管T7写入至第一节点N1，以对第一节点N1进行复位。
在补偿阶段t2和发光电压写入阶段t3，发光控制信号端EM提供的信号处于高电平，第六控制信号端SC6提供的信号处于高电平；第七晶体管T7处于截止状态，第四晶体管T4处于截止状态。
在发光阶段t4，发光控制信号端EM提供的信号处于低电平，第六控制信号端SC6提供的信号处于高电平；第四晶体管T4处于导通 状态，第七晶体管T7处于截止状态。
图13为本公开实施例提供的像素驱动电路的再一种电路结构示意图，图14为本公开实施例提供的像素驱动电路的再一种电路结构示意图，如图13和图14所示，在一些实施例中，像素驱动电路不但包括数据写入电路1、补偿控制电路2、发光控制电路3和稳压电路4，还同时包括上述第一复位电路5和第二复位电路6。
对于图13、图14中数据写入电路1、补偿控制电路2、发光控制电路3、稳压电路4、第一复位电路5和第二复位电路6的具体电路结构的描述，可参见前面实施例中的相应内容，此处不再赘述。图13和图14所示像素驱动电路的具体工作过程可参见前面对图9和图12中所示时序的描述。
图15为本公开实施例提供的像素驱动电路的再一种电路结构示意图，如图15所示，在一些实施例中，第一晶体管T1为双栅型低温多晶硅晶体管。低温多晶硅晶体管具有响应速度快的特点，可使得在补偿阶段能够将数据电压Vdata快速写入至第二节点N2，以满足高分辨率产品对数据电压写入速度的高要求。同时，低温多晶硅晶体管的双栅结构设计，可有效减少第二节点N2通过第一晶体管T1的漏电。
继续参见图15所示，在一些实施例中，在第一晶体管T1为低温多晶硅晶体管(P型晶体管)的同时，第三晶体管T3为氧化物晶体管(N型晶体管，具体可以为低温多晶氧化物晶体管)，第一控制信号端SC1与第三控制信号端SC3为同一控制信号端。氧化物晶体管具有较小的漏电流，可有效减少第二节点N2通过第三晶体管T3的漏电。与此同时，将第一控制信号端SC1与第三控制信号端SC3为设计为同一控制信号端，可以有效减少像素驱动电路所需配置的信号种类，有利于简化产品设计。
在一些实施例中，第二晶体管T2和第六晶体管T6均为低温多晶硅晶体管，第二控制信号端SC2与第五控制信号端SC5为同一控制信号端。在本公开中，将第六晶体管T6设计为低温多晶硅晶体管，可使得第三电压Vref能够在复位阶段快速的写入至发光器件OLED的第一 极，因此复位阶段的时长可设计的相对较短，以满足高分辨率产品对复位速度的高要求；将第二晶体管T2设计为低温多晶硅晶体管，可使得在补偿阶段能够快速的获取到驱动晶体管DTFT的阈值电压，因此补偿阶段的时长可设计的相对较短，以满足高分辨率产品对补偿速度的高要求；与此同时，将第二控制信号端SC2与第五控制信号端SC5为设计为同一控制信号端，可以有效减少像素驱动电路所需配置的信号种类，有利于简化产品设计。
进一步地，考虑到第一节点N1在发光阶段处于浮接状态，而第一节点N1处电压的稳定性直接影响到发光器件OLED的发光效果，为此可将与第一节点N1相连的第二晶体管T2设计为双栅型低温多晶硅晶体管，可有效减少第一节点N1通过第二晶体管T2的漏电。
图16为图15所示像素驱动电路的一种工作时序图，如图16所示，图16所示像素驱动电路的工作过程可包括如下几个阶段：
在复位阶段t1，第一控制信号端SC1(第三控制信号端SC3)提供的信号为高电平，第二控制信号端SC2(第五控制信号端SC5)提供的信号为低电平，发光控制信号端EM提供的信号为低电平，第四控制信号端SC4提供的信号为高电平。此时，第二晶体管T2、第三晶体管T3、第四晶体管T4和第六晶体管T6均导通，第一晶体管T1和第五晶体管T5均截止。
第三电压Vref通过第三晶体管T3写入至第二节点N2，以对第二节点N2进行复位；第三电压Vref通过第六晶体管T6写入至发光器件OLED的第一极，以对发光器件OLED的第一极进行复位，同时还通过第四晶体管T4和第二晶体管T2写入至第一节点N1，以对第一节点N1进行复位。
在补偿阶段t2，第一控制信号端SC1(第三控制信号端SC3)提供的信号为低电平，第二控制信号端SC2(第五控制信号端SC5)提供的信号为低电平，发光控制信号端EM提供的信号为高电平，第四控制信号端SC4提供的信号为高电平。此时，第一晶体管T1、第二晶体管T2和第六晶体管T6均导通，第三晶体管T3、第四晶体管T4和 第五晶体管T5均截止。
数据电压Vdata通过第一晶体管T1写入至第二节点N2N2；第一电压VDD通过驱动晶体管DTFT和第二晶体管T2对第一节点N1进行充电，当第一节点N1处电压为VDD+Vth时，驱动晶体管DTFT截止，充电结束；此时，耦合电容C1的两端电压差为VDD+Vth-Vdata。
在发光电压写入阶段t3，第一控制信号端SC1(第三控制信号端SC3)提供的信号为高电平，第二控制信号端SC2(第五控制信号端SC5)提供的信号为高电平，发光控制信号端EM提供的信号为高电平，第四控制信号端SC4提供的信号为低电平。此时，第三晶体管T3和第五晶体管T5均导通，第一晶体管T1、第二晶体管T2、第四晶体管T4和第六晶体管T6均截止。
第二晶体管T2截止，第一节点N1处于浮接状态。第三电压Vref通过第三晶体管T3写入至第二节点N2，第二节点N2处电压由Vdata变为Vref，在耦合电容C1的自举作用下，第一节点N1处电压由VDD+Vth变为VDD+Vth+Vref-Vdata。即，向第一节点N1写入发光电压为VDD+Vth+Vref-Vdata。
在第一节点N1写入发光电压的过程中，由于第五晶体管T5导通，因此第三电压Vref通过第五晶体管T5写入第三节点N3，第三节点N3处电压始终维持在Vref，即驱动晶体管DTFT所受偏压应力基本一致，驱动晶体管DTFT的阈值电压基本保持稳定，能够减弱磁滞效应的影响。
在发光阶段t4，第一控制信号端SC1(第三控制信号端SC3)提供的信号为高电平，第二控制信号端SC2(第五控制信号端SC5)提供的信号为高电平，发光控制信号端EM提供的信号为低电平，第四控制信号端SC4提供的信号为高电平。此时，第三晶体管T3和第四晶体管T4均导通，第一晶体管T1、第二晶体管T2、第五晶体管T5和第六晶体管T6均截止。
第三晶体管T3持续向第二节点N2写入第三电压Vref，以维持第二节点N2处电压的稳定，有利于维持第一节点N1处电压的稳定；与 此同时，驱动晶体管DTFT根据自身的栅源电压Vgs输出驱动电流I。
图17为本公开实施例提供的像素驱动电路的再一种电路结构示意图，如图17所示，在图16所示像素驱动电路的基础上，图17所示像素驱动电路还包括：第二复位电路6，第二复位电路6还包括第七晶体管T7。
考虑到第一节点N1在发光阶段处于浮接状态，而第一节点N1处电压的稳定性直接影响到发光器件OLED的发光效果，为此可将与第一节点N1相连的第七晶体管T7设计为氧化物晶体管，可有效减少第一节点N1通过第二晶体管T2的漏电。
图18为图17所示像素驱动电路的一种工作时序图，如图18所示，图18中所示第一控制信号端SC1(第三控制信号端SC3)、第二控制信号端SC2(第五控制信号端SC5)和第四控制信号端SC4的工作时序，与图16中所示第一控制信号端SC1(第三控制信号端SC3)、第二控制信号端SC2(第五控制信号端SC5)和第四控制信号端SC4的工作时序相同。下面仅对图18中发光控制信号端EM和第六控制信号端SC6在各阶段的工作时序进行详细描述。
在复位阶段t1，发光控制信号端EM提供的信号处于高电平，第六控制信号端SC6提供的信号处于高电平；第七晶体管T7处于导通状态，第四晶体管T4处于截止状态。第三电压Vref通过第七晶体管T7写入至第一节点N1，以对第一节点N1进行复位。
在补偿阶段t2和发光电压写入阶段t3，发光控制信号端EM提供的信号处于高电平，第六控制信号端SC6提供的信号处于低电平；第七晶体管T7处于截止状态，第四晶体管T4处于截止状态。
在发光阶段t4，发光控制信号端EM提供的信号处于低电平，第六控制信号端SC6提供的信号处于低电平；第四晶体管T4处于导通状态，第七晶体管T7处于截止状态。
图19为本公开实施例提供的像素驱动电路的再一种电路结构示意图，如图19所示，与图15中所示第二晶体管T2和第六晶体管T6均为低温多晶硅晶体管不同，图17中所示第二晶体管T2和第六晶体 管T6均为氧化物型晶体管，可有效减少第一节点N1通过第二晶体管T2的漏电以及减少发光器件OLED的第一极通过第六晶体管T6的漏电。
图20为图19所示像素驱动电路的一种工作时序图，如图20所示，图20中所示第一控制信号端SC1(第三控制信号端SC3)、第四控制信号端SC4和发光控制信号端EM的工作时序，与图16中所示第一控制信号端SC1(第三控制信号端SC3)、第四控制信号端SC4和发光控制信号端EM的工作时序相同；图20中所示第二控制信号端SC2(第五控制信号端SC5)在各阶段的电平状态，与图16中所示第二控制信号端SC2(第五控制信号端SC5)在各阶段的电平状态相反。具体工作过程此处不再赘述。
图15、图17、图19中稳压电压也可以不为上述第五晶体管T5，而是为前面实施例中所涉及的稳压电容C2，此种情况未给出相应附图。
需要说明的是，上述各实施例所提供像素驱动电路中的各晶体管可以分别独立选自N型晶体管或P型晶体管，仅通过对晶体管的类型以及对应的时序进行简单变换所得到的技术方案，也应属于本公开的保护范围。另外，在上述所有实施例中，不同技术特征之间可以相互组合，通过技术特征的组合所得到的新技术方案，也应属于本公开的保护范围。
基于同一发明构思，本公开实施例还提供了一种像素驱动电路的驱动方法。图21为本公开实施例提供的一种像素驱动电路的驱动方法的流程图，如图21所示，该像素驱动电路为前面实施例所提供的像素驱动电路，对于该像素驱动电路的具体描述可参见前面实施例中的内容，此处不再赘述；该驱动方法包括：
步骤S1、在补偿阶段，数据写入电路响应于第一控制信号端的信号的控制将数据线提供的数据电压写入至第二节点，补偿控制电路响应于第二控制信号端的信号的控制来获取驱动晶体管的阈值电压。
步骤S2、在发光电压写入阶段，补偿控制电路响应于第三控制信 号端的信号的控制将第三电压输入端提供的第三电压写入至第二节点，并根据第二节点处电压变化和阈值电压向第一节点写入能够对驱动晶体管进行阈值补偿的发光电压，稳压电路维持第三节点处电压的稳定。
步骤S3、在发光阶段，发光控制电路响应于发光控制信号端的信号的控制将第三节点与发光器件的第一极之间导通，驱动晶体管根据发光电压产生相应的驱动电流，以驱动发光器件发光。
对于上述步骤S1～步骤S3的具体描述，可参见前面实施例中的内容，此处不再赘述。
在本公开实施例中，通过在像素驱动电路内的第三节点处设置稳压电路，该稳压电路可在补偿控制电路向驱动晶体管的栅极写入发光电压过程中，减弱、甚至完全消除驱动晶体管的栅极与漏极之间寄生电容对驱动晶体管的漏极处电压的影响，以维持第三节点处电压的稳定，从而使得驱动晶体管所受偏压应力基本一致，驱动晶体管的阈值电压基本保持稳定，能够减弱磁滞效应的影响，进而能够有效改善显示装置的残影、闪烁的问题。
基于同一发明构思，本公开实施例还提供了一种显示基板，该显示基板包括：像素驱动电路，该像素驱动电路采用前面实施例提供的像素驱动电路，具体描述可参见前面实施例中的内容，此处不再赘述。
本公开实施例还提供了一种显示装置，该显示装置包括：显示基板，该显示基板采用前面实施例提供的显示基板。
本公开实施例中的显示装置可以为：电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (19)

  1. 一种像素驱动电路，其特征在于，包括：数据写入电路、补偿控制电路、发光控制电路、稳压电路和驱动晶体管，所述补偿控制电路与所述驱动晶体管的栅极连接于第一节点，所述补偿控制电路与所述数据写入电路连接于第二节点，所述补偿控制电路、所述发光控制电路、所述稳压电路以及所述驱动晶体管的第二极连接于第三节点；
    所述数据写入电路，与第一控制信号端和数据线连接，配置为响应于所述第一控制信号端的信号的控制将所述数据线提供的数据电压写入至所述第二节点；
    所述发光控制电路，与发光控制信号端和发光器件的第一极连接，配置为响应于所述发光控制信号端的信号的控制，来控制所述第三节点与所述发光器件的第一极之间的通断；
    所述补偿控制电路，与第二控制信号端、第三控制信号端和第三电压输入端连接，配置为响应于所述第二控制信号端的信号的控制来获取所述驱动晶体管的阈值电压，以及响应于所述第三控制信号端的信号的控制将所述第三电压输入端提供的第三电压写入至所述第二节点，并根据所述第二节点处电压变化和所述阈值电压向所述第一节点写入能够对所述驱动晶体管进行阈值补偿的发光电压；
    所述稳压电路，配置为在所述补偿控制电路向所述第一节点写入所述发光电压时维持所述第三节点处电压的稳定；
    所述驱动晶体管，其第一极与第一电压输入端连接，配置为根据所述发光电压产生相应的驱动电流。
  2. 根据权利要求1所述的像素驱动电路，其特征在于，所述稳压电路包括：第五晶体管；
    所述第五晶体管的控制极与第四控制信号端的第一极连接，所述第五晶体管的第一极与所述第三节点连接，所述第五晶体管的第二极 与所述第三电压输入端连接。
  3. 根据权利要求1所述的像素驱动电路，其特征在于，所述稳压电路包括：稳压电容；
    所述稳压电容的第一端与所述第三节点连接，所述稳压电容的第二端与第四电压输入端连接。
  4. 根据权利要求3所述的像素驱动电路，其特征在于，所述第四电压输入端为所述发光控制信号端。
  5. 根据权利要求1至4中任一所述的像素驱动电路，其特征在于，所述数据写入电路包括第一晶体管；
    所述第一晶体管的控制极与所述第一控制信号端连接，所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述第二节点连接。
  6. 根据权利要求5所述的像素驱动电路，其特征在于，所述第一晶体管为双栅型低温多晶硅晶体管。
  7. 根据权利要求1至4中任一所述的像素驱动电路，其特征在于，所述复位补偿电路包括：第二晶体管、第三晶体管和耦合电容；
    所述第二晶体管的控制极与所述第二控制信号端连接，所述第二晶体管的第一极与所述第一节点连接，所述第二晶体管的第二极与所述第三节点连接；
    所述第三晶体管的控制极与所述第三控制信号端连接，所述第三晶体管的第一极与所述第三电压输入端连接，所述第三晶体管的第二极与所述第二节点连接；
    所述耦合电容的第一端与所述第一节点连接，所述耦合电容的第二端与所述第二节点连接。
  8. 根据权利要求7所述的像素驱动电路，其特征在于，所述数据写入电路包括第一晶体管；
    所述第一晶体管的控制极与所述第一控制信号端连接，所述第一晶体管的第一极与所述数据线连接，所述第一晶体管的第二极与所述第二节点连接；
    所述第一晶体管为低温多晶硅晶体管，所述第三晶体管为氧化物晶体管；
    所述第一控制信号端与所述第三控制信号端为同一控制信号端。
  9. 根据权利要求7所述的像素驱动电路，其特征在于，还包括：第一复位电路；
    所述第一复位电路包括：第六晶体管；
    所述第六晶体管的控制极与所述第五控制信号端连接，所述第六晶体管的第一极与所述发光器件的第一极连接，所述第六晶体管的第二极与所述第三电压输入端连接；
    所述第二晶体管和所述第六晶体管均为低温多晶硅晶体管或均为氧化物晶体管；
    所述第二控制信号端与所述第五控制信号端为同一控制信号端。
  10. 根据权利要求7所述的像素驱动电路，其特征在于，所述第一晶体管为双栅型低温多晶硅晶体管。
  11. 根据权利要求1至4中任一所述的像素驱动电路，其特征在于，所述发光控制电路包括：第四晶体管；
    所述第四晶体管的控制极与所述发光控制信号端连接，所述第四晶体管的第一极与所述第三节点连接，所述第四晶体管的第二极与所述发光器件的第一极连接。
  12. 根据权利要求1至4中任一所述的像素驱动电路，其特征在于，还包括：第一复位电路；
    所述第一复位电路，与第五控制信号端、所述第三电压输入端和发光器件的第一极连接，配置为响应于所述第五控制信号端的信号的控制将所述第三电压输入端提供的第三电压写入至所述发光器件的第一极。
  13. 根据权利要求12所述的像素驱动电路，其特征在于，所述第一复位电路包括：第六晶体管；
    所述第六晶体管的控制极与所述第五控制信号端连接，所述第六晶体管的第一极与所述发光器件的第一极连接，所述第六晶体管的第二极与所述第三电压输入端连接。
  14. 根据权利要求1至4中任一所述的像素驱动电路，其特征在于，还包括：第二复位电路；
    所述第二复位电路，与第六控制信号端、所述第三电压输入端和所述第一节点连接，配置为响应于所述第六控制信号端的信号的控制将所述第三电压输入端提供的第三电压写入至所述第一节点。
  15. 根据权利要求14所述的像素驱动电路，其特征在于，所述第二复位电路包括：第七晶体管；
    所述第七晶体管的控制极与所述第六控制信号端连接，所述第七晶体管的第一极与所述第三电压输入端连接，所述第七晶体管的第二极与所述第一节点连接。
  16. 根据权利要求15所述的像素驱动电路，其特征在于，所述第七晶体管为氧化物晶体管。
  17. 一种像素驱动电路的驱动方法，其特征在于，所述像素驱动电路为权利要求1至16中任一所述像素驱动电路，所述驱动方法包括：
    补偿阶段，所述数据写入电路响应于所述第一控制信号端的信号的控制将所述数据线提供的数据电压写入至所述第二节点，所述补偿控制电路响应于所述第二控制信号端的信号的控制来获取所述驱动晶体管的阈值电压；
    发光电压写入阶段，所述补偿控制电路响应于所述第三控制信号端的信号的控制将所述第三电压输入端提供的第三电压写入至所述第二节点，并根据所述第二节点处电压变化和所述阈值电压向所述第一节点写入能够对所述驱动晶体管进行阈值补偿的发光电压，所述稳压电路维持所述第三节点处电压的稳定；
    发光阶段，所述发光控制电路响应于所述发光控制信号端的信号的控制将所述第三节点与所述发光器件的第一极之间导通，所述驱动晶体管根据所述发光电压产生相应的驱动电流，以驱动所述发光器件发光。
  18. 一种显示基板，其特征在于，包括：如上述权利要求1至16中任一所述像素驱动电路。
  19. 一种显示装置，其特征在于，包括：如上述权利要求18中所述显示基板。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116312376A (zh) * 2023-02-28 2023-06-23 合肥维信诺科技有限公司 一种像素电路及其驱动方法、显示面板

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112022007459T5 (de) * 2022-06-30 2025-04-17 Boe Technology Group Co., Ltd. Pixeltreiberschaltung, Antriebsverfahren für Pixeltreiberschaltung, und Anzeigefeld
KR20240081795A (ko) * 2022-12-01 2024-06-10 엘지디스플레이 주식회사 화소 회로 및 이를 포함하는 표시 장치
KR20240114223A (ko) * 2023-01-16 2024-07-23 엘지디스플레이 주식회사 화소 회로 및 화소 회로를 포함하는 표시 장치
WO2024174153A1 (zh) * 2023-02-23 2024-08-29 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
CN116386541B (zh) * 2023-06-05 2023-08-04 惠科股份有限公司 显示驱动电路、显示驱动方法及显示面板
KR20250000969A (ko) * 2023-06-27 2025-01-06 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
WO2025020130A1 (zh) * 2023-07-26 2025-01-30 京东方科技集团股份有限公司 像素电路、显示装置及驱动方法
KR20250064214A (ko) * 2023-11-02 2025-05-09 엘지디스플레이 주식회사 픽셀 회로와 이를 포함한 표시장치
CN117854441A (zh) * 2024-01-03 2024-04-09 京东方科技集团股份有限公司 显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035174A (zh) * 2011-09-29 2013-04-10 乐金显示有限公司 有机发光二极管显示器
CN103456267A (zh) * 2013-08-26 2013-12-18 北京京东方光电科技有限公司 触控显示驱动电路及其驱动方法和显示装置
CN104064148A (zh) * 2014-06-30 2014-09-24 上海天马微电子有限公司 一种像素电路、有机电致发光显示面板及显示装置
CN104217682A (zh) * 2014-09-04 2014-12-17 上海天马有机发光显示技术有限公司 一种像素电路、有机电致发光显示面板及显示装置
CN106910468A (zh) * 2017-04-28 2017-06-30 上海天马有机发光显示技术有限公司 显示面板、显示装置及像素电路的驱动方法
CN212010325U (zh) * 2020-04-02 2020-11-24 深圳柔宇显示技术有限公司 像素单元、阵列基板与显示终端

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101985501B1 (ko) * 2013-01-08 2019-06-04 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치, 및 그 구동 방법
US10373554B2 (en) * 2015-07-24 2019-08-06 Ignis Innovation Inc. Pixels and reference circuits and timing techniques
CN105185304B (zh) * 2015-09-09 2017-09-22 京东方科技集团股份有限公司 一种像素电路、有机电致发光显示面板及显示装置
KR102509185B1 (ko) 2015-09-25 2023-03-13 엘지디스플레이 주식회사 유기발광다이오드 표시 패널, 이를 구비하는 유기발광다이오드 표시 장치 및 이의 구동 방법
US10262586B2 (en) * 2016-03-14 2019-04-16 Apple Inc. Light-emitting diode display with threshold voltage compensation
CN108806605A (zh) * 2018-06-15 2018-11-13 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板和显示装置
KR102653575B1 (ko) * 2019-07-29 2024-04-03 엘지디스플레이 주식회사 표시 장치
CN110738964A (zh) * 2019-10-29 2020-01-31 京东方科技集团股份有限公司 像素电路及显示装置
CN111754941B (zh) * 2020-07-29 2022-04-15 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板和显示装置
CN115101011B (zh) * 2021-07-21 2024-12-13 武汉天马微电子有限公司 配置成控制发光元件的像素电路
CN115035858B (zh) * 2022-06-29 2024-07-23 武汉天马微电子有限公司 像素电路及其驱动方法、显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035174A (zh) * 2011-09-29 2013-04-10 乐金显示有限公司 有机发光二极管显示器
CN103456267A (zh) * 2013-08-26 2013-12-18 北京京东方光电科技有限公司 触控显示驱动电路及其驱动方法和显示装置
CN104064148A (zh) * 2014-06-30 2014-09-24 上海天马微电子有限公司 一种像素电路、有机电致发光显示面板及显示装置
CN104217682A (zh) * 2014-09-04 2014-12-17 上海天马有机发光显示技术有限公司 一种像素电路、有机电致发光显示面板及显示装置
CN106910468A (zh) * 2017-04-28 2017-06-30 上海天马有机发光显示技术有限公司 显示面板、显示装置及像素电路的驱动方法
CN212010325U (zh) * 2020-04-02 2020-11-24 深圳柔宇显示技术有限公司 像素单元、阵列基板与显示终端

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116312376A (zh) * 2023-02-28 2023-06-23 合肥维信诺科技有限公司 一种像素电路及其驱动方法、显示面板

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