[go: up one dir, main page]

WO2022061852A1 - 像素驱动电路及显示面板 - Google Patents

像素驱动电路及显示面板 Download PDF

Info

Publication number
WO2022061852A1
WO2022061852A1 PCT/CN2020/118279 CN2020118279W WO2022061852A1 WO 2022061852 A1 WO2022061852 A1 WO 2022061852A1 CN 2020118279 W CN2020118279 W CN 2020118279W WO 2022061852 A1 WO2022061852 A1 WO 2022061852A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrode
control
light
circuit
Prior art date
Application number
PCT/CN2020/118279
Other languages
English (en)
French (fr)
Inventor
刘冬妮
玄明花
郑皓亮
肖丽
陈亮
张振宇
赵蛟
陈昊
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/309,917 priority Critical patent/US11798473B2/en
Priority to PCT/CN2020/118279 priority patent/WO2022061852A1/zh
Priority to CN202080002144.4A priority patent/CN114586091B/zh
Publication of WO2022061852A1 publication Critical patent/WO2022061852A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the invention belongs to the field of display technology, and in particular relates to a pixel driving circuit and a display panel.
  • Micro Light Emitting Diode (Micro LED) display technology is developing rapidly. Due to its outstanding advantages: small size, low power consumption, high color saturation, fast response speed, long life, etc. Workers' input into research.
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a pixel driving circuit and a display panel.
  • an embodiment of the present disclosure provides a pixel driving circuit, which includes: a data writing subcircuit, a threshold compensation subcircuit, a driving subcircuit, a storage subcircuit, and a voltage maintaining subcircuit; wherein,
  • the data writing sub-circuit is configured to transmit the data voltage signal to the first end of the driving sub-circuit in response to the first scanning signal;
  • the threshold compensation sub-circuit is configured to compensate the threshold voltage of the driving sub-circuit in response to the second scan signal
  • the storage subcircuit is configured to store the data voltage signal
  • the driving sub-circuit is configured to provide a driving current for the light-emitting device to be driven according to the voltage of the first terminal and the control terminal;
  • the voltage maintenance subcircuit is configured to maintain the control terminal voltage of the driving subcircuit when the first terminal voltage of the driving subcircuit jumps.
  • the voltage maintaining sub-circuit includes a first capacitor, the first plate of the first capacitor is connected to the control terminal of the driving sub-circuit, and the second plate of the first capacitor is connected to the driving sub-circuit second end.
  • the voltage maintaining sub-circuit includes a first capacitor, the first plate of the first capacitor is connected to the control terminal of the driving sub-circuit, and the second plate of the first capacitor is connected to the reference voltage terminal.
  • the capacitance value of the first capacitor is 0.1pF-10pF.
  • the pixel driving circuit further includes:
  • the first lighting control sub-circuit is configured to control whether the first voltage can be written into the first end of the first driving sub-circuit of the driving sub-circuit in response to the first lighting control signal.
  • the first light-emitting control sub-circuit includes a first light-emitting control transistor
  • the first electrode of the first light-emitting control transistor is connected to the first power supply voltage line
  • the second electrode of the first light-emitting control transistor is connected to the first end of the driving sub-circuit
  • the control electrode of the first light-emitting control transistor Connect the first lighting control line.
  • the pixel driving circuit further includes:
  • the first reset sub-circuit is configured to reset the voltage of the control terminal of the driving sub-circuit through the first initialization signal in response to the first reset control signal.
  • the first reset sub-circuit includes a first reset transistor
  • the first pole of the first reset transistor is connected to the first initialization signal terminal
  • the second pole of the first reset transistor is connected to the control terminal of the driving sub-circuit
  • the control pole of the first reset transistor is connected to the first reset transistor.
  • the pixel driving circuit further includes:
  • the second light-emitting control sub-circuit is configured to turn on or off the connection between the driving sub-circuit and the light-emitting device to be driven in response to the second light-emitting control signal.
  • the second light-emitting control sub-circuit includes a second light-emitting control transistor
  • the first electrode of the second light-emitting control transistor is connected to the second end of the driving subcircuit, the second electrode of the second light-emitting control transistor is connected to the first electrode of the light-emitting device to be driven, and the second light-emitting control transistor is connected to the first electrode of the light-emitting device to be driven.
  • the control electrode of the light-emitting control transistor is connected to the second light-emitting control line.
  • the pixel driving circuit further includes:
  • the second reset sub-circuit is configured to initialize the light emitting device to be driven by the second initialization signal in response to the second reset control signal.
  • the second reset sub-circuit includes a second reset transistor
  • the first electrode of the second reset transistor is connected to the first electrode of the light-emitting device to be driven, the second electrode of the second reset transistor is connected to the second initialization signal terminal, and the control of the second reset transistor The pole is connected to the second reset control signal line.
  • the pixel driving circuit further includes: a time control sub-circuit, configured to respond to the time control signal and control the light-emitting time of the light-emitting device to be driven through the time modulation signal and the third light-emitting control signal.
  • the time control sub-circuit includes a first time modulation transistor, a second time modulation transistor, a third light emission control transistor and a second capacitor;
  • the first electrode of the first time modulation transistor is connected to the second end of the driving sub-circuit, the second electrode of the first time modulation transistor is connected to the first electrode of the third light-emitting control transistor, and the first The control electrode of the time modulation transistor is connected to the third light-emitting control line;
  • the first electrode of the second time modulation transistor is connected to the time modulation signal terminal, the second electrode of the second time modulation transistor is connected to the control electrode of the third light-emitting control transistor, and the control electrode of the second time modulation transistor Connect the time control signal line;
  • the second electrode of the third light-emitting control transistor is connected to the first electrode of the light-emitting device to be driven, and the control electrode of the third light-emitting control transistor is connected to the first electrode plate of the second capacitor;
  • the second plate of the second capacitor is connected to the common voltage terminal.
  • the third light-emitting control line is configured to write the working level signal multiple times in one frame of display time, and the duration of each writing working level is unequal.
  • the driving subcircuit includes a driving transistor
  • the threshold compensation subcircuit includes a threshold compensation transistor
  • the data writing subcircuit includes a data writing transistor
  • the storage subcircuit includes a storage capacitor
  • the first electrode of the driving transistor is used as the first terminal of the driving sub-circuit
  • the second electrode of the driving transistor is used as the second terminal of the driving sub-circuit
  • the control electrode of the driving sub-circuit is used as the the control terminal of the driving sub-circuit
  • the first electrode of the drive transistor is connected to the second electrode of the data writing transistor, the second electrode of the drive transistor is connected to the first electrode of the threshold compensation transistor, and the control electrode of the drive transistor is connected to the threshold value the second electrode of the compensation transistor and the first electrode plate of the storage capacitor;
  • the first electrode of the data writing transistor is connected to the data line, and the control electrode of the data writing transistor is connected to the first scan line;
  • the control electrode of the threshold compensation transistor is connected to the second scan line
  • the second plate of the storage capacitor is connected to the first power supply voltage line.
  • the capacitance value of the storage capacitor is 0.1pF-10pF.
  • Embodiments of the present disclosure further provide a pixel driving circuit, which includes: a data writing subcircuit, a threshold compensation subcircuit, a driving subcircuit, a storage subcircuit, a first light emission control subcircuit, a second light emission control subcircuit, a first light emission control subcircuit, and a first light emission control subcircuit.
  • a reset subcircuit, a second reset subcircuit and a voltage maintenance subcircuit wherein,
  • the driving subcircuit includes a driving transistor, the threshold compensation subcircuit includes a threshold compensation transistor, the data writing subcircuit includes a data writing transistor, the storage subcircuit includes a storage capacitor, and the first light emission control subcircuit includes a first lighting control subcircuit.
  • a light-emitting control transistor the second light-emitting control sub-circuit includes a second light-emitting control transistor
  • the first reset sub-circuit includes a first reset transistor
  • the second reset sub-circuit includes a second reset transistor
  • the voltage maintains the subcircuit includes a first capacitor
  • the first electrode of the drive transistor is connected to the second electrode of the data writing transistor and the second electrode of the first light emission control transistor, and the second electrode of the drive transistor is connected to the first electrode of the threshold compensation transistor , the control electrode of the driving transistor is connected to the second electrode of the threshold compensation transistor, the first electrode plate of the storage capacitor and the first electrode plate of the first capacitor;
  • the first electrode of the data writing transistor is connected to the data line, and the control electrode of the data writing transistor is connected to the first scan line;
  • the control electrode of the threshold compensation transistor is connected to the second scan line
  • the second plate of the storage capacitor is connected to the first power supply voltage line
  • the first electrode of the first light-emitting control transistor is connected to the first power supply voltage line, and the control electrode of the first light-emitting control transistor is connected to the first light-emitting control line;
  • the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor, the second electrode of the second light-emitting control transistor is connected to the first electrode of the light-emitting device to be driven, and the second light-emitting device is connected to the first electrode of the light-emitting device to be driven.
  • the control electrode of the control transistor is connected to the second light-emitting control line;
  • the first electrode of the first reset transistor is connected to the first initialization signal terminal, the second electrode of the first reset transistor is connected to the control electrode of the driving transistor, and the control electrode of the first reset transistor is connected to the first reset transistor. reset control signal line;
  • the first electrode of the second reset transistor is connected to the first electrode of the light-emitting device to be driven, the second electrode of the second reset transistor is connected to the second initialization signal terminal, and the control of the second reset transistor The pole is connected to the second reset control signal line;
  • the second electrode plate of the first capacitor is connected to the second electrode or the reference voltage terminal of the driving transistor.
  • An embodiment of the present disclosure further provides a pixel driving circuit, which includes: a data writing subcircuit, a threshold compensation subcircuit, a driving subcircuit, a storage subcircuit, a first lighting control subcircuit, a first reset subcircuit, and a time control subcircuit and the voltage maintenance subcircuit; wherein,
  • the driving subcircuit includes a driving transistor, the threshold compensation subcircuit includes a threshold compensation transistor, the data writing subcircuit includes a data writing transistor, the storage subcircuit includes a storage capacitor, and the first light emission control subcircuit includes a first lighting control subcircuit.
  • a light-emitting control transistor the second light-emitting control sub-circuit includes a second light-emitting control transistor
  • the first reset sub-circuit includes a first reset transistor
  • the second reset sub-circuit includes a second reset transistor
  • the time control The sub-circuit includes a first time modulation transistor, a second time modulation transistor, a third light-emitting control transistor and a second capacitor
  • the voltage maintaining sub-circuit includes a first capacitor
  • the first electrode of the drive transistor is connected to the second electrode of the data writing transistor and the second electrode of the first light emission control transistor, and the second electrode of the drive transistor is connected to the first electrode of the threshold compensation transistor , the control electrode of the driving transistor is connected to the second electrode of the threshold compensation transistor, the first electrode plate of the storage capacitor and the first electrode plate of the first capacitor;
  • the first electrode of the data writing transistor is connected to the data line, and the control electrode of the data writing transistor is connected to the first scan line;
  • the control electrode of the threshold compensation transistor is connected to the second scan line
  • the second plate of the storage capacitor is connected to the first power supply voltage line
  • the first electrode of the first light-emitting control transistor is connected to the first power supply voltage line, and the control electrode of the first light-emitting control transistor is connected to the first light-emitting control line;
  • the first electrode of the first reset transistor is connected to the first initialization signal terminal, the second electrode of the first reset transistor is connected to the control electrode of the driving transistor, and the control electrode of the first reset transistor is connected to the first reset transistor. reset control signal line;
  • the first electrode of the first time modulation transistor is connected to the second electrode of the driving transistor, the second electrode of the first time modulation transistor is connected to the first electrode of the third light-emitting control transistor, and the first time The control electrode of the modulation transistor is connected to the third light-emitting control line;
  • the first electrode of the second time modulation transistor is connected to the time modulation signal terminal, the second electrode of the second time modulation transistor is connected to the control electrode of the third light-emitting control transistor, and the control electrode of the second time modulation transistor Connect the time control signal line;
  • the second electrode of the third light-emitting control transistor is connected to the first electrode of the light-emitting device to be driven, and the control electrode of the third light-emitting control transistor is connected to the first electrode plate of the second capacitor;
  • the second plate of the second capacitor is connected to the common voltage terminal.
  • an embodiment of the present disclosure is a display panel, which includes a plurality of pixel units, and each of the plurality of pixel units includes a pixel driving circuit and a light-emitting device; wherein, the pixel driving circuit is any one of the above pixel driver circuit.
  • the light-emitting device includes: a miniature inorganic light-emitting diode.
  • FIG. 1 is a schematic diagram of an exemplary display substrate structure.
  • FIG. 2 is a schematic diagram of an exemplary pixel driving circuit.
  • FIG. 3 is an operation timing diagram of the pixel driving circuit shown in FIG. 2 .
  • FIG. 4 is a cross-sectional view of a driving transistor and a storage capacitor in the pixel driving circuit shown in FIG. 2 .
  • FIG. 5 is a simulation diagram showing the variation of the source voltage Vs and the gate voltage Vg of the driving transistor in each working stage of the pixel driving circuit shown in FIG. 2 .
  • FIG. 6 is a diagram showing the corresponding relationship between driving current and time generated by the pixel driving circuit of FIG. 2 .
  • FIG. 7 is a schematic diagram of a pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 10 is an operation timing diagram of the pixel driving circuit shown in FIG. 9 .
  • FIG. 1 is a schematic diagram of an exemplary structure of a display substrate
  • FIG. 2 is a schematic diagram of an exemplary pixel driving circuit
  • the display substrate includes a plurality of pixel units arranged in an array, each Each of the pixel units 100 includes a pixel driving circuit and a light-emitting device D.
  • the pixel driving circuit in each pixel unit 100 may include: a first reset sub-circuit 1, a threshold compensation sub-circuit 2, a driving sub-circuit 3, a data writing sub-circuit 4, a first light-emitting control sub-circuit 5, and a second light-emitting control sub-circuit.
  • Circuit 6 , second reset sub-circuit 7 and storage sub-circuit 8 are examples of the display substrate.
  • the first reset sub-circuit 1 is connected to the control terminal of the driving sub-circuit 3, and is configured to reset the control terminal of the driving sub-circuit 3 under the control of the first reset signal.
  • the threshold compensation sub-circuit 2 is electrically connected to the control terminal and the second terminal of the driving sub-circuit 3 respectively, and is configured to perform threshold compensation on the driving sub-circuit 3 .
  • the data writing sub-circuit 4 is electrically connected to the first end of the driving sub-circuit 3, and is configured to write the data signal into the storage sub-circuit under the control of the scanning signal.
  • the storage sub-circuits 8 are respectively electrically connected to the control terminal of the driving sub-circuit 3 and the first power supply voltage line VDD, and are configured to store data signals.
  • the first light-emitting control sub-circuit 5 is respectively connected to the first power supply voltage line VDD and the first end of the driving sub-circuit 3, and is configured to turn on or off the connection between the driving sub-circuit 3 and the first power supply voltage line VDD
  • the second light-emitting control sub-circuit 6 is respectively electrically connected to the second end of the driving sub-circuit 3 and the first electrode of the light-emitting device D, and is configured to turn on or off the connection between the driving sub-circuit 3 and the light-emitting device D open.
  • the second reset sub-circuit 7 is electrically connected to the first electrode of the light-emitting device D, and is configured to reset the control terminal of the driving sub-circuit 3 and the first electrode of the light-emitting device D under the control of the second reset control signal.
  • the first reset sub-circuit includes a first reset transistor T1
  • the threshold compensation sub-circuit 2 includes a threshold compensation transistor T2
  • the driving sub-circuit 3 includes a driving transistor T3
  • the control terminal of the driving sub-circuit 3 includes the control of the driving transistor T3
  • the first terminal of the driving sub-circuit 3 includes the first pole of the driving transistor T3, and the second terminal of the driving sub-circuit 3 includes the second pole of the driving transistor T3.
  • the data writing sub-circuit 4 includes a data writing transistor T4, the storage sub-circuit 7 includes a storage capacitor Cst, the first light-emitting control sub-circuit 5 includes a first light-emitting control transistor T5, and the second light-emitting control sub-circuit 6 includes a second light-emitting control transistor T6, the second reset sub-circuit 7 includes a second reset transistor T7.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take the transistors as P-type transistors (for example, P-type MOS transistors) as an example in detail.
  • the driving transistor T3, the data writing transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the first light-emitting control transistor T5, the first light-emitting Both the reset transistor T1 and the second reset transistor T7 and the like may be P-type transistors.
  • the transistors in the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (eg, N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs. .
  • N-type transistors eg, N-type MOS transistors
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
  • the control electrode is used as the gate of the transistor, one of the first electrode and the second electrode is used as the source electrode of the transistor, and the other is used as the transistor.
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain of the transistor can be indistinguishable in physical structure.
  • the first electrode is directly described as the source electrode and the second electrode as the drain electrode, so all or part of the source electrodes of the transistors in the embodiments of the present disclosure are directly described. and drain are interchangeable as required.
  • the drain of the data writing transistor T4 is electrically connected to the source of the driving transistor T3, the source of the data writing transistor T4 is configured to be electrically connected to the data line Data to receive a data signal, and the data writing transistor T4
  • the gate is configured to be electrically connected to the first scan signal line Ga1 to receive the scan signal;
  • the second plate of the storage capacitor Cst is electrically connected to the first power supply voltage line VDD, and the first plate of the storage capacitor Cst is connected to the drive transistor T3
  • the gate of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, the drain of the threshold compensation transistor T2 is electrically connected to the drain of the driving transistor T3, and the gate of the threshold compensation transistor T2 is configured as is electrically connected to the second scan signal line Ga2 to receive the compensation control signal;
  • the source of the first reset transistor T1 is configured to be electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal, and the drain of the first reset transistor T1 Electrically connected to
  • the control signal line Rst2 is electrically connected to receive the second reset control signal; the source of the first light-emitting control transistor T5 is electrically connected to the first power supply voltage line VDD, and the drain of the first light-emitting control transistor T5 is electrically connected to the source of the driving transistor T3.
  • the gate of the first light-emitting control transistor T5 is configured to be electrically connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal;
  • the source of the second light-emitting control transistor T6 is electrically connected to the drain of the driving transistor T3 , the drain of the second light-emitting control transistor T6 is electrically connected to the first electrode D1 of the light-emitting device D, and the gate of the second light-emitting control transistor T6 is configured to be electrically connected to the second light-emitting control signal line EM2 to receive the second light-emitting control signal;
  • the second electrode of the light-emitting device D is electrically connected to the second power supply terminal VSS.
  • one of the first power supply voltage line VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal.
  • the first power supply voltage line VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power supply terminal VSS can be a voltage source to output a constant
  • the second voltage, the second voltage is a negative voltage, etc.
  • the second power supply terminal VSS may be grounded.
  • the scan signal and the compensation control signal may be the same, that is, the gate of the data writing transistor T4 and the gate of the threshold compensation transistor T2 may be electrically connected to the same signal line, such as the first scan signal line Ga1, to To receive the same signal (eg, scan signal), at this time, the display substrate may not be provided with the second scan signal line Ga2, thereby reducing the number of signal lines.
  • the gate of the data writing transistor T4 and the gate of the threshold compensation transistor T2 may also be electrically connected to different signal lines respectively, that is, the gate of the data writing transistor T4 is electrically connected to the first scanning signal line Ga1, and the threshold The gate of the compensation transistor T2 is electrically connected to the second scan signal line Ga2, and the first scan signal line Ga1 and the second scan signal line Ga2 transmit the same signal.
  • the scan signal and the compensation control signal may also be different, so that the gate of the data writing transistor T4 and the threshold compensation transistor T2 can be controlled separately and independently, increasing the flexibility of controlling the pixel circuit.
  • the gate of the data writing transistor T4 and the gate of the threshold compensation transistor T2 are electrically connected to the first scan signal line Ga(A) as an example for description.
  • the first lighting control signal and the second lighting control signal may be the same, that is, the gate of the first lighting control transistor T5 and the gate of the second lighting control transistor T6 may be electrically connected to the same signal line, for example
  • the first light-emitting control signal line EM1 is used to receive the same signal (eg, the first light-emitting control signal).
  • the display substrate may not have the second light-emitting control signal line EM2 to reduce the number of signal lines.
  • the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 may also be electrically connected to different signal lines respectively, that is, the gate of the first light-emitting control transistor T5 is electrically connected to the first light-emitting control transistor T5.
  • the gate of the second light emission control transistor T6 is electrically connected to the second light emission control signal line EM2
  • the signals transmitted by the first light emission control signal line EM1 and the second light emission control signal line EM2 are the same.
  • first light-emitting control transistor T5 and the second light-emitting control transistor T6 are different types of transistors, for example, the first light-emitting control transistor T5 is a P-type transistor and the second light-emitting control transistor T6 is an N-type transistor
  • the first lighting control signal and the second lighting control signal may also be different, which is not limited by the embodiment of the present disclosure.
  • the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both connected to the light-emitting control line EM for illustration.
  • the first reset control signal and the second reset control signal may be the same, that is, the gate of the first reset transistor T1 and the gate of the second reset transistor T7 may be electrically connected to the same signal line, eg, the first reset control signal
  • the line Rst1 is used to receive the same signal (for example, the first sub-reset control signal).
  • the second reset control signal line Rst2 may not be provided on the display substrate to reduce the number of signal lines.
  • the gate of the first reset transistor T1 and the gate of the second reset transistor T7 may also be electrically connected to different signal lines respectively, that is, the gate of the first reset transistor T1 is electrically connected to the first reset control signal line Rst1 , the gate of the second reset transistor T7 is electrically connected to the second reset control signal line Rst2, and the signals transmitted by the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same.
  • the first reset control signal and the second reset control signal may also be different.
  • the gate of the first reset transistor T1 and the gate of the second reset transistor T7 are both electrically connected to the reset control signal line Rst as an example.
  • the second reset control signal may be the same as the scan signal, i.e., the gate of the second reset transistor T7 may be electrically connected to the scan signal line Ga(A) to receive the scan signal as the second sub-reset control signal.
  • the source of the first reset transistor T1 and the drain of the second reset transistor T7 are respectively connected to the first reset power terminal Vinit1 and the second reset power terminal Vinit2, and the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be It is a DC reference voltage terminal to output a constant DC reference voltage.
  • the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same, for example, the source of the first reset transistor T1 and the drain of the second reset transistor T7 are connected to the same reset power terminal.
  • the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be high voltage terminals or low voltage terminals, as long as they can provide the first reset signal and the first reset signal to control the gate of the driving transistor T3 and the first reset signal of the light-emitting element.
  • One electrode D1 can be reset, which is not limited in the present disclosure.
  • the source of the first reset transistor T1 and the drain of the second reset transistor T7 may both be connected to the reset power signal line Init.
  • the gate of the first reset transistor T1 and the gate of the second reset transistor T7 are both electrically connected to Rst1; the source of the first reset transistor T1 and the gate of the second reset transistor are both electrically connected to Rst1; The drains of T7 are all electrically connected to the reset power signal line Init as an example for description.
  • the driving sub-circuit, data writing sub-circuit, storage sub-circuit, threshold compensation sub-circuit and reset sub-circuit in the pixel circuit shown in FIG. 2 are only illustrative.
  • the specific structures of the subcircuits, such as the subcircuit, the threshold compensation subcircuit, and the reset subcircuit can be set according to actual application requirements, which are not specifically limited in the embodiments of the present disclosure.
  • the pixel circuit of the sub-pixel may also be a structure including other numbers of transistors and capacitors
  • the circuit structure such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, is not limited in this embodiment of the present disclosure.
  • the light-emitting device D may be a micro inorganic light-emitting diode, and further, may be a current-type light-emitting diode, such as a micro light-emitting diode (Micro Light Emitting Diode, Micro LED) or a mini light-emitting diode (Mini Light Emitting Diode, Mini LED).
  • the light-emitting device D in the embodiment of the invention may also be an organic electroluminescent diode (Organic Light Emitting Diode, OLED).
  • One of the first electrode and the second electrode of the light-emitting device D is an anode, and the other is a cathode; in the embodiment of the present invention, the first electrode of the light-emitting device D is an anode and the second electrode is a cathode as an example for description .
  • FIG. 3 is a working timing diagram of the pixel driving circuit shown in FIG. 2; as shown in FIGS. 2 and 3, the driving method of the pixel driving circuit described above may include the following stages:
  • Reset stage (t1) the reset control signal line Rst writes a low-level signal, and the scan line Ga(A) and the light-emitting control line EM write a high-level signal; the first reset transistor T1 and the second reset transistor T7 are turned on, driving The initial voltage Vinit written to the gate of the transistor T3 by the reset power signal line Init prepares for the writing of the writing data voltage Vdata in the next frame.
  • the anode of the light-emitting device D writes an initialization voltage (Vinit ⁇ VSS) through the second reset transistor T7, so that the light-emitting device D is no longer in the forward conduction state, and the internal electric field formed by the directional movement of the impurity ions in the light-emitting device D gradually disappears, thereby The characteristics of the light emitting device D are restored.
  • Data writing and threshold compensation stage (t2) the scanning line Ga (A) is written as a low-level signal, the reset control signal line Rst and the first light-emitting control line EM are written with a high-level signal; the data writing transistors T4 and Threshold compensation transistor T2 is turned on.
  • the driving transistor T3 is connected to a diode structure by the threshold compensation transistor T2.
  • the data voltage Vdata written on the data line Data is written to the gate of the driving transistor T3 through the data writing transistor T4 and the threshold compensation transistor T2 until the driving transistor T3 is turned off.
  • the gate voltage of the driving transistor T3 is Vdata+Vth (Vth ⁇ 0, Vth is the threshold voltage of the driving transistor T3 ), and is stored in the storage capacitor Cst.
  • the voltages of the first plate and the second plate of the storage capacitor Cst are Vdata+Vth and Vd, respectively.
  • Light-emitting stage (t3) the light-emitting control line EM writes a low-level signal
  • the scan line Ga (A) and the reset control signal line Rst write a high-level signal
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both When turned on, the source of the driving transistor T3 is connected to the first power supply voltage line VDD, and the source voltage of the driving transistor T3 instantaneously changes from Vdata in the previous stage to Vdd.
  • the light-emitting device D emits light under the driving of the driving transistor T3.
  • the driving transistor T3 works in the saturation region, the gate voltage of the driving transistor T3 is Vdata+Vth, and the source voltage of the driving transistor T3 is Vdd.
  • the light-emitting current of the light-emitting device D is equal to the current flowing through the driving transistor T3, and its expression is as follows:
  • FIG. 4 is a cross-sectional view of the driving transistor and the storage capacitor in the pixel driving circuit shown in FIG. 2; as shown in FIG. 4, the driving transistor T3 adopts a top-gate thin film transistor, and a buffer layer 102 is formed on the substrate 101, and the driving transistor T3
  • the active layer 201 is formed on the side of the buffer layer 102 away from the substrate 101
  • the first gate insulating layer 103 is formed on the side of the active layer 201 of the driving transistor away from the substrate 101
  • the first plate 301 is formed on the side of the buffer layer 102 away from the substrate 101
  • the second gate insulating layer 104 is formed on the side of the gate 202 of the driving transistor away from the substrate 101; the second gate insulating layer 104 is away from the substrate.
  • One side of 101 forms the second electrode plate 302 of the storage capacitor Cst; the interlayer insulating layer 105 is formed on the side of the second electrode plate 302 of the storage capacitor Cst away from the substrate, and the source electrode 203 and the drain electrode 204 of the driving transistor T3 are formed on The interlayer insulating layer 105 is on the side facing away from the substrate 101 .
  • the inventors found that when a micro inorganic light-emitting diode is used as a light-emitting device, the driving current of the pixel driving circuit needs to be ⁇ A level or mA level. At this time, the driving transistor T3 in the pixel driving circuit pre-generates a relatively stable output current.
  • FIG. 5 is a simulation diagram showing the variation of the source voltage Vs and the gate voltage Vg of the driving transistor in each working stage of the pixel driving circuit shown in FIG. 2 . As shown in FIG.
  • one solution is to increase the storage capacitor Cst, but after the storage capacitor Cst is increased, since the second plate 302 of the storage capacitor Cst is connected to the first power supply voltage line VDD, the data line Data and the first power supply
  • the voltage lines VDD are adjacent and arranged side by side, and there is a certain coupling capacitance between them.
  • FIG. 7 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a pixel driving circuit, which may include the above-mentioned data writing sub-circuit 4, a threshold value Compensation sub-circuit 2 , driving sub-circuit 3 , storage sub-circuit 8 , in particular, the pixel driving circuit further includes a voltage maintaining sub-circuit 9 .
  • the voltage maintaining sub-circuit 9 is electrically connected to the first terminal of the driving sub-circuit 3, and is configured to maintain the control terminal voltage of the driving sub-circuit 3 when the voltage of the first terminal of the driving sub-circuit 3 jumps.
  • the driving sub-circuit 3 may include a driving transistor T3, the source of the driving transistor T3 is used as the first terminal of the driving sub-circuit 3, the drain of the driving transistor T3 is used as the second terminal of the driving sub-circuit 3, The gate of the driving transistor T3 is used as the control terminal of the driving sub-circuit 3 .
  • the voltage maintaining sub-circuit 9 in the embodiment of the present disclosure is configured to maintain the control terminal voltage of the driving sub-circuit 3, that is, maintain the voltage of the gate of the driving transistor T3.
  • the driving sub-circuit 3 includes the driving transistor T3 as an example for description.
  • both the data writing sub-circuit 4 and the threshold compensation sub-circuit 2 work under the control of the scan signal, and at this time the gate and drain of the driving transistor T3 are blocked by the threshold compensation sub-circuit 2 connection, the data voltage signal Vdata is written to the source of the driving transistor T3, and the voltage of the gate of the driving transistor T3 at this stage is Vdata+Vth (Vth ⁇ 0, Vth is the threshold voltage of the driving transistor T3).
  • the voltage of the source of the driving transistor T3 becomes the first voltage Vdd, that is, from the data writing and threshold compensation stage to the light-emitting stage, the source voltage of the driving transistor T3 jumps from Vdata to Vdd, which occurs Large instantaneous change, in the embodiment of the present disclosure, by setting the voltage maintenance sub-circuit 9, so that the gate of the driving electrode tube will not change greatly when the voltage of its source changes greatly, so as to make the light emitting In the stage, the current output by the driving transistor T3 is stable, so as to ensure that the light-emitting device D to be driven emits light normally.
  • the voltage maintaining sub-circuit 9 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the gate of the driving transistor T3, and is configured to jump at the source voltage of the driving transistor T3 When changing, the gate voltage of the driving transistor T3 is maintained.
  • the gate voltage of the driving transistor T3 is kept stable by the first capacitor C1, which can ensure that the light-emitting device D in the display stage can emit light normally, and the storage capacitor Cst is increased to maintain the driving transistor T3 compared with the related art.
  • the size of the storage capacitor Cst can be reduced (the area of the two pole pieces of the storage capacitor Cst can be reduced), so the area of the pixel driving circuit can be reduced, thereby improving the application of the The resolution of the display panel of the pixel driving circuit, at the same time, it can also avoid the problem that the capacitance of the first power supply voltage line VDD increases after the storage capacitor Cst increases, and the current changes caused by the capacitive coupling jump of VDD when the data line Data jumps. .
  • the first electrode plate of the first capacitor C1 is connected to the gate of the driving transistor T3
  • the second electrode plate of the first capacitor C1 is connected to the drain electrode of the driving transistor T3 .
  • the reason for this connection is that the drain voltage of the driving transistor T3 is Vdata+Vth in the data writing and threshold compensation stages, and the drain voltage of the driving transistor T3 is Vdd+Vds in the light-emitting stage, where Vds represents the driving transistor in the light-emitting stage.
  • Vds is about -3V to -5V
  • Vth is about -0.7V to -1.3V
  • the maximum voltage difference between Vdd and Vdata does not exceed 5V.
  • (Vdd+Vds)-(Vdata+Vth) is about 1V, so under the bootstrap action of the first capacitor C1, the drain voltage of the driving transistor T3 changes from the data writing and threshold compensation stage to the light-emitting stage It is relatively small, so under the action of the first capacitor C1, the gate of the driving transistor T3 will not change significantly, so the gate voltage of the driving transistor T3 can be effectively maintained to ensure that the driving transistor is driven in the light-emitting stage.
  • the stability of T3 enables the light-emitting device D to emit light normally.
  • the gate of the driving transistor T3 is connected to the first plate of the first capacitor C1, and the drain of the driving transistor T3 is connected to the second plate of the first capacitor C1.
  • the first electrode plate of the first capacitor C1 is formed at the same time as the gate of the driving transistor T3 is formed, and the second electrode plate of the first capacitor C1 is formed at the same time as the drain electrode of the driving transistor T3 is formed. In this way, the thickness of the display panel for the pixel driving circuit will not be increased, and the process steps will also be increased.
  • the first electrode plate and the second substrate can also be formed by two separate layers of metal, respectively.
  • FIG. 8 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure; as shown in FIG. 8 , as in the pixel driving circuit shown in FIG. 7 , the first plate of the first capacitor C1 is connected to a driving transistor The gate of T3 and the second plate of the first capacitor C1 are connected to the reference voltage terminal Vref.
  • the reference voltage terminal Vref is continuously written with a fixed reference voltage, that is to say, the potential of the second plate of the first capacitor C1 maintains the reference voltage at any stage.
  • the gate voltage of the driving transistor T3 can also be kept unchanged by the first capacitor C1, so as to avoid the formation between the gate and the source of the driving transistor T3.
  • the coupling capacitor Cgs affects the gate voltage of the driving transistor T3.
  • the first electrode plate of the first capacitor C1 is connected to the gate of the driving transistor T3, and the second electrode plate of the first capacitor C1 is connected to the drain of the driving transistor T3 as an example, but this It does not constitute a limitation on the protection scope of the embodiments of the present disclosure.
  • the pixel driving circuit of the embodiment of the present disclosure not only includes the above-mentioned data writing sub-circuit 4, threshold compensation sub-circuit 2, driving sub-circuit 3, storage sub-circuit 8, and first capacitor C1, It may also include at least one of the first reset sub-circuit 1 , the second reset sub-circuit 7 , the second reset sub-circuit 72 , the first lighting control sub-circuit 5 , and the second lighting control sub-circuit 6 .
  • the pixel driving circuit including the first reset subcircuit 1 , the second reset subcircuit 7 , the second reset subcircuit 72 , the first light emission control subcircuit 5 and the second light emission control subcircuit 6 will be described as an example.
  • the threshold compensation sub-circuit 2 for the data writing sub-circuit 4, the threshold compensation sub-circuit 2, the driving sub-circuit 3, the storage sub-circuit 8, the first reset sub-circuit 1, the second reset sub-circuit 7, the second reset sub-circuit 72, the first light-emitting control
  • Both the sub-circuit 5 and the second light-emitting control sub-circuit 6 can have the same structure as that shown in FIG. 2 , so the description is not repeated here.
  • the first plate of the first capacitor C1 is connected to the gate of the drive transistor T3 and the drain of the threshold compensation transistor T2, and the second plate of the first capacitor C1 is connected to the drain of the drive transistor T3 and the source of the threshold compensation transistor T2 .
  • the driving method of the pixel driving circuit includes the following stages:
  • Reset stage (t1) the reset control signal line Rst writes a low-level signal, and the scan line Ga(A) and the light-emitting control line EM write a high-level signal; the first reset transistor T1 and the second reset transistor T7 are turned on, driving The initial voltage Vinit written to the gate of the transistor T3 by the reset power signal line Init prepares for the writing of the writing data voltage Vdata in the next frame.
  • the anode of the light-emitting device D writes an initialization voltage (Vinit ⁇ VSS) through the second reset transistor T7, so that the light-emitting device D is no longer in the forward conduction state, and the internal electric field formed by the directional movement of the impurity ions in the light-emitting device D gradually disappears, thereby The characteristics of the light emitting device D are restored.
  • Data writing and threshold compensation stage (t2) the scanning line Ga (A) is written as a low-level signal, the reset control signal line Rst and the first light-emitting control line EM are written with a high-level signal; the data writing transistors T4 and Threshold compensation transistor T2 is turned on.
  • the driving transistor T3 is connected to a diode structure by the threshold compensation transistor T2.
  • the data voltage written on the data line Data is written into the gate of the driving transistor T3 through the data writing transistor T4 and the threshold compensation transistor T2 until the driving transistor T3 is turned off.
  • the gate voltage of the driving transistor T3 is Vdata+Vth (Vth ⁇ 0, Vth is the threshold voltage of the driving transistor T3 ), and is stored in the storage capacitor Cst.
  • the voltages of the first plate and the second plate of the storage capacitor Cst are Vdata+Vth and Vdd respectively; the voltages of the first plate and the second plate of the first capacitor C1 are Vdata+Vth.
  • Light-emitting stage (t3) the light-emitting control line EM writes a low-level signal
  • the scan line Ga(A) and the reset control signal line Rst write a high-level signal
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both When turned on, the source of the driving transistor T3 is connected to the first power supply voltage line VDD, and the source voltage of the driving transistor T3 instantaneously changes from Vdata in the previous stage to Vdd.
  • the drain voltage of the driving transistor T3 changes from Vdata+Vth in the previous stage to Vdd+Vds, where the value of Vdata depends on the grayscale value to be displayed by the light-emitting device D, and Vds is the difference between the source and the drain of the driving transistor T3.
  • the voltage value depends on the driving current corresponding to the gray scale value to be displayed by the light-emitting device D.
  • Vds is about -3V to -5V
  • Vth is about -0.7V to -1.3V
  • the maximum voltage difference between Vdd and Vdata does not exceed 5V
  • (Vdd+Vds)-(Vdata+Vth ) is about 1V
  • the gate voltage of the driving transistor T3 and the voltage Vdata+Vth of the previous stage only change by about 1V, which is approximately Vdata+Vth, that is, That is, even if there is a large coupling capacitance Cgs between the gate and the source of the driving transistor T3, when the source of the driving transistor T3 undergoes a large instantaneous change, due to the existence of the first capacitance C1, the There are also no large instantaneous changes in the gate voltage.
  • the light-emitting device D emits light under the driving of the driving transistor T3.
  • the light-emitting current of the light-emitting device D is equal to the current flowing through the driving transistor T3, and its expression is as follows:
  • the current of the light-emitting device D has nothing to do with the threshold voltage of the driving transistor T3 in the light-emitting stage, so as to avoid the influence of the threshold voltage of the driving transistor T3 on the display uniformity of the display panel.
  • Tables 1 and 2 are the simulation results of the inventors implementing the pixel driving circuit shown in FIG. 7 and the related art FIG. 2 according to the present disclosure. Among them, Vg represents the gate voltage of the driving transistor T3, and Id represents the driving current generated in the light-emitting stage of the driving transistor T3.
  • the gate voltage Vg of the driving transistor T3 in the pixel driving circuit diagrams shown in FIG. 7 and FIG. 2 is 0.409V in the light-emitting stage, and the driving current Id generated by the driving transistor is 75.5
  • the pixel driving circuit shown in FIG. 4 according to the embodiment of the present disclosure due to the addition of the first capacitor C1, can choose a relatively low-cost pixel driving circuit compared with the pixel driving circuit shown in FIG. 2 .
  • the driving transistor T3 of the pixel driving circuit shown in FIG. 4 The gate voltage Vg is -0.116V, and the driving current Id is 98.5; the gate voltage Vg of the driving transistor T3 of the pixel driving circuit shown in FIG. 2 is 0.409V, and the driving current Id is 75.5.
  • FIG. 9 is a schematic diagram of another pixel driving circuit according to an embodiment of the disclosure; as shown in FIG. 9 , the pixel circuit not only includes the above-mentioned data writing sub-circuit 4, threshold compensation sub-circuit 2, driving Subcircuit 3, storage subcircuit 8, first capacitor C1, first reset subcircuit 1 and first lighting control subcircuit 5; and also include a duration control subcircuit configured to respond to a timing control signal , and the light-emitting time of the light-emitting device D to be driven is controlled by the time modulation signal and the third light-emitting control signal.
  • the driving transistor T3 outputs a certain current
  • the driving circuit can write the time to the light-emitting device D through the time modulation signal and the third light-emitting control signal to realize the display of different gray scales.
  • the lighting duration control sub-circuit 10 may include a first time modulation transistor T8, a second time modulation transistor T9, a third lighting control transistor T10 and a second capacitor C2; wherein the first time modulation
  • the source of the transistor T8 is connected to the drain of the driving transistor T3, the drain of the first time modulation transistor T8 is connected to the source of the third light-emitting control transistor T10, and the gate of the first time-modulation transistor T8 is connected to the third light-emitting control line EM3;
  • the source of the second time modulation transistor T9 is connected to the time modulation signal terminal Data-T, the drain of the second time modulation transistor T9 is connected to the gate of the third light-emitting control transistor T10, and the gate of the second time modulation transistor T9 is connected to the time control Signal line Ga(B);
  • the drain of the third light-emitting control transistor T10 is connected to the anode of the light-emitting device D to be driven, and the
  • the duration of the third light-emitting control line EM3 being written to a low level within one frame of display time is controlled, for example, the duty ratio of the signal written to the third light-emitting control line EM3 is controlled, so as to control the first
  • the time modulation transistor T8 is turned on for a duration, thereby controlling the duration of the driving current output by the driving transistor T3 to the light-emitting device D.
  • the third light-emitting control line EM3 is configured to be written with a low-level signal multiple times in one frame of display time, and the duration of the written low-level signal is different each time.
  • the number of times that the third light-emitting control line EM3 is written to a low level within a frame of display time is N, where N is an integer greater than or 2
  • the third light-emitting control line EM3 is written in the 1st to Nth scan cycles
  • the time control signal line Ga(B) will be written with a low level signal for a certain period of time in each scanning period of the third light emission control line EM3.
  • K 2 p , 1 ⁇ p ⁇ N.
  • the light-emitting duration control sub-circuit 10 For the light-emitting duration of each pixel, the number h of the low-level signal (active level) input from the time modulation signal terminal Data-T and the 1st to Nth scan periods, the third light-emitting control line EM3 is written into The duration of the low-level time is determined. It can be seen that, in the embodiment of the present disclosure, since the light-emitting duration control sub-circuit 10 is added, it is possible to realize the control of 2 p kinds of light-emitting durations for each pixel.
  • the time when the time control signal line Ga(B) is written to the low level for the first time is the same as the time when the scan line Ga(A) is written to the working level in the data writing and threshold compensation stages
  • the data writing sub-circuit 4, the threshold compensation sub-circuit 2, the driving sub-circuit 3, the storage sub-circuit 8, the first reset sub-circuit 1 and the first light-emitting control sub-circuit 5 can all be The same structure as shown in FIG. 2 .
  • the data writing sub-circuit 4, the threshold compensation sub-circuit 2, the driving sub-circuit 3, the storage sub-circuit 8, the first reset sub-circuit 1 and the first light-emitting control sub-circuit are used in the pixel circuit.
  • the circuit 5 can be described by taking the same structure as that shown in FIG. 2 as an example.
  • control signals written by the first light-emitting control line EM1 and the third light-emitting control line EM3 may be the same, that is, the gate of the first time modulation transistor T8 and the gate of the first light-emitting control transistor T5 Connect the same luminous control line EM.
  • the control signals written in the first light-emitting control line EM1 and the third light-emitting control line EM3 may also be different. In the stage, the first light-emitting control transistor T5 is always on.
  • control signals written by the first light-emitting control line EM1 and the third light-emitting control line EM3 are the same, that is, the gate of the first time modulation transistor T8 is connected to the gate of the first light-emitting control transistor T5
  • a light emission control line EM is taken as an example for description.
  • Fig. 10 is the working timing diagram of the pixel driving circuit shown in Fig. 9; as shown in Figs. 7 and 8, wherein, with the light-emitting control line EM in one frame of display time, the time modulation signal terminal Data-T is at time 1 , time 2. For example, time N is written into a low-level signal in three scan cycles.
  • Reset stage (t1) the reset control signal line Rst writes a low-level signal, and the scan line Ga(A) and the light-emitting control line EM write a high-level signal; the first reset transistor T1 is turned on, and the gate of the drive transistor T3 is turned on.
  • the initial voltage Vinit written in the power signal line Init is reset to prepare for the writing of the data voltage Vdata in the next frame.
  • Data writing and threshold compensation stage (t2) the scanning line Ga (A) is written as a low level signal, the reset control signal line Rst and the light emission control line EM are written with a high level signal; the data writing transistor T4 and threshold compensation Transistor T2 is turned on.
  • the driving transistor T3 is connected to a diode structure by the threshold compensation transistor T2.
  • the data voltage written on the data line Data is written into the gate of the driving transistor T3 through the data writing transistor T4 and the threshold compensation transistor T2 until the driving transistor T3 is turned off.
  • the gate voltage of the driving transistor T3 is Vdata+Vth (Vth ⁇ 0, Vth is the threshold voltage of the driving transistor T3 ), and is stored in the storage capacitor Cst.
  • the voltages of the first plate and the second plate of the storage capacitor Cst are Vdata+Vth and Vdd respectively; the voltages of the first plate and the second plate of the first capacitor C1 are both Vdata+Vth.
  • the time time 1 T of the level signal, the scan line Ga(A) and the reset control signal line Rst write a high level signal, the first light-emitting control transistor T5, the first time modulation transistor T8, the second time modulation transistor T9, the first light-emitting control transistor T5, the first time modulation transistor T8, the second time modulation transistor T9,
  • the three light-emitting control transistors T10 are all turned on, and the light-emitting duration of the light-emitting device D in the first scanning period is T; in the second scanning period, the time control signal line Ga(B) is written to a low level, and the time modulation The signal terminal Data-T inputs a low-level signal, the light-emitting control line
  • Time N T/ 2 (n-1) , the scan line Ga(A) and the reset control signal line Rst write a high level signal, the first light emission control transistor T5, the first time modulation transistor T8, the second time modulation transistor T9, the third light emission
  • the control transistors T10 are all turned on, and the light-emitting duration of the light-emitting device D in the Nth scan period is T/2 (n-1) ; the time modulation signal terminal Data-T of the scan period from the 3rd row to the n-1th row is When a high-level signal is written, the third light-emitting control transistor T10 is turned off, and the light-emitting device D does not emit light, that is, the total light-emitting duration of the light-emitting device D is T+T/2+T/2 (n- 1) .
  • the source of the driving transistor T3 is connected to the first power supply voltage line VDD, and the source voltage of the driving transistor T3 instantaneously changes from Vdata in the previous stage to Vdd.
  • the drain voltage of the driving transistor T3 changes from Vdata+Vth in the previous stage to Vdd+Vds, where the value of Vdata depends on the grayscale value to be displayed by the light-emitting device D, and Vds is the difference between the source and the drain of the driving transistor T3.
  • the voltage value depends on the driving current corresponding to the gray scale value to be displayed by the light-emitting device D.
  • Vds is about -3V to -5V
  • Vth is about -0.7V to -1.3V
  • the maximum voltage difference between Vdd and Vdata does not exceed 5V
  • (Vdd+Vds)-(Vdata+Vth ) is about 1V
  • (Vdd+Vds)-(Vdata+Vth) is about 1V
  • the gate voltage of the driving transistor T3 is the same as the voltage Vdata+ of the previous stage Vth only changes by about 1V, which is approximately Vdata+Vth.
  • the light-emitting device D emits light under the driving of the driving transistor T3.
  • the light-emitting current of the light-emitting device D is equal to the current flowing through the driving transistor T3, and its expression is as follows:
  • the current of the light-emitting device D has nothing to do with the threshold voltage of the driving transistor T3 in the light-emitting stage, so as to avoid the influence of the threshold voltage of the driving transistor T3 on the display uniformity of the display panel.
  • the effective light-emitting brightness of the light-emitting device D in the pixel driving circuit in an image frame can be determined by the number of scanning periods in an image frame, the duration of each scanning period, the first data voltage Vdata_A , the second data voltage Vdata_B, and the light-emitting control signal provided by the light-emitting control signal line EM are determined by multiple factors, so that the sub-pixels with the pixel driving circuit can display more grayscale values, and the screen displayed by the display panel is more abundant and delicate. .
  • an embodiment of the present invention further provides a display panel, which includes any one of the above-mentioned pixel driving circuits. Therefore, the display panel of this embodiment has a better display effect and can realize high-resolution display.
  • the display panel may be a liquid crystal display device or an electroluminescent display device, such as liquid crystal panel, OLED panel, Micro LED panel, Mini LED panel, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, etc. Any product or part that has a display function.
  • liquid crystal panel OLED panel
  • Micro LED panel Mini LED panel
  • mobile phone tablet computer
  • TV monitor
  • notebook computer digital photo frame, navigator, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

本公开提供一种像素驱动电路及显示面板，属于显示技术领域。本公开的像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路、存储子电路及电压维持子电路；其中，所述数据写入子电路，被配置为响应于第一扫描信号，将数据电压信号传输至驱动子电路的第一端；所述阈值补偿子电路，被配置为响应于第二扫描信号，对所述驱动子电路的阈值电压进行补偿；所述存储子电路，被配置为对所述数据电压信号进行存储；所述驱动子电路，被配置为根据其第一端和控制端的电压为待驱动的发光器件提供驱动电流；所述电压维持子电路，被配置为在所述驱动子电路的第一端电压发生跳变时，维持所述驱动子电路的控制端电压。

Description

像素驱动电路及显示面板 技术领域
本发明属于显示技术领域，具体涉及一种像素驱动电路及显示面板。
背景技术
目前，微型发光二极管(Micro Light Emitting Diode，Micro LED)显示技术正在日新月异地发展，由于其突出的优点：体积微型、低耗电、高色彩饱和度、反应速度快、寿命长等吸引了广大科技工作者的投入研究。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种像素驱动电路及显示面板。
第一方面，本公开实施例提供一种像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路、存储子电路及电压维持子电路；其中，
所述数据写入子电路，被配置为响应于第一扫描信号，将数据电压信号传输至驱动子电路的第一端；
所述阈值补偿子电路，被配置为响应于第二扫描信号，对所述驱动子电路的阈值电压进行补偿；
所述存储子电路，被配置为对所述数据电压信号进行存储；
所述驱动子电路，被配置为根据其第一端和控制端的电压为待驱动的发光器件提供驱动电流；
所述电压维持子电路，被配置为在所述驱动子电路的第一端电压发生跳变时，维持所述驱动子电路的控制端电压。
其中，所述电压维持子电路包括第一电容，所述第一电容的第一极板连接所述驱动子电路的控制端，所述第一电容的第二极板连接所述驱动子电路的第二端。
其中，所述电压维持子电路包括第一电容，所述第一电容的第一极板连接所述驱动子电路的控制端，所述第一电容的第二极板连接参考电压端。
其中，所述第一电容的容值为0.1pF-10pF。
其中，所述像素驱动电路还包括：
第一发光控制子电路，被配置为响应于第一发光控制信号，控制第一电压是否能够被写入所述驱动子电路的第一驱动子电路的第一端。
其中，所述第一发光控制子电路包括第一发光控制晶体管；
所述第一发光控制晶体管的第一极连接第一电源电压线，所述第一发光控制晶体管的第二极连接所述驱动子电路的第一端，所述第一发光控制晶体管的控制极连接第一发光控制线。
其中，所述的像素驱动电路还包括：
第一复位子电路，被配置为响应于第一复位控制信号，并通过第一初始化信号对驱动子电路的控制端的电压进行复位。
其中，第一复位子电路包括第一复位晶体管；
所述第一复位晶体管的第一极连接第一初始化信号端，所述第一复位晶体管的第二极连接所述驱动子电路的控制端，所述第一复位晶体管的控制极连接所述第一复位控制信号线。
其中，所述像素驱动电路还包括：
第二发光控制子电路，被配置为响应于第二发光控制信号，导通或断开所述驱动子电路和所述待驱动的发光器件之间的连接。
其中，所述第二发光控制子电路包括第二发光控制晶体管；
所述第二发光控制晶体管的第一极连接所述驱动子电路的第二端，所述第二发光控制晶体管的第二极连接所述待驱动的发光器件的第一电极，所述第二发光控制晶体管的控制极连接第二发光控制线。
其中，所述像素驱动电路还包括：
第二复位子电路，被配置为响应于第二复位控制信号，通过第二初始化信号对所述待驱动的发光器件进行初始化。
其中，所述第二复位子电路包括第二复位晶体管；
所述第二复位晶体管的第一极连接所述待驱动的所述发光器件的第一电极，所述第二复位晶体管的第二极连接第二初始化信号端，所述第二复位晶体管的控制极连接第二复位控制信号线。
其中，所述像素驱动电路还包括：时间控制子电路，被配置为响应于时间控制信号，并通过时间调制信号和第三发光控制信号控制所述待驱动的发光器件的发光时间。
其中，所述时间控制子电路包括第一时间调制晶体管、第二时间调制晶体管、第三发光控制晶体管及第二电容；
所述第一时间调制晶体管的第一极连接所述驱动子电路的第二端，所述第一时间调制晶体管的第二极连接所述第三发光控制晶体管的第一极，所述第一时间调制晶体管的控制极连接第三发光控制线；
所述第二时间调制晶体管的第一极连接时间调制信号端，所述第二时间调制晶体管的第二极连接所述第三发光控制晶体管的控制极，所述第二时间调制晶体管的控制极连接时间控制信号线；
所述第三发光控制晶体管的第二极连接待驱动的发光器件的第一电极，所述第三发光控制晶体管的控制极连接所述第二电容的第一极板；
所述第二电容的第二极板连接公共电压端。
其中，所述第三发光控制线被配置为在一帧显示时间内分多次写入工作电平信号，且每次所写入的工作电平时长不等。
其中，所述驱动子电路包括驱动晶体管，所述阈值补偿子电路包括阈值补偿晶体管，所述数据写入子电路包括数据写入晶体管，存储子电路包括存储电容；
所述驱动晶体管的第一极用作所述驱动子电路的第一端，所述驱动晶体 管的第二极用作所述驱动子电路的第二端，所述驱动子电路的控制极用作所述驱动子电路的控制端；
所述驱动晶体管的第一极连接所述数据写入晶体管的第二极，所述驱动晶体管的第二极连接所述阈值补偿晶体管的第一极，所述驱动晶体管的控制极连接所述阈值补偿晶体管的第二极和所述存储电容的第一极板；
所述数据写入晶体管的第一极连接数据线，所述数据写入晶体管的控制极连接第一扫描线；
所述阈值补偿晶体管的控制极连接第二扫描线；
所述存储电容的第二极板连接第一电源电压线。
其中，所述存储电容的容值为0.1pF-10pF。
本公开实施例还提供一种像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路、存储子电路、第一发光控制子电路、第二发光控制子电路、第一复位子电路、第二复位子电路及电压维持子电路；其中，
所述驱动子电路包括驱动晶体管，所述阈值补偿子电路包括阈值补偿晶体管，所述数据写入子电路包括数据写入晶体管，存储子电路包括存储电容，所述第一发光控制子电路包括第一发光控制晶体管，所述第二发光控制子电路包括第二发光控制晶体管，所述第一复位子电路包括第一复位晶体管，所述第二复位子电路包括第二复位晶体管，所述电压维持子电路包括第一电容；
所述驱动晶体管的第一极连接所述数据写入晶体管的第二极和所述第一发光控制晶体管的第二极，所述驱动晶体管的第二极连接所述阈值补偿晶体管的第一极，所述驱动晶体管的控制极连接所述阈值补偿晶体管的第二极、所述存储电容的第一极板和所述第一电容的第一极板；
所述数据写入晶体管的第一极连接数据线，所述数据写入晶体管的控制极连接第一扫描线；
所述阈值补偿晶体管的控制极连接第二扫描线；
所述存储电容的第二极板连接第一电源电压线；
所述第一发光控制晶体管的第一极连接第一电源电压线，所述第一发光控制晶体管的控制极连接第一发光控制线；
所述第二发光控制晶体管的第一极连接所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接所述待驱动的发光器件的第一电极，所述第二发光控制晶体管的控制极连接第二发光控制线；
所述第一复位晶体管的第一极连接第一初始化信号端，所述第一复位晶体管的第二极连接所述驱动晶体管的控制极，所述第一复位晶体管的控制极连接所述第一复位控制信号线；
所述第二复位晶体管的第一极连接所述待驱动的所述发光器件的第一电极，所述第二复位晶体管的第二极连接第二初始化信号端，所述第二复位晶体管的控制极连接第二复位控制信号线；
所述第一电容的第二极板连接所述驱动晶体管的第二电极或者参考电压端。
本公开实施例还一种像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路、存储子电路、第一发光控制子电路、第一复位子电路、时间控制子电路及电压维持子电路；其中，
所述驱动子电路包括驱动晶体管，所述阈值补偿子电路包括阈值补偿晶体管，所述数据写入子电路包括数据写入晶体管，存储子电路包括存储电容，所述第一发光控制子电路包括第一发光控制晶体管，所述第二发光控制子电路包括第二发光控制晶体管，所述第一复位子电路包括第一复位晶体管，所述第二复位子电路包括第二复位晶体管，所述时间控制子电路包括第一时间调制晶体管、第二时间调制晶体管、第三发光控制晶体管及第二电容，所述电压维持子电路包括第一电容；
所述驱动晶体管的第一极连接所述数据写入晶体管的第二极和所述第一发光控制晶体管的第二极，所述驱动晶体管的第二极连接所述阈值补偿晶 体管的第一极，所述驱动晶体管的控制极连接所述阈值补偿晶体管的第二极、所述存储电容的第一极板和所述第一电容的第一极板；
所述数据写入晶体管的第一极连接数据线，所述数据写入晶体管的控制极连接第一扫描线；
所述阈值补偿晶体管的控制极连接第二扫描线；
所述存储电容的第二极板连接第一电源电压线；
所述第一发光控制晶体管的第一极连接第一电源电压线，所述第一发光控制晶体管的控制极连接第一发光控制线；
所述第一复位晶体管的第一极连接第一初始化信号端，所述第一复位晶体管的第二极连接所述驱动晶体管的控制极，所述第一复位晶体管的控制极连接所述第一复位控制信号线；
所述第一时间调制晶体管的第一极连接所述驱动晶体管的第二极，所述第一时间调制晶体管的第二极连接所述第三发光控制晶体管的第一极，所述第一时间调制晶体管的控制极连接第三发光控制线；
所述第二时间调制晶体管的第一极连接时间调制信号端，所述第二时间调制晶体管的第二极连接所述第三发光控制晶体管的控制极，所述第二时间调制晶体管的控制极连接时间控制信号线；
所述第三发光控制晶体管的第二极连接待驱动的发光器件的第一电极，所述第三发光控制晶体管的控制极连接所述第二电容的第一极板；
所述第二电容的第二极板连接公共电压端。
第二方面，本公开实施例一种显示面板，其包括多个像素单元，所述多个像素单元中的每个包括像素驱动电路和发光器件；其中，所述像素驱动电路为上述的任一像素驱动电路。
其中，所述发光器件包括：微型无机发光二极管。
附图说明
图1为一种示例性的显示基板结构示意图。
图2为一种示例性的像素驱动电路示意图。
图3为图2所示的像素驱动电路的工作时序图。
图4为图2所示的像素驱动电路中驱动晶体管和存储电容的截面图。
图5为图2所示的像素驱动电路的各工作阶段驱动晶体管的源极电压Vs和栅极电压Vg变化仿真图。
图6为图2的像素驱动电路产生的驱动电流和时间对应关系图。
图7为本公开实施例的一种像素驱动电路的示意图。
图8为本公开实施例的另一像素驱动电路的示意图。
图9为本公开实施例的另一种像素驱动电路的示意图。
图10为图9所示的像素驱动电路的工作时序图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种示例性的显示基板结构示意图；图2为一种示例性的像素驱动电路示意图；如图1和2所示，该显示基板包括呈阵列排布的多个像素单元，每个像素单元100中均包括像素驱动电路和发光器件D。各像素单元100中的像素驱动电路可以包括：第一复位子电路1、阈值补偿子电路2、驱动子电路3、数据写入子电路4、第一发光控制子电路5、第二发光控制子电路6、第二复位子电路7及存储子电路8。
其中，第一复位子电路1与驱动子电路3的控制端连接，且被配置为在第一复位信号的控制下对驱动子电路3的控制端进行复位。阈值补偿子电路2分别与驱动子电路3的控制端和第二端电连接，且被配置为对驱动子电路3进行阈值补偿。数据写入子电路4与驱动子电路3的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储子电路。存储子电路8分别与驱动子电路3的控制端和第一电源电压线VDD电连接，且被配置为存储数据信号。第一发光控制子电路5分别与第一电源电压线VDD以及驱动子电路3的第一端相连，且被配置为实现驱动子电路3和第一电源电压线VDD间的连接导通或断开，第二发光控制子电路6分别与驱动子电路3的第二端和发光器件D的第一电极电连接，且被配置为实现驱动子电路3和发光器件D之间的连接导通或断开。第二复位子电路7与发光器件D的第一电极电连接，且被配置为在第二复位控制信号的控制下对驱动子电路3的控制端和发光器件D的第一电极进行复位。
继续参照图2，第一复位子电路包括第一复位晶体管T1，阈值补偿子电路2包括阈值补偿晶体管T2，驱动子电路3包括驱动晶体管T3，驱动子电路3的控制端包括驱动晶体管T3的控制极，驱动子电路3的第一端包括驱动晶体管T3的第一极，驱动子电路3的第二端包括驱动晶体管T3的第二极。数据写入子电路4包括数据写入晶体管T4，存储子电路7包括存储电容Cst，第一发光控制子电路5包括第一发光控制晶体管T5，第二发光控制子电路6包括第二发光控制晶体管T6，第二复位子电路7包括第二复位晶体管T7。
在此需要说明的是，按照晶体管的特性，晶体管可以分为N型晶体管和 P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，驱动晶体管T3、数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1和第二复位晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
另外，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。对于每个晶体管其均包括第一极、第二极和控制极；其中，控制极作为晶体管的栅极，第一极和第二极中的一者作为晶体管的源极，另一者作为晶体管的漏极；而晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中第一极为源极，第二极为漏极，所以本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
继续参照图2，数据写入晶体管T4漏极的与驱动晶体管T3的源极电连接，数据写入晶体管T4的源极被配置为与数据线Data电连接以接收数据信号，数据写入晶体管T4的栅极被配置为与第一扫描信号线Ga1电连接以接收扫描信号；存储电容Cst的第二极板与第一电源电压线VDD电连接，存储电容Cst的第一极板与驱动晶体管T3的栅极电连接；阈值补偿晶体管T2的源极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的漏极与驱动晶体管T3的漏极电连接，阈值补偿晶体管T2的栅极被配置为与第二扫描信号线Ga2电连接以接收补偿控制信号；第一复位晶体管T1的源极被配置为与第一复位电源端Vinit1电连接以接收第一复位信号，第一复位晶体管T1的漏极与驱动晶体管T3的栅极电连接，第一复位晶体管T1的栅极被配置为与第一复位控制信号线Rst1电连接以接收第一复位控制信号；第二复位晶体管 T7的漏极被配置为与第一复位电源端Vinit1电连接以接收第一复位信号，第二复位晶体管T7的源极与发光器件D的第一电极电连接，第二复位晶体管T7的栅极被配置为与第二复位控制信号线Rst2电连接以接收第二复位控制信号；第一发光控制晶体管T5的源极与第一电源电压线VDD电连接，第一发光控制晶体管T5的漏极与驱动晶体管T3的源极电连接，第一发光控制晶体管T5的栅极被配置为与第一发光控制信号线EM1电连接以接收第一发光控制信号；第二发光控制晶体管T6的源极与驱动晶体管T3的漏极电连接，第二发光控制晶体管T6的漏极与发光器件D的第一电极D1电连接，第二发光控制晶体管T6的栅极被配置为与第二发光控制信号线EM2电连接以接收第二发光控制信号；发光器件D的第二电极与第二电源端VSS电连接。
例如，第一电源电压线VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图8所示的实施例中，第一电源电压线VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
继续参照图2，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T4的栅极和阈值补偿晶体管T2的栅极可以电连接到同一条信号线，例如第一扫描信号线Ga1，以接收相同的信号(例如，扫描信号)，此时，显示基板可以不设置第二扫描信号线Ga2，减少信号线的数量。又例如，数据写入晶体管T4的栅极和阈值补偿晶体管T2的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T4的栅极电连接到第一扫描信号线Ga1，阈值补偿晶体管T2的栅极电连接到第二扫描信号线Ga2，而第一扫描信号线Ga1和第二扫描信号线Ga2传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得数据写入晶体管T4的栅极和阈值补偿晶体管T2可以被分开单独控制，增加控制像素电路的灵活性。在本公开实施例中以数据写入晶体管T4的栅极和阈值补偿晶体管T2的栅极电连接第一扫描信号线Ga(A)为例进行说明。
继续参照图2，第一发光控制信号和第二发光控制信号可以相同，即，第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极可以电连接到同一条信号线，例如第一发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板可以不设置第二发光控制信号线EM2，减少信号线的数量。又例如，第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极也可以分别电连接至不同的信号线，即，第一发光控制晶体管T5的栅极电连接到第一发光控制信号线EM1，第二发光控制晶体管T6的栅极电连接到第二发光控制信号线EM2，而第一发光控制信号线EM1和第二发光控制信号线EM2传输的信号相同。
需要说明的是，当第一发光控制晶体管T5和第二发光控制晶体管T6为不同类型的晶体管，例如，第一发光控制晶体管T5为P型晶体管，而第二发光控制晶体管T6为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本公开的实施例对此不作限制。在本公开实施例中以第一发光控制晶体管T5和第二发光控制晶体管T6的栅极均连接发光控制线EM为例进行说明。
例如，第一复位控制信号和第二复位控制信号可以相同，即，第一复位晶体管T1的栅极和第二复位晶体管T7的栅极可以电连接到同一条信号线，例如第一复位控制信号线Rst1，以接收相同的信号(例如，第一子复位控制信号)，此时，显示基板可以不设置第二复位控制信号线Rst2，减少信号线的数量。又例如，第一复位晶体管T1的栅极和第二复位晶体管T7的栅极也可以分别电连接至不同的信号线，即第一复位晶体管T1的栅极电连接到第一复位控制信号线Rst1，第二复位晶体管T7的栅极电连接到第二复位控制信号线Rst2，而第一复位控制信号线Rst1和第二复位控制信号线Rst2传输的信号相同。需要说明的是，第一复位控制信号和第二复位控制信号也可以不相同。在本公开实施例中以第一复位晶体管T1的栅极和第二复位晶体管T7的栅极均电连接到复位控制信号线Rst为例。
例如，在一些示例中，第二复位控制信号可以与扫描信号相同，即第二 复位晶体管T7的栅极可以电连接到扫描信号线Ga(A)以接收扫描信号作为第二子复位控制信号。
例如，第一复位晶体管T1的源极和第二复位晶体管T7的漏极分别连接到第一复位电源端Vinit1和第二复位电源端Vinit2，第一复位电源端Vinit1和第二复位电源端Vinit2可以为直流参考电压端，以输出恒定的直流参考电压。第一复位电源端Vinit1和第二复位电源端Vinit2可以相同，例如第一复位晶体管T1的源极和第二复位晶体管T7的漏极连接到同一复位电源端。第一复位电源端Vinit1和第二复位电源端Vinit2可以为高压端，也可以为低压端，只要其能够提供第一复位信号和第一复位信号以对驱动晶体管T3的栅极和发光元件的第一电极D1进行复位即可，本公开对此不作限制。例如，第一复位晶体管T1的源极和第二复位晶体管T7的漏极可以均连接至复位电源信号线Init。
需要说明的是，在本公开实施例中，以第一复位晶体管T1的栅极和第二复位晶体管的T7的栅极均电连接Rst1；第一复位晶体管T1的源极和第二复位晶体管的T7的漏极均电连接复位电源信号线Init为例进行说明。另外，图2所示的像素电路中的驱动子电路、数据写入子电路、存储子电路、阈值补偿子电路和复位子电路仅为示意性的，驱动子电路、数据写入子电路、存储子电路、阈值补偿子电路和复位子电路等子电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
需要说明的是，在本公开实施例中，子像素的像素电路除了可以为图2所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管和电容的电路结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
发光器件D可以是微型无机发光二极管，进一步地，可以为电流型发光二极管，如微型发光二极管(Micro Light Emitting Diode，Micro LED)或者迷你发光二极管(Mini Light Emitting Diode，Mini LED)，当然，在发明实施例中的发光器件D还可以是有机电致发光二极管(Organic Light Emitting  Diode，OLED)。发光器件D的第一电极和第二电极中的一者为阳极，另一者为阴极；在本发明实施例中以发光器件D的第一电极为阳极，第二电极为阴极为例进行说明。
图3为图2所示的像素驱动电路的工作时序图；如图2和3所示，上述的像素驱动电路的驱动方法可以包括如下阶段：
复位阶段(t1)：复位控制信号线Rst写入低电平信号，扫描线Ga(A)和发光控制线EM写入高电平信号；第一复位晶体管T1和第二复位晶体管T7打开，驱动晶体管T3栅极的被复位电源信号线Init写入的初始电压Vinit，为下一帧写入数据电压Vdata的写入做准备。发光器件D的阳极通过第二复位晶体管T7写入初始化电压(Vinit≤VSS)，使发光器件D不再处于正向导通状态，使发光器件D内杂质离子定向移动形成的内部电场逐渐消失，从而恢复发光器件D的特性。
数据写入及阈值补偿阶段(t2)：扫描线Ga(A)写入为低电平信号，复位控制信号线Rst和第一发光控制线EM写入高电平信号；数据写入晶体管T4和阈值补偿晶体管T2打开。驱动晶体管T3被阈值补偿晶体管T2连成二极管结构，数据线Data上写入的数据电压Vdata通过数据写入晶体管T4和阈值补偿晶体管T2写入驱动晶体管T3的栅极，直到驱动晶体管T3截止。驱动晶体管T3的栅极电压为Vdata+Vth(Vth<0，Vth为驱动晶体管T3的阈值电压)，并存储在存储电容Cst中。存储电容Cst的第一极板和第二极板的电压分别为Vdata+Vth和Vd。
发光阶段(t3)：发光控制线EM写入低电平信号，扫描线Ga(A)与复位控制信号线Rst写入高电平信号，第一发光控制晶体管T5和第二发光控制晶体管T6均打开，驱动晶体管T3的源极与第一电源电压线VDD连接，驱动晶体管T3的源极电压由上一阶段的Vdata瞬时变化为Vdd。发光器件D在驱动晶体管T3的驱动下发光，此时驱动晶体管T3工作在饱和区，驱动晶体管T3的栅极电压为Vdata+Vth，驱动晶体管T3的源极电压为Vdd，故，驱动晶体管T3的栅源电压为：Vgs＝(Vdata+Vth)-Vdd，直到下一帧的复位 阶段。
发光器件D的发光电流等于流过驱动晶体管T3的电流，其表达式如下：
I D＝β(Vgs-Vth) 2
＝β(Vdata+Vth-dd-Vth) 2
Figure PCTCN2020118279-appb-000001
图4为图2所示的像素驱动电路中的驱动晶体管和存储电容的截面图；如图4所示，驱动晶体管T3采用顶栅型薄膜晶体管，在基底101上形成有缓冲层102，驱动晶体管的有源层201形成在缓冲层102背离基底101的一侧，在驱动晶体管的有源层201背离基底101的一侧形成第一栅极绝缘层103，驱动晶体管的栅极202和存储电容Cst的第一极板301形成在缓冲层102背离基底101的一侧，在驱动晶体管的栅极202背离基底101的一侧形成第二栅极绝缘层104；在第二栅极绝缘层104背离基底101的一侧形成存储电容Cst的第二极板302；在存储电容Cst的第二极板302背离基底的一侧形成层间绝缘层105，驱动晶体管T3的源极203和漏极204形成在层间绝缘层105背离基底101的一侧。发明人发现，当采用微型无机发光二极管作为发光器件时，像素驱动电路的驱动电流需要μA级或者mA级，此时像素驱动电路中的驱动晶体管T3预生成较为稳定的输出电流，则需要沟道宽度和长度的尺寸较大的驱动晶体管T3，而随着沟道宽度和长度的尺寸增大，驱动晶体管T3的栅极202和源极203所形成的耦合电容Cgs及栅极202和漏极204所形成耦合电容Cgd均会增大。图5为图2所示的像素驱动电路的各工作阶段驱动驱动晶体管的源极电压Vs和栅极电压Vg变化仿真图。如图5所示，当Cgs增大后，一旦驱动晶体管T3的源极的电压Vs发生较大的变化(例如：从数据写入及阈值补偿阶段t2的Vdata到发光阶段t3的Vdd)，由于Cgs的电压保持作用，驱动晶体管T3的栅极电压Vg将会随着源极的电压Vs发生变化，导致驱动晶体管T3的栅源电压Vgs降低，进而导致驱动晶体 管T3产生的输出电流降低，发光器件的发光亮度随之降低。为避免上述问题发生，一种解决方案是增大存储电容Cst，但是存储电容Cst增加后，由于存储电容Cst的第二极板302与第一电源电压线VDD连接，数据线Data和第一电源电压线VDD相邻且并排设置，二者之间存在一定的耦合电容，这样一来，在数据线Data上电压跳变时，数据线Data上电压跳变时，第一电源电压线VDD因电容耦合电压跳变，而由于存储电容Cst较大，在存储电容Cst的自举作用下，驱动晶体管T3的栅极电压将会发生跳变，进而导致电流Id变化(如图6中t11时刻Id跳变ΔId)，故存储电容Cst增加需同时考虑第一电源电压线VDD的跳变影响，即Cst增加存在上限。
针对上述技术问题，在本公开实施例中提供以下技术方案。
第一方面，图7为本公开实施例的一种像素驱动电路的示意图；如图4所示，本公开实施例提供一种像素驱动电路，其可以包括上述的数据写入子电路4、阈值补偿子电路2、驱动子电路3、存储子电路8，特别的是，该像素驱动电路还包括电压维持子电路9。该电压维持子电路9与驱动子电路3的第一端电连接，且被配置为在驱动子电路3的第一端电压发生跳变时，维持驱动子电路3的控制端电压。
在一些实施例中，驱动子电路3可以包括驱动晶体管T3，驱动晶体管T3的源极用作驱动子电路3的第一端，驱动晶体管T3的漏极用作驱动子电路3的第二端，驱动晶体管T3的栅极用作驱动子电路3的控制端。本公开实施例中的电压维持子电路9被配置为维持驱动子电路3的控制端电压，也即维持驱动晶体管T3的栅极的电压。在本公开实施例中以驱动子电路3包括驱动晶体管T3为例进行描述。
具体的，当在数据写入和阈值补偿阶段，数据写入子电路4和阈值补偿子电路2均在扫描信号的控制下工作，此时驱动晶体管T3的栅极和漏极被阈值补偿子电路2连接，驱动晶体管T3的源极被写入数据电压信号Vdata，在该阶段驱动晶体管T3的栅极的电压为Vdata+Vth(Vth＜0，Vth为驱动晶体管T3的阈值电压)。在发光阶段阶段，驱动晶体管T3的源极的电压变为 第一电压Vdd，也就是说，从数据写入和阈值补偿阶段到发光阶段驱动晶体管T3的源极电压由Vdata跳变至Vdd，发生较大的瞬时变化，在本公开实施例中通过设置电压维持子电路9，使得驱动电极管的栅极不会在其源极的电压发生较大瞬时变化时，发生较大变化，从而使得发光阶段驱动晶体管T3可以输出的电流稳定，以保证待驱动的发光器件D正常发光。
在一些实施例中，电压维持子电路9包括第一电容C1，该第一电容C1的第一极板与驱动晶体管T3的栅极连接，且被配置为在驱动晶体管T3的源极电压发生跳变时，维持驱动晶体管T3的栅极电压。在本公开实施例中，通过第一电容C1维持驱动晶体管T3的栅极电压稳定，可以保证在显示阶段的发光器件D可以正常发光，而且较相关技术通过增大存储电容Cst来维持驱动晶体管T3的栅极稳定而言，通过增加第一电容C1，可以降低存储电容Cst的大小(减小存储电容Cst的两个极片的面积)，因此可以减小像素驱动电路的面积，从而提高应用该像素驱动电路的显示面板的分辨率，与此同时，也可以避免存储电容Cst增加后，第一电源电压线VDD的电容增加，数据线Data跳变时VDD因电容耦合跳变导致电流变化的问题。
在一个示例中，继续参照图7，第一电容C1的第一极板连接驱动晶体管T3的栅极，第一电容C1的第二极板连接驱动晶体管T3的漏极。之所以如此连接是因为，在数据写入和阈值补偿阶段，驱动晶体管T3的漏极电压为Vdata+Vth，在发光阶段，驱动晶体管T3的漏极电压为Vdd+Vds，Vds表示发光阶段驱动晶体管T3导通后其源极和漏极之间的跨压，其中，Vdata的值取决于发光器件D待显示的灰阶值，Vds电压值取决于发光器件D待显示的灰阶值所对应的驱动电流。在一些实施例中Vds大约在-3V到-5V左右，Vth大约在-0.7V到-1.3V左右，而Vdd与Vdata的最大电压差不超过5V。因此，(Vdd+Vds)-(Vdata+Vth)大约在1V左右，故在在第一电容C1的自举作用下，驱动晶体管T3的漏极电压由数据写入和阈值补偿阶段到发光阶段变化相对很小，因此在第一电容C1的作用下，驱动晶体管T3的栅极也不会发生较大幅度的变化，故可以有效的维持驱动晶体管T3的栅极电压，以保证 在发光阶段驱动晶体管T3的稳定性，从而使得发光器件D可以正常发光。
需要说明的是，在本公开实施例中是以第一电容C1的第一极板连接驱动晶体管T3的栅极，第一电容C1的第二极板连接驱动晶体管T3的漏极，此时可以在形成驱动晶体管T3的栅极的同时形成第一电容C1的第一极板，在形成驱动晶体管T3的漏极的同时形成第一电容C1的第二极板。这样一来，不会增加应该像素驱动电路的显示面板的厚度，也会增加工艺步骤。当然，也可以通过两层单独的金属分别形成第一极板和第二基板。
在另一个示例中，图8为本公开实施例的另一像素驱动电路的示意图；如图8所示，与图7所示的像素驱动电路，第一电容C1的第一极板连接驱动晶体管T3的栅极，第一电容C1的第二极板连接参考电压端Vref。例如：参考电压端Vref被持续写入一固定的参考电压，也就是说，在任何阶段第一电容C1的第二极板的电位均保持参考电压，因此，即使在数据写入及阈值补偿阶段到发光阶段驱动晶体管T3的栅极电压发生较大瞬时变化，也可以通过第一电容C1来维持驱动晶体管T3的栅极电压保持不变，以避免驱动晶体管T3的栅极和源极之间形成耦合电容Cgs而影响驱动晶体管T3的栅极电压。
需要说明的是，在下述描述中以第一电容C1的第一极板连接驱动晶体管T3的栅极，第一电容C1的第二极板连接驱动晶体管T3的漏极为例进行说明的，但这并不构成对本公开实施例的保护范围的限制。
例如：继续参照图7，在本公开实施例的像素驱动电路中，不仅包括上述的数据写入子电路4、阈值补偿子电路2、驱动子电路3、存储子电路8、第一电容C1，还可以包括第一复位子电路1、第二复位子电路7第二复位子电路72、第一发光控制子电路5、第二发光控制子电路6中的至少一者。以下以像素驱动电路包括第一复位子电路1、第二复位子电路7第二复位子电路72、第一发光控制子电路5及第二发光控制子电路6为例进行说明。其中，对于数据写入子电路4、阈值补偿子电路2、驱动子电路3、存储子电路8、第一复位子电路1、第二复位子电路7第二复位子电路72、第一发光控制子 电路5及第二发光控制子电路6均可以与图2中所示的结构相同，故在此不在重复描述。对于第一电容C1的第一极板连接驱动晶体管T3的栅极和阈值补偿晶体管T2的漏极，第一电容C1的第二极板则连接驱动晶体管T3的漏极和阈值补偿晶体管T2源极。以下对本公开实施例的像素驱动电路的驱动方法进行说明，以便清楚了解本公开实施例的像素驱动电路的各部分功能。
同样参照图3所示的工作时序图；如图3和7所示，本公开实施例的像素驱动电路的驱动方法包括如下阶段：
复位阶段(t1)：复位控制信号线Rst写入低电平信号，扫描线Ga(A)和发光控制线EM写入高电平信号；第一复位晶体管T1和第二复位晶体管T7打开，驱动晶体管T3栅极的被复位电源信号线Init写入的初始电压Vinit，为下一帧写入数据电压Vdata的写入做准备。发光器件D的阳极通过第二复位晶体管T7写入初始化电压(Vinit≤VSS)，使发光器件D不再处于正向导通状态，使发光器件D内杂质离子定向移动形成的内部电场逐渐消失，从而恢复发光器件D的特性。
数据写入及阈值补偿阶段(t2)：扫描线Ga(A)写入为低电平信号，复位控制信号线Rst和第一发光控制线EM写入高电平信号；数据写入晶体管T4和阈值补偿晶体管T2打开。驱动晶体管T3被阈值补偿晶体管T2连成二极管结构，数据线Data上写入的数据电压通过数据写入晶体管T4和阈值补偿晶体管T2写入驱动晶体管T3的栅极，直到驱动晶体管T3截止。驱动晶体管T3的栅极电压为Vdata+Vth(Vth<0，Vth为驱动晶体管T3的阈值电压)，并存储在存储电容Cst中。存储电容Cst的第一极板和第二极板的电压分别为Vdata+Vth和Vdd；第一电容C1的第一极板和第二极板的电压分均为Vdata+Vth。
发光阶段(t3)：发光控制线EM写入低电平信号，扫描线Ga(A)与复位控制信号线Rst写入高电平信号，第一发光控制晶体管T5和第二发光控制晶体管T6均打开，驱动晶体管T3的源极与第一电源电压线VDD连接，驱动晶体管T3的源极电压由上一阶段的Vdata瞬时变化为Vdd。驱动晶体管 T3的漏极电压由上一阶段的Vdata+Vth变为Vdd+Vds，其中，Vdata的值取决于发光器件D待显示的灰阶值，Vds为驱动晶体管T3的源极和漏极之间的跨压，该电压值取决于发光器件D待显示的灰阶值所对应的驱动电流。在一些实施例中，Vds大约在-3V到-5V左右，Vth大约在-0.7V到-1.3V左右，而Vdd与Vdata的最大电压差不超过5V，(Vdd+Vds)-(Vdata+Vth)大约在1V左右，故在在第一电容C1的自举作用下，驱动晶体管T3的栅极电压与上一阶段的电压Vdata+Vth也仅变化了1V左右，近似为Vdata+Vth，也就是说，即使驱动晶体管T3的栅极和源极之间存在较大的耦合电容Cgs，在驱动晶体管T3的源极发生较大瞬时变化时，由于第一电容C1的存在，此时驱动晶体管T3的栅极电压也不会发生较大的瞬时变化。
另外，发光器件D在驱动晶体管T3的驱动下发光，此时驱动晶体管T3工作在饱和区，驱动晶体管T3的栅极电压为Vdata+Vth，驱动晶体管T3的源极电压为Vdd，故，驱动晶体管T3的栅源电压为：Vgs＝(Vdata+Vth)-Vdd，直到下一帧的复位阶段。
发光器件D的发光电流等于流过驱动晶体管T3的电流，其表达式如下：
I D＝β(Vgs-Vth) 2
＝β(Vdata+Vth-dd-Vth) 2
Figure PCTCN2020118279-appb-000002
如上述公式(1)所示，在发光阶段发光器件D的电流与驱动晶体管T3的阈值电压无关，从而避免驱动晶体管T3的阈值电压对显示面板的显示均一性造成影响。另外，下述表一和表二为发明人对本公开实施图7和相关技术图2所示的像素驱动电路的仿真结果。其中，Vg表示驱动晶体管T3的栅极电压，Id表示驱动晶体管T3的发光阶段产生的驱动电流。
Figure PCTCN2020118279-appb-000003
表一
Figure PCTCN2020118279-appb-000004
表二
具体的，由表一可以看出的是，图7和图2所示的的像素驱动电路图在发光阶段均驱动晶体管T3的栅极电压Vg为0.409V，驱动晶体管所产生的驱动电流Id为75.5μA时，也即在相同的电流(亮度)基准下，本公开实施例图4所示的像素驱动电路，由于增加了第一电容C1，因此较图2所示的像素驱动电路其可以选用相对较小的存储电容Cst，具体的图4所示的像素驱动电路中的C1为1.5pF时，存储电容Cst为1.53pF，而要达到相同的效果，图2所示的像素驱动电路则需要选用3.1pF的存储电容Cst。可以看出的是，应用本公开实施例的中像素驱动电路的显示面板的开口率和分辨率均能够有多提高。
由表二可以看出的是，当本公开实施图7和相关技术图2所示的像素驱动电路中存储电容Cst相同，由于公开实施图4所示的像素驱动电路中具有第一电容C1，在发光阶段驱动晶体管T3的栅极电压Vg受到的影响明显小于图2所示的像素驱动电路，而且公开实施图4所示的像素驱动电路的所产生的驱动电流明显大于图2所示的像素驱动电路。例如：本公开实施图4和相关技术图2所示的像素驱动电路中存储电容Cst均为3.1pF，第一电容为1.5pF，在发光阶段，图4所示的像素驱动电路的驱动晶体管T3的栅极电压 Vg为-0.116V，驱动电流Id为98.5；图2所示的像素驱动电路的驱动晶体管T3的栅极电压Vg为0.409V，驱动电流Id为75.5。
在一些实施例中，图9为本公开实施例的另一种像素驱动电路的示意图；如图9所示，该像素电路不仅包括上述的数据写入子电路4、阈值补偿子电路2、驱动子电路3、存储子电路8、第一电容C1、第一复位子电路1及第一发光控制子电路5；而且还包括时长控制子电路，该时长控制子电路被配置为响应于时间控制信号，并通过时间调制信号和第三发光控制信号控制待驱动的发光器件D的发光时间。这样一来，当驱动晶体管T3输出一定的电流时，则可以通过时间调制信号和第三发光控制信号，该驱动电路写入至发光器件D的时间，以实现不同灰阶的显示。
在一个示例中，继续参照图9，发光时长控制子电路10可以包括第一时间调制晶体管T8、第二时间调制晶体管T9、第三发光控制晶体管T10及第二电容C2；其中，第一时间调制晶体管T8的源极连接驱动晶体管T3的漏极，第一时间调制晶体管T8的漏极连接第三发光控制晶体管T10的源极，第一时间调制晶体管T8的栅极连接第三发光控制线EM3；第二时间调制晶体管T9的源极连接时间调制信号端Data-T，第二时间调制晶体管T9的漏极连接第三发光控制晶体管T10的栅极，第二时间调制晶体管T9的栅极连接时间控制信号线Ga(B)；第三发光控制晶体管T10的漏极连接待驱动的发光器件D的阳极，第三发光控制晶体管T10的栅极连接第二电容C2的第一极板；第二电容C2的第二极板连接公共电压端Vcom。
在一些实施例中，控制第三发光控制线EM3在一帧显示时间内被写入低电平的时长，如控制第三发光控制线EM3被写入的信号的占空比，以控第一时间调制晶体管T8导通时长，从而控制驱动晶体管T3输出至发光器件D的驱动电流的时长。
在一个示例中，第三发光控制线EM3被配置为在一帧显示时间内分多次被写入低电平信号，且每次被写入的低电平信号的时长不同。例如：第三发光控制线EM3在一帧显示时间内被写入低电平的次数为N，N为大于或 者2的整数，第三发光控制线EM3在第1至N次扫描周期被写入的低电平时间分别用t 1、t 2……t n表示，time 1＝T、time 2＝T/2……time N＝T/2 (N-1)，也即t (m-1)＝2t m，m取1到N的整数。在一帧显示时间内，时间控制信号线Ga(B)在第三发光控制线EM3的每一次扫描周期均会被写入一定时间的低电平信号，此时，对于每个像素而言，时间调制信号端Data-T所输入的低电平信号(有效电平)的次数p和该像素能够实现的发光时长的种类K的关系为：K＝2 p，1≤p≤N。而对于每个像素的发光时长则由时间调制信号端Data-T所输入的低电平信号(有效电平)的次数h和第1至N个扫描周期，第三发光控制线EM3被写入的低电平时间时长决定。可以看出的是，在本公开实施例中，由于增加了发光时长控制子电路10，可以实现对每个像素实现2 p种发光时长的控制。
在此需要说明的是，对于时间控制信号线Ga(B)第1次被写入低电平的时间，与数据写入及阈值补偿阶段扫描线Ga(A)被写入工作电平的时间存在部分交叠，也即Ga(B)第1次被写入低电平的时间的起始时间在数据写入及阈值补偿阶段。
继续参照图9，在该像素电路中，数据写入子电路4、阈值补偿子电路2、驱动子电路3、存储子电路8、第一复位子电路1及第一发光控制子电路5均可以与图2中所示的结构相同。同时，在本公开实施例中，以该像素电路中的数据写入子电路4、阈值补偿子电路2、驱动子电路3、存储子电路8、第一复位子电路1及第一发光控制子电路5均可以与图2中所示的结构相同为例进行说明。
需要说明的是，第一发光控制线EM1和第三发光控制线EM3所写入的控制信号可以相同，也就是说，第一时间调制晶体管T8的栅极和第一发光控制晶体管T5的栅极连接同一条发光控制线EM。当然，第一发光控制线EM1也可以与第三发光控制线EM3所写入的控制信号可以不同，例如在整个发光阶段给第一发光控制线EM1均写入低电平信号，也即在发光阶段第一发光控制晶体管T5一直处于开启状态。在本公开实施例中以第一发光控 制线EM1和第三发光控制线EM3所写入的控制信号相同，也即第一时间调制晶体管T8的栅极和第一发光控制晶体管T5的栅极连接一条发光控制线EM为例进行说明。
图10为图9所示的像素驱动电路的工作时序图；如图7和8所示，其中，以发光控制线EM在一帧显示时间内，时间调制信号端Data-T在time 1、time 2、time N三个扫描周期被写入低电平信号为例。
本公开实施例的像素驱动电路的驱动方法包括如下阶段：
复位阶段(t1)：复位控制信号线Rst写入低电平信号，扫描线Ga(A)和发光控制线EM写入高电平信号；第一复位晶体管T1打开，驱动晶体管T3栅极的被复位电源信号线Init写入的初始电压Vinit，为下一帧写入数据电压Vdata的写入做准备。
数据写入及阈值补偿阶段(t2)：扫描线Ga(A)写入为低电平信号，复位控制信号线Rst和发光控制线EM写入高电平信号；数据写入晶体管T4和阈值补偿晶体管T2打开。驱动晶体管T3被阈值补偿晶体管T2连成二极管结构，数据线Data上写入的数据电压通过数据写入晶体管T4和阈值补偿晶体管T2写入驱动晶体管T3的栅极，直到驱动晶体管T3截止。驱动晶体管T3的栅极电压为Vdata+Vth(Vth<0，Vth为驱动晶体管T3的阈值电压)，并存储在存储电容Cst中。存储电容Cst的第一极板和第二极板的电压分别为Vdata+Vth和Vdd；第一电容C1的第一极板和第二极板的电压均为Vdata+Vth。
发光阶段(t3)：在第1个扫描周期内，时间控制信号线Ga(B)被写入低电平，时间调制信号端Data-T输入低电平信号，发光控制线EM写入低电平信号的时间time 1＝T，扫描线Ga(A)与复位控制信号线Rst写入高电平信号，第一发光控制晶体管T5、第一时间调制晶体管T8、第二时间调制晶体管T9、第三发光控制晶体管T10均打开，发光器件D的在第一行扫描周期内的发光时长为T；在第2个扫描周期内，时间控制信号线Ga(B)被写入低电平，时间调制信号端Data-T输入低电平信号，发光控制线EM写入低电平信号的时 间time 2＝T/2，扫描线Ga(A)与复位控制信号线Rst写入高电平信号，第一发光控制晶体管T5、第一时间调制晶体管T8、第二时间调制晶体管T9、第三发光控制晶体管T10均打开，发光器件D的在第2个扫描周期内的发光时长为T/2；在第N个扫描周期内，时间控制信号线Ga(B)被写入低电平，时间调制信号端Data-T输入低电平信号发光控制线EM写入低电平信号的时间time N＝T/2 (n-1)，扫描线Ga(A)与复位控制信号线Rst写入高电平信号，第一发光控制晶体管T5、第一时间调制晶体管T8、第二时间调制晶体管T9、第三发光控制晶体管T10均打开，发光器件D的在第N个扫描周期内的发光时长为T/2 (n-1)；在第3行至第n-1行扫描周期时间调制信号端Data-T被写入高电平信号，第三发光控制晶体管T10关断，发光器件D不发光，也即在一帧显示时间该发光器件D的发光总时长为T+T/2+T/2 (n-1)。与此同时，在发光阶段驱动晶体管T3的源极与第一电源电压线VDD连接，驱动晶体管T3的源极电压由上一阶段的Vdata瞬时变化为Vdd。驱动晶体管T3的漏极电压由上一阶段的Vdata+Vth变为Vdd+Vds，其中，Vdata的值取决于发光器件D待显示的灰阶值，Vds为驱动晶体管T3的源极和漏极之间的跨压，该电压值取决于发光器件D待显示的灰阶值所对应的驱动电流。在一些实施例中，Vds大约在-3V到-5V左右，Vth大约在-0.7V到-1.3V左右，而Vdd与Vdata的最大电压差不超过5V，(Vdd+Vds)-(Vdata+Vth)大约在1V左右，(Vdd+Vds)-(Vdata+Vth)大约在1V左右，故在在第一电容C1的自举作用下，驱动晶体管T3的栅极电压与上一阶段的电压Vdata+Vth也仅变化了1V左右，近似为Vdata+Vth，也就是说，即使驱动晶体管T3的栅极和源极之间存在较大的耦合电容Cgs，在驱动晶体管T3的源极发生较大瞬时变化时，由于第一电容C1的存在，此时驱动晶体管T3的栅极电压也不会发生较大的瞬时变化。
另外，发光器件D在驱动晶体管T3的驱动下发光，此时驱动晶体管T3工作在饱和区，驱动晶体管T3的栅极电压为Vdata+Vth，驱动晶体管T3的源极电压为Vdd，故，驱动晶体管T3的栅源电压为：Vgs＝(Vdata+Vth)-Vdd， 直到下一帧的复位阶段。
发光器件D的发光电流等于流过驱动晶体管T3的电流，其表达式如下：
I D＝β(Vgs-Vth) 2
＝β(Vdata+Vth-dd-Vth) 2
Figure PCTCN2020118279-appb-000005
如上述公式(1)所示，在发光阶段发光器件D的电流与驱动晶体管T3的阈值电压无关，从而避免驱动晶体管T3的阈值电压对显示面板的显示均一性造成影响。
综上所述，本公开实施例中像素驱动电路中发光器件D在一图像帧内的有效发光亮度可以由一图像帧内扫描周期的个数、每个扫描周期的时长、第一数据电压Vdata_A、第二数据电压Vdata_B、发光控制信号线EM提供的发光控制信号多个因素决定，从而可以使得具有像素驱动电路的子像素显示的灰阶值更多，显示面板显示的画面更加的丰富、细腻。
第二方面，本发明实施例还提供一种显示面板，其包括上述的任意一种像素驱动电路，因此，本实施例的显示面板的显示效果较佳，且可以实现高分辨率的显示。
其中，显示面板可以为液晶显示装置或者电致发光显示装置，例如液晶面板、OLED面板、Micro LED面板，Mini LED面板，手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (21)

  1. 一种像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路、存储子电路及电压维持子电路；其中，
    所述数据写入子电路，被配置为响应于第一扫描信号，将数据电压信号传输至驱动子电路的第一端；
    所述阈值补偿子电路，被配置为响应于第二扫描信号，对所述驱动子电路的阈值电压进行补偿；
    所述存储子电路，被配置为对所述数据电压信号进行存储；
    所述驱动子电路，被配置为根据其第一端和控制端的电压为待驱动的发光器件提供驱动电流；
    所述电压维持子电路，被配置为在所述驱动子电路的第一端电压发生跳变时，维持所述驱动子电路的控制端电压。
  2. 根据权利要求1所述的像素驱动电路，其中，所述电压维持子电路包括第一电容，所述第一电容的第一极板连接所述驱动子电路的控制端，所述第一电容的第二极板连接所述驱动子电路的第二端。
  3. 根据权利要求1所述的像素驱动电路，其中，所述电压维持子电路包括第一电容，所述第一电容的第一极板连接所述驱动子电路的控制端，所述第一电容的第二极板连接参考电压端。
  4. 根据权利要求2或3所述的像素驱动电路，其中，所述第一电容的容值为0.1pF-10pF。
  5. 根据权利要求1-4中任一项所述的像素驱动电路，其中，还包括：
    第一发光控制子电路，被配置为响应于第一发光控制信号，控制第一电压是否能够被写入所述驱动子电路的第一驱动子电路的第一端。
  6. 根据权利要求5所述的像素驱动电路，其中，所述第一发光控制子电路包括第一发光控制晶体管；
    所述第一发光控制晶体管的第一极连接第一电源电压线，所述第一发光控制晶体管的第二极连接所述驱动子电路的第一端，所述第一发光控制晶体管的控制极连接第一发光控制线。
  7. 根据权利要求1-6中任一项所述的像素驱动电路，其中，还包括：
    第一复位子电路，被配置为响应于第一复位控制信号，并通过第一初始化信号对驱动子电路的控制端的电压进行复位。
  8. 根据权利要求7所述的像素驱动电路，其中，第一复位子电路包括第一复位晶体管；
    所述第一复位晶体管的第一极连接第一初始化信号端，所述第一复位晶体管的第二极连接所述驱动子电路的控制端，所述第一复位晶体管的控制极连接所述第一复位控制信号线。
  9. 根据权利要求1-8中任一项所述像素驱动电路，其中，还包括：
    第二发光控制子电路，被配置为响应于第二发光控制信号，导通或断开所述驱动子电路和所述待驱动的发光器件之间的连接。
  10. 根据权利要求9所述的像素驱动电路，其中，所述第二发光控制子电路包括第二发光控制晶体管；
    所述第二发光控制晶体管的第一极连接所述驱动子电路的第二端，所述第二发光控制晶体管的第二极连接所述待驱动的发光器件的第一电极，所述第二发光控制晶体管的控制极连接第二发光控制线。
  11. 根据权利要求1-10中任一项所述的像素驱动电路，其中，还包括：
    第二复位子电路，被配置为响应于第二复位控制信号，通过第二初始化信号对所述待驱动的发光器件进行初始化。
  12. 根据权利要求11所述的像素驱动电路，其中，所述第二复位子电路包括第二复位晶体管；
    所述第二复位晶体管的第一极连接所述待驱动的所述发光器件的第一电极，所述第二复位晶体管的第二极连接第二初始化信号端，所述第二复位 晶体管的控制极连接第二复位控制信号线。
  13. 根据权利要求1-8中任一项所述的像素驱动电路，其中，还包括：时间控制子电路，被配置为响应于时间控制信号，并通过时间调制信号和第三发光控制信号控制所述待驱动的发光器件的发光时间。
  14. 根据权利要求13所述的像素驱动电路，其中，所述时间控制子电路包括第一时间调制晶体管、第二时间调制晶体管、第三发光控制晶体管及第二电容；
    所述第一时间调制晶体管的第一极连接所述驱动子电路的第二端，所述第一时间调制晶体管的第二极连接所述第三发光控制晶体管的第一极，所述第一时间调制晶体管的控制极连接第三发光控制线；
    所述第二时间调制晶体管的第一极连接时间调制信号端，所述第二时间调制晶体管的第二极连接所述第三发光控制晶体管的控制极，所述第二时间调制晶体管的控制极连接时间控制信号线；
    所述第三发光控制晶体管的第二极连接待驱动的发光器件的第一电极，所述第三发光控制晶体管的控制极连接所述第二电容的第一极板；
    所述第二电容的第二极板连接公共电压端。
  15. 根据权利要求14所述的像素驱动电路，其中，所述第三发光控制线被配置为在一帧显示时间内分多次写入工作电平信号，且每次所写入的工作电平时长不等。
  16. 根据权利要求1-15中任一项所述的像素驱动电路，其中，所述驱动子电路包括驱动晶体管，所述阈值补偿子电路包括阈值补偿晶体管，所述数据写入子电路包括数据写入晶体管，存储子电路包括存储电容；
    所述驱动晶体管的第一极用作所述驱动子电路的第一端，所述驱动晶体管的第二极用作所述驱动子电路的第二端，所述驱动子电路的控制极用作所述驱动子电路的控制端；
    所述驱动晶体管的第一极连接所述数据写入晶体管的第二极，所述驱动晶体管的第二极连接所述阈值补偿晶体管的第一极，所述驱动晶体管的控制 极连接所述阈值补偿晶体管的第二极和所述存储电容的第一极板；
    所述数据写入晶体管的第一极连接数据线，所述数据写入晶体管的控制极连接第一扫描线；
    所述阈值补偿晶体管的控制极连接第二扫描线；
    所述存储电容的第二极板连接第一电源电压线。
  17. 根据权利要求16所述的显示基板，其中，所述存储电容的容值为0.1pF-10pF。
  18. 一种像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路、存储子电路、第一发光控制子电路、第二发光控制子电路、第一复位子电路、第二复位子电路及电压维持子电路；其中，
    所述驱动子电路包括驱动晶体管，所述阈值补偿子电路包括阈值补偿晶体管，所述数据写入子电路包括数据写入晶体管，存储子电路包括存储电容，所述第一发光控制子电路包括第一发光控制晶体管，所述第二发光控制子电路包括第二发光控制晶体管，所述第一复位子电路包括第一复位晶体管，所述第二复位子电路包括第二复位晶体管，所述电压维持子电路包括第一电容；
    所述驱动晶体管的第一极连接所述数据写入晶体管的第二极和所述第一发光控制晶体管的第二极，所述驱动晶体管的第二极连接所述阈值补偿晶体管的第一极，所述驱动晶体管的控制极连接所述阈值补偿晶体管的第二极、所述存储电容的第一极板和所述第一电容的第一极板；
    所述数据写入晶体管的第一极连接数据线，所述数据写入晶体管的控制极连接第一扫描线；
    所述阈值补偿晶体管的控制极连接第二扫描线；
    所述存储电容的第二极板连接第一电源电压线；
    所述第一发光控制晶体管的第一极连接第一电源电压线，所述第一发光控制晶体管的控制极连接第一发光控制线；
    所述第二发光控制晶体管的第一极连接所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接所述待驱动的发光器件的第一电极，所述第二发光控制晶体管的控制极连接第二发光控制线；
    所述第一复位晶体管的第一极连接第一初始化信号端，所述第一复位晶体管的第二极连接所述驱动晶体管的控制极，所述第一复位晶体管的控制极连接所述第一复位控制信号线；
    所述第二复位晶体管的第一极连接所述待驱动的所述发光器件的第一电极，所述第二复位晶体管的第二极连接第二初始化信号端，所述第二复位晶体管的控制极连接第二复位控制信号线；
    所述第一电容的第二极板连接所述驱动晶体管的第二电极或者参考电压端。
  19. 一种像素驱动电路，其包括：数据写入子电路、阈值补偿子电路、驱动子电路、存储子电路、第一发光控制子电路、第一复位子电路、时间控制子电路及电压维持子电路；其中，
    所述驱动子电路包括驱动晶体管，所述阈值补偿子电路包括阈值补偿晶体管，所述数据写入子电路包括数据写入晶体管，存储子电路包括存储电容，所述第一发光控制子电路包括第一发光控制晶体管，所述第二发光控制子电路包括第二发光控制晶体管，所述第一复位子电路包括第一复位晶体管，所述第二复位子电路包括第二复位晶体管，所述时间控制子电路包括第一时间调制晶体管、第二时间调制晶体管、第三发光控制晶体管及第二电容，所述电压维持子电路包括第一电容；
    所述驱动晶体管的第一极连接所述数据写入晶体管的第二极和所述第一发光控制晶体管的第二极，所述驱动晶体管的第二极连接所述阈值补偿晶体管的第一极，所述驱动晶体管的控制极连接所述阈值补偿晶体管的第二极、所述存储电容的第一极板和所述第一电容的第一极板；
    所述数据写入晶体管的第一极连接数据线，所述数据写入晶体管的控制极连接第一扫描线；
    所述阈值补偿晶体管的控制极连接第二扫描线；
    所述存储电容的第二极板连接第一电源电压线；
    所述第一发光控制晶体管的第一极连接第一电源电压线，所述第一发光控制晶体管的控制极连接第一发光控制线；
    所述第一复位晶体管的第一极连接第一初始化信号端，所述第一复位晶体管的第二极连接所述驱动晶体管的控制极，所述第一复位晶体管的控制极连接所述第一复位控制信号线；
    所述第一时间调制晶体管的第一极连接所述驱动晶体管的第二极，所述第一时间调制晶体管的第二极连接所述第三发光控制晶体管的第一极，所述第一时间调制晶体管的控制极连接第三发光控制线；
    所述第二时间调制晶体管的第一极连接时间调制信号端，所述第二时间调制晶体管的第二极连接所述第三发光控制晶体管的控制极，所述第二时间调制晶体管的控制极连接时间控制信号线；
    所述第三发光控制晶体管的第二极连接待驱动的发光器件的第一电极，所述第三发光控制晶体管的控制极连接所述第二电容的第一极板；
    所述第二电容的第二极板连接公共电压端。
  20. 一种显示面板，其包括多个像素单元，所述多个像素单元中的每个包括像素驱动电路和发光器件；其中，所述像素驱动电路包括权利要求1-19中任一项所述的像素驱动电路。
  21. 根据权利要求20所述的显示面板，其中，所述发光器件包括：微型无机发光二极管。
PCT/CN2020/118279 2020-09-28 2020-09-28 像素驱动电路及显示面板 WO2022061852A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US17/309,917 US11798473B2 (en) 2020-09-28 2020-09-28 Pixel driving circuit and display panel
PCT/CN2020/118279 WO2022061852A1 (zh) 2020-09-28 2020-09-28 像素驱动电路及显示面板
CN202080002144.4A CN114586091B (zh) 2020-09-28 2020-09-28 像素驱动电路及显示面板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/118279 WO2022061852A1 (zh) 2020-09-28 2020-09-28 像素驱动电路及显示面板

Publications (1)

Publication Number Publication Date
WO2022061852A1 true WO2022061852A1 (zh) 2022-03-31

Family

ID=80844848

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/118279 WO2022061852A1 (zh) 2020-09-28 2020-09-28 像素驱动电路及显示面板

Country Status (3)

Country Link
US (1) US11798473B2 (zh)
CN (1) CN114586091B (zh)
WO (1) WO2022061852A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023005597A1 (zh) * 2021-07-30 2023-02-02 京东方科技集团股份有限公司 像素驱动电路及显示面板

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112785972A (zh) * 2021-03-08 2021-05-11 深圳市华星光电半导体显示技术有限公司 发光器件驱动电路、背光模组以及显示面板
CN115668344B (zh) * 2021-04-21 2025-04-25 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板及其驱动方法
CN115101011B (zh) 2021-07-21 2024-12-13 武汉天马微电子有限公司 配置成控制发光元件的像素电路
KR20230102364A (ko) * 2021-12-30 2023-07-07 엘지디스플레이 주식회사 시야각 전환 표시장치
DE112022007459T5 (de) * 2022-06-30 2025-04-17 Boe Technology Group Co., Ltd. Pixeltreiberschaltung, Antriebsverfahren für Pixeltreiberschaltung, und Anzeigefeld
CN115312002B (zh) * 2022-06-30 2023-08-18 惠科股份有限公司 像素驱动电路、显示面板及显示装置
WO2024043558A1 (ko) 2022-08-23 2024-02-29 삼성디스플레이주식회사 표시장치
CN115966180B (zh) * 2023-01-03 2025-07-15 京东方科技集团股份有限公司 显示画面切换残影补偿方法、像素驱动电路及显示基板
US12300173B2 (en) * 2023-01-19 2025-05-13 Hefei Boe Joint Technology Co., Ltd. Pixel circuit, display panel and display apparatus
CN116434701A (zh) * 2023-04-27 2023-07-14 云谷（固安）科技有限公司 像素电路、驱动方法及显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700338A (zh) * 2012-09-27 2014-04-02 乐金显示有限公司 像素电路及其驱动方法及采用该电路的有机发光显示装置
CN109166528A (zh) * 2018-09-28 2019-01-08 昆山国显光电有限公司 像素电路及其驱动方法
CN110491335A (zh) * 2019-09-03 2019-11-22 京东方科技集团股份有限公司 一种驱动电路及其驱动方法、显示装置
CN111247579A (zh) * 2018-09-11 2020-06-05 株式会社矽因赛德 用于完全消除驱动PMOS阈值电压的干扰的控制μLED像素结构方法
CN111292683A (zh) * 2020-02-13 2020-06-16 鄂尔多斯市源盛光电有限责任公司 阵列基板及其制备方法、显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITMI20070100A1 (it) * 2007-01-24 2008-07-25 St Microelectronics Srl Circuito di pilotaggio di un diodo oled (diodo organico ed emissione di luce), in particolare per applicazione a display di tipo am-oled
CN105427809B (zh) * 2016-01-04 2020-11-03 京东方科技集团股份有限公司 像素补偿电路及amoled显示装置
CN107256690B (zh) * 2017-07-31 2019-11-19 上海天马有机发光显示技术有限公司 一种电致发光显示面板、其驱动方法及显示装置
CN108877674A (zh) * 2018-07-27 2018-11-23 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN111445858B (zh) * 2020-04-20 2024-09-03 昆山国显光电有限公司 像素电路及其驱动方法、显示装置
KR102783671B1 (ko) * 2020-05-11 2025-03-20 삼성디스플레이 주식회사 유기 발광 표시 장치의 화소, 및 유기 발광 표시 장치
KR20220002790A (ko) * 2020-06-30 2022-01-07 삼성디스플레이 주식회사 화소 및 유기 발광 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700338A (zh) * 2012-09-27 2014-04-02 乐金显示有限公司 像素电路及其驱动方法及采用该电路的有机发光显示装置
CN111247579A (zh) * 2018-09-11 2020-06-05 株式会社矽因赛德 用于完全消除驱动PMOS阈值电压的干扰的控制μLED像素结构方法
CN109166528A (zh) * 2018-09-28 2019-01-08 昆山国显光电有限公司 像素电路及其驱动方法
CN110491335A (zh) * 2019-09-03 2019-11-22 京东方科技集团股份有限公司 一种驱动电路及其驱动方法、显示装置
CN111292683A (zh) * 2020-02-13 2020-06-16 鄂尔多斯市源盛光电有限责任公司 阵列基板及其制备方法、显示装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023005597A1 (zh) * 2021-07-30 2023-02-02 京东方科技集团股份有限公司 像素驱动电路及显示面板
US12230182B2 (en) 2021-07-30 2025-02-18 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel circuit and driving method therefor, display substrate, and display apparatus
US12236831B2 (en) 2021-07-30 2025-02-25 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel driving circuit and display panel
US12236829B2 (en) 2021-07-30 2025-02-25 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel driving circuit and driving method thereof, and display panel
US12260799B2 (en) 2021-07-30 2025-03-25 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel circuit, driving method thereof and display device

Also Published As

Publication number Publication date
US11798473B2 (en) 2023-10-24
US20220319417A1 (en) 2022-10-06
CN114586091A (zh) 2022-06-03
CN114586091B (zh) 2024-03-19

Similar Documents

Publication Publication Date Title
WO2022061852A1 (zh) 像素驱动电路及显示面板
JP7693740B2 (ja) 画素回路、駆動方法、電界発光表示パネル及び表示装置
US11881176B2 (en) Pixel circuit, display panel, display device, and driving method
JP7495031B2 (ja) 画素回路、画素回路の駆動方法及び表示装置
US10978002B2 (en) Pixel circuit and driving method thereof, and display panel
CN107316613B (zh) 像素电路、其驱动方法、有机发光显示面板及显示装置
US11232749B2 (en) Pixel circuit and driving method thereof, array substrate, and display device
WO2023005695A1 (zh) 像素电路及其驱动方法、显示面板
CN104680980B (zh) 像素驱动电路及其驱动方法、显示装置
TWI696990B (zh) 像素驅動電路及其驅動方法和電晶體的版圖結構
CN107452338B (zh) 一种像素电路、其驱动方法、显示面板及显示装置
WO2019037499A1 (zh) 像素电路及其驱动方法、显示装置
WO2023005597A1 (zh) 像素驱动电路及显示面板
CN112352274B (zh) 像素补偿电路、显示面板、驱动方法及显示装置
CN109949739B (zh) 一种像素电路、驱动方法及显示器
CN105405395B (zh) 一种像素结构、其驱动方法及相关显示装置
CN113851082B (zh) 像素驱动电路及其驱动方法、显示面板
CN106067291A (zh) 一种像素驱动电路及其驱动方法、显示装置
CN106971691A (zh) 一种像素电路、驱动方法及显示装置
WO2022099508A1 (zh) 像素驱动电路及显示面板
US10140922B2 (en) Pixel driving circuit and driving method thereof and display device
GB2620507A (en) Pixel circuit and driving method therefor and display panel
WO2019047701A1 (zh) 像素电路及其驱动方法、显示装置
WO2024021465A1 (zh) 像素驱动电路和显示面板
CN107103882A (zh) 一种像素电路、其驱动方法及显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20954703

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20954703

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 26.01.2024)

122 Ep: pct application non-entry in european phase

Ref document number: 20954703

Country of ref document: EP

Kind code of ref document: A1